Reconfigurable computing architecture exploration using silicon photonics technology

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1 Reconfigurable computing architecture exploration using silicon photonics technology Zhen Li To cite this version: Zhen Li. Reconfigurable computing architecture exploration using silicon photonics technology. Other. Ecole Centrale de Lyon, 5. English. <NNT : 5ECDL>. <tel-564> HAL Id: tel Submitted on 3 May 5 HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

2 N d ordre : 5- Année : 5 THESE délivré par L ECOLE CENTRALE DE LYON Spécialité : Electronique, micro et nano-électronique, optique et laser Présentée et soutenue publiquement par Zhen LI Préparé à l Institut des Nanotechnologies de Lyon (INL), UMR CNRS 57 RECONFIGURABLE COMPUTING ARCHITECTURE EXPLORATION USING SILICON PHOTONICS TECHNOLOGY Ecole Doctoral E.E.A «Electronique, Electrotechnique, Automatique» de Université de Lyon Sera soutenue le 8 janvier 5 devant la Commission d Examen Jury : M.Peter Bienstman Associate Professeur, Ghent University Rapporteur M.Lionel Torres Professeur, Univ.de Montpellier Rapporteur M.Yannick Dumeige HDR, Univ.de Rennes Examinateur M.Jacques-Olivier Klein Professeur, Université Paris-Sud XI Examinateur M.Sébastien Le Beux Maitre de conférence, ECL Examinateur Mme.Christelle Monat Maitre de conférence, ECL Examinateur M.Xavier Letartre Directeur de recherche, CNRS Examinateur M.Ian O'Connor Professeur, ECL Directeur de thèse

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4 REMERCIEMENTS Tout d abord, je tiens à remercier Peter Bienstman et Lionel Torres pour avoir joué le role essentiel de rapporteurs de cette thèse, en lisant avec sérieux et indulgence ce manuscrite «double-disciplinaire». Peter et Lionel a aussi contribué grandement non seulement à l amélioration de l architecture je proposé, et encore à reconsidérer ce travail sous un autre horizon. Je joins à ces remerciements Jacques-Olivier Klein et Yannick Dumeige pour avoir ajouté des visions différentes à la variété des compétences de mon jury et aussi pour leurs remarques, questions et conseils lors de ma présentation. Les quatres personnes restant du jury ont contribué plus intensément à la réussite de cette thèse, mon directeur de thèse Ian O Connor, avec Sébastien Le Beux, Christelle Monat et Xavier Letartre. Je tiens à exprimer ma profonde gratitude envers cette équipe d encadrement «fantastique» et «croisé le monde du système et du photonique», pour m avoir encadré, accompagné, conseillé et soutenu tout au long de ma thèse, pour leur aides scientifiques, organisationnelles et énormément encouragements à défendre mes idées et suivre le chemin je choisie, pour l ensemble de nos échanges stimulants, de nos débats agreables et passionants ainsi que pour ces nombreuses relecteurs de ce manuscrite. Je voudrais remercier Guy Hollinger (directeur de l INL), Catherine Bru-Chevallier (directrice INL) et Christian Seassal (directeur adjoint INL, résponsable site-ecl) pour m avoir accueillie au sein de l INL et m avoir permis d effectuer cette thèse dans ses murs. Bien sûr, Xavier a joué un rôle essentiel qui est un peu comme «le roi physique» dans ces traveaux de thèse. Combien de fois j ai pu apprécier de discuter avec toi des problèmes épineux et mes questions à la fois «informé» et «inprécisé», et l ésprit prolifique de sortir un solution élégant et satisfaite (plus qu un compromis) pour des choses compliqués. Souvent je me sens plutot comme jouer un petit jeu de raisonnement avec toi, avec les échos «et alors» «et alors» «mais c est bien sur» ou «on sent fou», on a trouvé finalment c était tout simple! J espère vraiment que je me montrerai aussi l ésprit que toi dans ma carrière de recherche de futur. Egalement, Christelle est aussi joué un rôle comme «mère optique» dans mes traveaux. Toujours vivant, jamais à dire «oui» facilement sans une réflexion profondu pour i

5 tous ce que je t ai parlé et proposé, tu es toujours curieuse et passionné à apprendre les nouveaux (plus que du côte physique, mais aussi du système), à décourir des petits choses intéréssantes, à tenir les détails au cœur et pu faire le lien entre eux quand t a besoin (par exemple, pour me montrer les choses bizzares ou inraisonnables qui sont dans un coin caché de ma thèse). Pour ces moments, le mieux je peux faire est de te dire «je ne sais pas, et je vais le bien vérifier après». Mais plus qu une perfectionniste et parfois «exigente» en science, tu es aussi très attentive et tolérante, je ne sais plus combien de fois je suis ému que tu tiens sur ma position à considérer et/ou à montré un autre angle sur mes idées et mes traveaux. Tu es le premier exemple du chercheur accompli qui me vienne à l esprit. Egalement, Sébastien prends le rôle comme «boss système». C est vraiment difficile à croire que tu as des imaginations si riches et tu as pu inspirer des belles idées chaque fois qu on échange et discute. J ai encore bien du mal à réaliser comment tu parviens d avoir le grande vue en même temps n oublier pas tous les petites détails, parfois je ne sais pas comment te faire plaisir quand tu m a dit «c est pas claire». Mais ce qui est précieuse pour moi, c est tu m as parlé souvent la difficulté sur ce sujet multi-disciplinaire qui est entre le système et physique (la communication, la compromis), surtout quand on n étais pas content sur les résultats, ta tolérence et personnalité fait toi comme «mon frère». Et finalement j ai eu la chance d avoir Ian, le meilleur directeur de la thèse, cette thèse n aurait pas pu voir le jour sans l implication de toi. Je n a pas pu de trouver un mot ou une phrase pour merci ton support, tes encouragements, tes idées, tes temps, ta compherension tu es le «père» de ma vie de la science. Je tiens aussi à mentioner le plaisir que j ai eu à travailler au sein de l équipe conception et l équipe nanophotonique et j en remercie ici tous les membres. Merci également auxadministrateurs systèmes (Laurent Carrel et Rapheal Lopez) et aux secrétaires (Sylvie, Patricia), qui font un travail formidable pour le labo. Je passe ensuite une dédicace spéciale à tous les jeunes que j ai eu plaisir de cotôyer durant ces quelques années à INL, à savoir Felipe Frantz, Barakat Jean-Baptiste, Zhu Nanhao, Feng Zhengfu, Yang Zhugeng, Sui Ning, Zhang Taiping, Meng Xianqing, Liu Huanhuan, Yin Shi, Liu Qiang, Ding He, Li Hui, Guan Xin, Shi Liu J ai aussi voulu remercier ceux qui sont déjà repartis qui m a partagé des moments inoubliables dans la vie à Ecully, Tianli Huang, Yu Zhang, Meng Jie, Merci égalment à tous mes amis qui, bien que souvent à ii

6 distance, m ont soutenu au cours de cette aventure : Tang Qingshan, Ning Baozhu, Bing jingyi, Shi Peiluo, Wang Weijia Enfin, je souhaiterais remercier l ensemble de ma famille pour m avoir soutenu au cours de ma thèse, mon père, ma copine et mes frères et mes sœurs. Et merci maman au ciel, tu m appris heureux, courage, dignité, je sens ta presence chaque jours. «Pour ma maman au ciel, Le paradis est sous tes pieds» iii

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8 RESUME Les progrès dans la fabrication des systèmes de calcul reconfigurables de type «Field Programmable Gate Arrays» (FPGA) s appuient sur la technologie CMOS, ce qui engendre une consommation des puces élevée. Des nouveaux paradigmes de calcul sont désormais nécessaires pour remplacer les architectures de calcul traditionnel ayant une faible performance et une haute consommation énergétique. En particulier, optique intégré pourrait offrir des solutions intéressantes. Beaucoup de travail sont déjà adressées à l utilisation d interconnexion optique pour relaxer les contraintes intrinsèques d interconnexion électronique. Dans ce contexte, nous proposons une nouvelle architecture de calcul reconfigurable optique, la «optical lookup table» (OLUT), qui est une implémentation optique de la lookup table (LUT). Elle améliore significativement la latence et la consommation énergétique par rapport aux architectures de calcul d optique actuelles tel que RDL («reconfigurable directed logic»), en utilisant le spectre de la lumière au travers de la technologie WDM. Nous proposons une méthodologie de conception multi-niveaux permettant l'explorer l espace de conception et ainsi de réduire la consommation énergétique tout en garantissant une fiabilité élevée des calculs (BER~ -8 ). Les résultats indiquent que l OLUT permet une consommation inférieure à fj/opération logique, ce qui répondait en partie aux besoins d un FPGA tout-optique à l avenir. v

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10 ABSTRACT Advances in the design of high performance silicon chips for reconfigurable computing, i.e. Field Programmable Gate Arrays (FPGAs), rely on CMOS technology and are essentially limited by energy dissipation. New design paradigms are mandatory to replace traditional, slow and power consuming, electronic computing architectures. Integrated optics, in particular, could offer attractive solutions. Many related works already addressed the use of optical on-chip interconnects to help overcome the technology limitations of electrical interconnects. Integrated silicon photonics also has the potential for realizing high performance computing architectures. In this context, we present an energy-efficient on-chip reconfigurable photonic logic architecture, the so-called OLUT, which is an optical core implementation of a lookup table. It offers significant improvement in latency and power consumption with respect to optical directed logic architectures, through allowing the use of wavelength division multiplexing (WDM) for computation parallelism. We proposed a multilevel modeling approach based on the design space exploration that elucidates the optical device characteristics needed to produce a computing architecture with high computation reliability (BER~ -8 ) and low energy dissipation. Analytical results demonstrate the potential of the resulting OLUT implementation to reach < fj/bit per logic operation, which may meet future demands for on-chip optical FPGAs. vii

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12 RESUME FRANCAIS. Introduction A l'ère de l'explosion des données, les systèmes de calcul sont un facteur clé pour l innovation des technologies de l'informatique et de la communication. En raison des besoins sans-cesse croissantes en puissance de calcul, en rentabilité économique, et en efficacité énergétique, les méthodes traditionnelles reposant sur une évolution incrémentale des architectures de calcul ne suffisent plus ; des nouveaux paradigmes de calcul s appuyant sur de nouvelles technologies sont désormais nécessaires pour relever les défis énergétiques et de performance. ITRS (the International Technology Roadmap for Semiconductors) prédit que les interconnexions électriques ne seront plus capables de supporter les échanges de données ultrarapides dans les systèmes de calcul parallèle (e.g. système sur puce multiprocesseurs, MPSoC), du fait de leurs faibles efficacités énergétiques et de leur faible bande passante. L optique intégrée sur puce fait partie des alternatives susceptibles de répondre aux besoins en vitesse et en faible consommation des circuits intégrés (IC), cela en leur conférerant davantage de fiabilité. En effet, selon [] and [7], l optique permet d augmenter la bande passante, de diminuer la latence et la consommation associée aux interconnexions. De plus, la compatibilité de l optique avec les procédés de fabrication traditionnels CMOS permet de réduire fortement les couts de développements et de fabrication tout en garantissant un accès aux techniques d'assemblage hautement intégrés. Au-delà de l'utilisation de la photonique sur silicium pour la réalisation d interconnexions dans les architectures multi-processeurs, cette technologie peut également être exploitée pour effectuer des calculs en tout-optique, bénéficiant ainsi des avantages intrinsèques de la lumière, cad une bande passante élevée et une consommation énergétique plus faible. Cependant, il est illusoire de penser que l'optique peut directement concurrencer l'électronique dans les système de calcul en raison de son immaturité technologique, qui induit naturellement des problèmes d'intégration, de fiabilité et de coût de fabrication. Une première étape consiste donc à rendre l'optique utile dans des fonctions de niche, cela afin d améliorer les futurs systèmes de calcul. Cela nécessite de repenser et d imaginer de nouvelles ix

13 architectures de calcul adaptés à l optique et capable de tirer profit de ses bonne propriété [3]. Une feuille de route permettant de développer des architectures de calcul exploitant l optique peuvent être résumés ainsi: a) le calcul doit rester autant que possible dans le domaine optique afin de limiter l'utilisation d'interfaces électro-optiques couteuse; b) le spectre de la lumière doit être utilisés via le multiplexage en longueurs d onde («wavelength division multiplexing», WDM) afin de représenter et traiter l'information de manière efficace et compacte; c) l architecture optique doit être reconfigurable pour permettre plus de flexibilité et d adaptabilité selon les applications traitées; d) l'optique doit permettre d améliorer l'efficacité énergétique des systèmes de calcul. Dans cette thèse, nous proposons une nouvelle architecture de calcul optique, la «Optical LookUp table» (OLUT), qui est une implémentation optique de la Lookup table (LUT). Les progrès dans la fabrication des systèmes de calcul reconfigurables de type «field programmable gate arrays» (FPGA) s appuient sur la technologie CMOS, ce qui engendre une consommation des puces élevée. Dans la mesure où la technologie CMOS approche de ses limites fondamentales, l approche classique visant à densifier les ressources de calculs au sein des FPGAs mènera à des puissances surfaciques élevées qui ne pourront être réduite que par une limitation de l activité. Continuer à réduire le nombre de pj/bits avec chaque génération de technologie n est donc plus possible. La photonique sur silicium, quant à elle, a le potentiel pour franchir cette barrière énergétique et augmenter le rapport performances/puissance des FPGAs, permettant ainsi de réduire l'écart entre FPGAs et ASICs. L'architecture OLUT proposée permet d accélérer les calculs en utilisant le spectre de la lumière au travers de la technologie WDM. Elle améliore significativement la latence et la consommation énergétique par rapport aux architectures de calcul d optique actuelles tel que RDL («reconfigurable directed logic»). Nous proposons une méthodologie de conception multi-niveaux permettant l'explorer l espace de conception et ainsi de réduite la consommation énergétique tout en garantissant une fiabilité élevée des calculs (BER ~ -8 ). Les résultats indiquent que l OLUT permet une consommation inférieure à fj par bit, ce qui répondait en partie aux besoins d un FPGA tout-optique. Objectifs et plan de la thèse Le travail décrit dans cette thèse a pur but d aider à la conception d'une nouvelle architecture de calcul reconfigurable reposant sur la photonique de silicium. Ce travail se situe x

14 à la frontière entre des domaines de la conception de systèmes de calcul et de la modélisation de dispositifs photoniques. Le plan de cette thèse est le suivant: Le chapitre introduit les systèmes de traitement de l'information et offre un aperçu des défis technologiques liés à l'utilisation de la technologie optique pour les communications dans les systèmes sur puce électroniques. Il retrace ensuite l'évolution du calcul optique et résumé les raisons de ses échecs pour sa diffusion. Enfin, ce chapitre identifie le rôle que pourrait jouer l optique dans les systèmes de calcul en tirant profit des ses bonnes propriétés. Le chapitre identifie les principaux types d'architectures de calcul existant et leurs limites actuels ou à venir pour répondre aux défis de la réduction de la consommation d'énergie et de l augmentation de la puissance de calcul. Il présente ensuite les tendances actuelles liées à l utilisation des technologies émergentes pour la mise en œuvre des architectures de calcul reconfigurables, tels que la technologie 3-D, les nano-mémoires et l optique. Un état de l art portant sur les architectures de calcul optiques est ensuite adressé. Le chapitre 3 décrit le principe de fonctionnement de l OLUT. Dans un premier temps, une implémentation optique équivalente à la LUT électrique est décrite. Nous montrons ensuite comment le WDM est avantageusement utilisé pour réaliser des calculs en parallèles, ce qui permet d aboutir à une OLUT avec plusieurs sorties. Le principe de filtrage en longueurs d onde des OLUTs y est ensuite détaillé. Une évaluation préliminaire de gains potentiels de l OLUT est ensuite réalisée via l exemple de l additionneur complet -bit. Dans la dernière partie, les sorties sont dupliquées afin de densifier plus encore les calculs. Cela est réalisé par le biais de sorties complémentaire, qui permettent d effectuer simultanément le calcul d une fonction logique et de son complément. Le chapitre 4 propose une mise en œuvre des OLUTs reposant sur une technologie photonique sur silicium existante. Il est consacré à la modélisation multi-niveaux de l OLUT, partant de sa brique de base principal qu est un filtre «add-drop» contrôlé électriquement. Il sert de base à l'évaluation des performances et de la consommation de l OLUT au niveau du système. Pour cela, la transmission du filtre «add-drop» est étudiée dans les régimes passifs et actifs, cela en utilisant la théorie des modes couplés. Nous avons exploré plusieurs schémas de modulation des signaux optiques sous la commande électrique, en prenant en compte les porteurs au travers d une jonction PIN. Les pertes optiques se produisant dans le layout du circuit photonique du système OLUT sont ensuite étudiés. Enfin, le modèle d énergétique complet est décrit. xi

15 Le chapitre 5 présente les résultats d évaluation de performance de l OLUT en utilisant la méthodologie de conception multi-niveaux décrite dans le chapitre 4. Dans la première partie, la consommation d énergie de l OLUT est évaluée en explorant l'espace de conception des filtres «add-drop». L'impact des dimensions d'entrée et de sortie d OLUT sur son efficacité énergétique est étudié. La deuxième partie quantifie les gains de l OLUT avec les sorties complémentaires sur les performances de calcul et l'efficacité énergétique. La surface sur silicium et la puissance de laser optique d entrée sont ensuite analysés. Le chapitre 6 conclut la thèse et donne les perspectives de l OLUT. En particulier, une OLUT tout-optique reposant sur les interfaces d'entrée et de sortie tout-optique est proposée, ce qui permet de passer à l échelle et de traiter des fonctions de calcul plus complexes.. Utilisé la technologie optique dans les systèmes de calcul reconfigurables Les solutions optiques ont été proposées pour réaliser les interconnexions sur puce et les interfaces d'entrée/sortie (I/O) à haut débit, qui pourrait potentiellement influencer significative le domaine de FPGA. Ils se concentrent sur l'augmentation de la bande passante d'interconnexion en diminuant l'énergie par bit pour relaxer les limites intrinsèques imposées par des pertes élevées dans les interconnexions électriques. Il a aussi promesse de rendre les implémentations économique en tirant profit de bonne propriété de l optique. Bien que ce ne soit pas encore mature, des progrès importants continuent d'être reportés sur cette technologie. Par exemple, Altera a démontré une interface optique en intégrant des lasers et des photodétecteurs actuelle sur son FPGA en. La figure illustre l'architecture de ce FPGA avec les interfaces optiques associées. Ce FPGA est intégré avec des sous-assemblées d émetteurs optiques («TOSAS») et sous-assemblées des récepteurs optiques («ROSAS»), tels que les liens de puce-à-puce entre les FPGAs peuvent être mise en œuvre au travers des fibres optiques à haut débit au lieu de fils électriques. Cette interface optique donne un taux de données maximum de 8Gbps sur le nœud de processus de 8nm, et probablement il peut augmenter jusqu au 4 Gbps sur le noeud de nm ou 4nm. xii

16 Fig. Une architecture de FPGA optique proposé par Altera[5] La «Directed logic» (DL) est une architecture proposée pour réaliser du «supercomputing» optique. Elle améliore la latence de calcul par rapport aux circuits électronique en utilisant un réseau de commutateurs optiques interconnectés. L architecture DL a évolué avec les progrès technologiques récents de la photonique sur silicium, et en particulier les modulateurs d anneau silicium. Une preuve de concept reposant sur des résonateurs en anneau en cascade a été démontrée expérimentalement. Des améliorations significatives dans la reconfigurabilité et le passage à échèlle ont été apportées par l architecture reconfigurable DL (RDL). Une implémentation de l architecture RDL constitués d une matrice par de interrupteurs a permit d obtenir une vitesse de calcul de.5gbits/s. Dans RDL, des fonctions logiques sont écrites sous la forme d une somme de produits, qui sont généralement implémentées dans le circuit photonique via un réseau complet de type «cross-bar». Ce circuit est constitué de micro-résonateurs électriquement contrôlés, ce qui aboutit à des coûts d implémentation relativement élevés et des consommations énergétiques trop importantes. De plus, l architecture RDL ne tire pas profit du WDM, qui est pourtant un intérêt majeur de la photonique pour le calcul parallèle et l efficacité énergétique. La capacité de calcul des FPGAs s appuie sur la petite taille et le grand nombre de LUTs. En électronique, une n-lut prend n bits de donnée en entrée et fournit bit de donnée en sortie, c'est-à-dire qu une seule opération est effectuée à chaque cycle. Plusieurs n-luts doivent donc être mise en parallèle pour réaliser des calculs différents sur un même ensemble d entrées. Dans cette thèse, nous proposons une implémentation optique de la LUT, que nous appelons OLUT. Au lieu de multiplexer des signaux électriques et de changer l état de transistors comme dans une LUT, l OLUT route des signaux optiques au travers d un réseau de «démultiplexage» constitué de guides d ondes et de commutateurs électro-optiques, selon un chemin spécifié par les données d entrée. En utilisant le WDM, une OLUT avec m opérations (càd une n-m-olut) interface n bits de données d entrée avec m bits de données de sortie, en utilisant m signaux optiques aux longueurs d onde distincts (λ,..., λ m- ), chacune réalisant un calcul. De cette manière, les OLUTs permettent d augmenter la capacité de calcul par rapport aux LUTs traditionnelles, profitant ainsi des avantages de la technologie photonique sur silicium. 3. Présentation de l architecture de l OLUT De la LUT électrique à la LUT optique xiii

17 Les OLUTs sont inspirées directement de la LUTs électriques. Une LUTà n entrées interface n données d entrée et donnée de sortie à partir de la configuration stockée dans les n bits de mémoire statique SRAM. Le calcul est réalisé en récupérant le résultat de l opération stockée dans la mémoire spécifique à laquelle on accède à partir de l état des données d entrée. La Fig.(a) montre un layout du circuit associé à une -LUT électrique. Il est construit à partir de 4 bits de mémoire et d un multiplexeur 4:. Les LUTs sont utilisés dans les FPGA électriques, en raison de leur temps de calcul constant et de leur capacité à réaliser toutes les fonctions booléennes selon l'état de configuration des SRAM, ce qui conduit à la réalisation d architectures hautement flexibles et reconfigurables. Le schéma d une -OLUT qui fonctionne comme l équivalent d une -LUT électrique, est présenté sur la Fig.(b). La -OLUT utilise un signal optique à la longueur d onde λ, comme l équivalent d une alimentation électrique. L OLUT possède ses données d'entrée et de sortie sous forme électrique. De façon similaire à la LUT électrique, l OLUT est composée de deux parties relativement indépendantes, qui sont dans le cas de la -OLUT : ) La partie de routage : En fonction des données d entrée électriques, un ensemble de routeurs optiques interconnectés (pour une implémentation possible, cf. la section suivante) for un réseau :4 de démultiplexage de façon à acheminer le signal optique dans l un des 4 guides d'ondes horizontaux. ) La partie de mémorisation : elle est composée de 4 filtres «add-drop» contrôlés électriquement et interconnectés par 4 guides d onde horizontaux, Ce réseau produit le bit de donnée associé au résultat de l opération Booléenne effectuée sur les données d entrée électriques. Comme pour les LUTs électriques, la fonction booléenne exécutée dépend des bits de donnée de configuration stockés dans les mémoires SRAM qui contrôlent l état des interrupteurs (ou filtres «add-drop»): un état logique et logique dans la SRAM viennent respectivement commuter l état de l interrupteur adjacent de façon à renvoyer l état logique de sortie désiré jusqu au photodétecteur (présence d un signal optique : logique et absence d un signal optique : logique ). xiv

18 / Input Data Input Data Output y Data x y x z SRAM D / λ / / Output Data Z λ λ λ / λ / λ / SRAM Multiplexer Routing λ / λ λ stage Memorization (a) Electrical -LUT (b) Optical -LUT Fig. Representation schematique d une (a) -LUT electrique et (b) de l OLUT équivalente. Principe de base et l opération du switch Le composant clé de l OLUT est le commutateur (ou filtre add-drop). Ces composants permettent de sélectionner et de rediriger un signal optique en fonction de sa longueur d'onde. Par souci de clarté, dans la figure, on utilise des symboles différents pour représenter les routeurs optiques et les commutateurs optiques dans la partie de routage et de mémorisation, respectivement, même si ces fonctions peuvent être physiquement implémentés par le même composant optique, par exemple un filtre «add-drop» exploitant un micro-résonateur en anneau (comme expliqué dans la section suivante). La pertinence de cette distinction deviendra plus explicite lors de l'introduction de l'utilisation du WDM dans les architectures OLUTs pour paralléliser les calculs. Pour une géométrie et des paramètres matériaux donnés, le spectre de transmission d un filtre add-drop à micro-anneau est typiquement un peigne de raies qui peut être modifié par un signal de contrôle, conduisant à la définition d un état «Through» et d un état «Drop» : «Etat Through»: la résonance du filtre add-drop (i.e. associé à un pic de transmission) est désalignée spectralement avec la longueur d onde du signal d entrée, de sorte que le signal optique continue sur le même guide d onde, sans être perturbé par le filtre add-drop qu il croise. «Etat Drop» : la résonance du filtre add-drop est alignée avec la longueur d onde du signal d entrée, de sorte que ce dernier est redirigé du guide d onde d entrée vers le second guide (dans l exemple de la Fig., le guide orthogonal). Le commutateur ainsi implémenté peut être considéré comme un routeur optique spatial x contrôlé dynamiquement (i.e. le bloc de base dans la partie routage) ou bien xv

19 comme un interrupteur optique contrôlé statiquement qui peut changer la direction du signal optique d entrée en fonction de l état de donnée stockée dans la mémoire adjacent (i.e. la brique de base pour implémenter la partie de mémorisation). Noter que les cahiers des charges pour ces deux fonctions sont cependant assez différents: le commutateur de la partie routage doit pouvoir fonctionner en régime de modulation dynamique très rapide, pour être compatible avec un débit de données (signale de contrôle) élevé, tandis que le commutateur de la partie mémorisation n impose aucune exigence sur la vitesse de modulation puisqu il fonctionne à l'état statique et n est modifié que de manière ponctuelle si l OLUT est reconfigurée. Pour le reste du résumé, nous utilisons de manière équivalente le terme de filtre «add-drop» pour désigner ces deux composants. Enfin, bien que le symbole choisi pour représenter le commutateur optique ressemble à un micro-anneau, nous soulignons que cela ne représente qu un choix d implémentation possible (probablement la plus mature actuellement) pour construire les commutateurs composant l architecture de l OLUT. a) AND b) AND c) AND d) AND Electrical -LUT e) AND D f) g) h) AND D AND D - x -OLUT λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ AND λ D Fig3. Example d une fonction AND implementé par une -LUT et une -OLUT: (a-d) chemins d entrée et sortie des données dans la -LUT pour différents scénarios de données d entrée, (e-h) chemins corréspondants suivis par le signal optique pour la -OLUT. La figure 3 (a-d) illustre les chemins suivis par les données et les résultats obtenus en sortie quand la LUT est configurée pour implémenter une opération logique «AND», un signal de sortie associé à une logique ou est généré en fonction des signaux de contrôle électrique, i.e. les données d entrée. La Fig.3 (g-j) représente les scenarios correspondants dans une -OLUT qui est configurée pour exécuter la même fonction logique en utilisant un faisceau lumineux à la longueur d onde λ. Dans l OLUTs, l état logique de sortie est obtenu selon que la lumière est présenté (scenario (e) : logique ) ou non (scenario (f)-(h) : logique ) au niveau du photodetecteur positionné en haut de la colonne de mémorisation. Pour plus de clarté, on représente les commutateurs en (hors) résonance, i.e xvi

20 qui sont spectralement (des)alignés avec le signal optique incident par les contours des rings en trait plain (pointillé). Principe de fonctionnement de la n-m-oluts Comme mentionné précédemment, en tirant le meilleur parti de la technologie photonique silicium, l'utilisation du WDM est un vecteur fondamental pour la création d architectures de calcul puissantes. Bien que l OLUT décrite sur la figure (b) utilise un signal optique à la longueur d'onde λ pour faire une seule opération, de manière équivalente à une LUT traditionnelle, le WDM peut être avantageusement utilisé dans l OLUT pour réaliser des opérations logiques simultanées sur les mêmes données d'entrée. De cette façon, l OLUT permet potentiellement d'augmenter le rapport performance/consommation en puissance par rapport à la LUT électrique. Une OLUT avec m opérations (désigne si après n-m-olut) interface n bits de donnée d entrées électriques avec m bits de données de sortie, à l'aide de m signaux optiques aux longueurs d'onde distinctes (λ,..., λ m- ). Dans la partie de routage, les m signaux optiques λ i (i =... m-) partagent le même chemin optique spécifié par les combinaisons des données d'entrée électriques. Dans la partie de mémorisation, ils sont traités et routés successivement dans m étages de mémorisation (représentés par m colonnes distinctes), composé chacun de n filtres «add-drop» identiques et reliés entre eux par n guides d'ondes horizontaux. Chaque étage de la partie de mémorisation exécute une fonction booléenne précise grâce à une longueur d'onde spécifique, tous les étages fonctionnant en parallèle grâce au WDM. Un exemple de -4-OLUT configuré pour exécuter simultanément les opérations logiques de ET, OU, XOR et NXOR est illustré sur la figure 4. Dans cet exemple, les valeurs d'entrée x = et y =, redirigent, dans la partie routage, les signaux optiques vers le premier guide d'onde en haut. Les signaux optiques sont ensuite routés sélectivement en fonction de leur longueur d onde, dans la partie de mémorisation, selon les états des commutateurs tels que contrôlés par les configurations de SRAM. Chaque longueur d'onde continue ainsi sur le même guide d'onde horizontal ou est sélectivement redirigé dans le guide d onde vertical, produisant une logique ou sur les sorties associées. xvii

21 X Y Z Z Z Z 3 AND OR XOR Buffer λ D D D D λ λ λ 3 λ λ λ λ3 λ x λ x λ λ λ λ λ λ λ 3 λ 3 λ x λ λ λ λ 3 Routing part Memorization part Fig.4 Représentation fonctionnelle d'une -4-OLUT configurée pour réaliser en parallèle 4 opérations logiques sur 4 longueurs d'onde distinctes. Dans l'architecture de l OLUT, le WDM est mis en œuvre à l'aide de deux schémas distincts de filtrage en longueur d'onde (i) dans la partie de routage, où tous les signaux optiques, indépendamment de leur longueur d'onde, se propagent le long du même chemin, et (ii) dans la partie de mémorisation, où chaque signal optique (qui est spectralement distincte des autres) est acheminé individuellement en fonction de la donnée de configuration. Pour l'exemple de la -4-OLUT (Fig.4): La partie de routage: Le comportement du commutateur dans la partie de routage est illustré sur la Fig.5 (a) selon qu il est dans l état Drop (trait plein) ou dans l état Through (ligne pointillée). Les flèches représentent les quatre signaux optiques incidents pour lesquels les longueurs d'onde λ, λ, λ et λ 3 sont soit idéalement alignées avec les longueurs d'onde de résonance du filtre add-drop (représentés par des pics dans le spectre de transmission) dans l'état Drop, soit désaccordées avec un certain écart en longueur d'onde λ dans l'état Through. Les longueurs d'onde des signaux optiques injectés sont régulièrement espacées d un écart spectral correspondant au FSR x («free spectral range») du filtre add-drop. Ainsi, dans le cas où le filtre «add-drop» est dans l'état DROP, tous les signaux sont redirigés vers un guide d'onde donné, alors que dans l'état Through, tous les signaux se propagent le long de l'autre guide d'onde. La partie de mémorisation: Les Fig.5 (b) et (c) illustrent le fonctionnement des filtres «add-drop» dans la partie de mémorisation ainsi que leur spectre de transmission. Par rapport à ceux de la partie de routage, leur FSR est légèrement plus large (notés FSR m et dans FSR m sur les Fig.5 (b) et (c)) de sorte qu une seule longueur d'onde de résonance se trouve xviii

22 alignée avec l une des longueurs d'onde des signaux optiques injectés: λ pour (b) et λ pour (c), respectivement. En outre, les FSRs des filtres add-drop constituant les différents étages de mémorisations doivent être légèrement différents pour éviter le scénario indésirable où les résonances des filtres «add-drop» se retrouveraient alignées par erreur avec la longueur d'onde des autres signaux optiques après le processus de mise en accord/désaccord. Des FSR différents et de longueurs d'onde de résonance distinctes pour les filtres add-drop des différents étages de la partie de mémorisation peuvent être effectivement obtenus en modifiant la géométrie du filtre (par exemple le rayon du micro-anneau) ou en utilisant un contrôle thermique. Grâce à cette distinction, un seul signal est redirigé vers le guide d'onde vertical lorsque le filtre «add-drop» est dans l'état Drop (trait plein), les autres signaux continuant de se propager à travers le même guide d'onde, sans déviation. De manière similaire au filtre add-drop utilisé dans la partie de routage, tous les signaux se propagent le long du guide horizontal si le filtre «add-drop» est dans l'état Through (trait pointillé). a) Router ON Resonance DROP λ x λ λ3 THROUGH OFF Resonance DROP λ x λ THROUGH λ3 Transmission Spectrum at Drop port FSR x λ λ λ λ 3 λ b) λ Memorization Stage λ c) Memorization Stage λ λ DROP λ DROP λ λ λ λ 3 THROUGH λ λ λ 3 THROUGH λ λ DROP λ λ λ λ 3 THROUGH DROP λ λ λ λ 3 THROUGH Fig.5 Illustration du schéma de filtrage en longueur d onde dans une -4-OLUT. FSR m λ λ λ λ 3 FSR m λ λ λ λ 3 λ λ n-m x -OLUT architecture Pour maximiser les performances de calcul, on propose une architecture légèrement modifiée, désigné ci-après la n-m -OLUT, qui calcule la fonction logique, et sa logique complémentaire simultanément. La Fig.6 présente l architecture d une - -OLUT avec deux entrées. Le résultat du calcul de l OLUT, tel qu'effectué par une -LUT électrique, est donné xix

23 sur la sortie Z. La - -OLUT possède également une seconde sortie Z.sur laquelle le résultat complémentaire de l opération est calculé. La performance de calcul d une OLUT utilisant la sortie complémentaire est ainsi augmentée par rapport à l OLUT présentée dans la section précédente, avec un minimum de hardware supplémentaire (sans filtre add-drop, mais simplement des virages et des fusions de guides d onde supplémentaires dans ce cas simple). De manière similaire à la n-m-olut, l OLUT avec l interface complémentaire utilise le format électrique pour les données d'entrée et de sortie. La partie complémentaire de la n- m -OLUT est ajoutée comme suit : Partie complémentaire: Un guide d'onde vertical est utilisé pour acheminer les signaux optiques des guides d'onde horizontaux de la partie de mémorisation vers les sorties complémentaires. Des filtres add-drop optiques passifs sont utilisés pour filtrer les signaux optiques en fonction de leurs longueurs d'onde, produisant ainsi le résultat complémentaire de la fonction Booléenne ciblée qui est stockée dans la mémoire. On note que le même codage de données des résultats est utilisé dans la partie complémentaire et la mémoire. Input Data x y Output Data z D / λ λ x / λ λ λ x / λ λ x / λ Routing part Memorization part Complementary part D Output Data z Fig.6 Illustration de l architecture d une - -OLUT La n-m -OLUT adopte le même schéma de filtrage en longueur d'onde que la n-m- OLUT dans la partie de routage et de la mémorisation. Cependant, le filtrage dans la partie complémentaire est réalisé en exploitant un filtre «add-drop» passif pour sélectionner les signaux optiques sans aucun contrôle dynamique. La Figure 7 illustre le fonctionnement du filtre «add-drop» passif dans la partie complémentaire. Comme pour la partie de mémorisation, son FSR est légèrement plus large que l écart entre les longueurs d'onde adjacentes des signaux optiques incidents, de sorte qu une seule longueur d'onde parmi celles contenues dans le signal optique injecté se trouve alignée avec l'une des résonances du filtre xx

24 add-drop. L utilisation de filtres «add-drop» passifs fixe les longueurs d'onde résonantes pendant l étape de conception, ce qui est suffisant puisque celles-ci n ont pas besoin d'être changées, même lorsque l'olut est reconfigurée pour effectuer d'autres opérations logiques. a) THROUGH λ λ b) FSR i3 λ 3 λ λ 3 D DROP Z 3 λ λ λ λ 3 Fig 7. L opération de l add-drop filtre dans un -4 -OLUT: (a) Layout (b) spectre en longueur d onde L architecture et le concept de l OLUT présentés jusqu ici pourraient être mises en œuvre physiquement en utilisant diverses approches. Le choix de l implémentation a d ailleurs certainement un impact sur la performance de l'architecture ainsi réalisée. Dans la section suivante, nous proposons une implémentation physique spécifique de l OLUTs, qui n est peut-être pas la solution optimale, mais qui tire avantage de la technologie photonique sur silicium aujourd hui mature. λ 4. L implémentation physique de l architecture de l OLUT Le fonctionnement de l'architecture de l OLUT qui a été présenté impose certaines contraintes physiques sur les caractéristiques des filtres «add-drop», tels que leur géométries et leur facteurs de qualités Q. Ici, nous étudions comment la dimension du système, c est à dire le nombre d'entrées et de sorties, impacte la conception des filtres «add-drop» actifs pour la mise en œuvre de l'architecture de l OLUT électro-optique. La Figure 8 représente le filtre add-drop commandé par l intermédiaire d une jonction PIN. Cette dernière permet de modifier, par voie électrique, les propriétés optiques du microanneau silicium. Le micro-anneau est couplé à deux guides d onde silicium croisés. La diode PIN est polarisé aux bornes des deux électrodes P+ et N+. Lorsque le filtre add-drop est polarisé, la concentration de porteurs libres injectés dans l anneau peut être de plusieurs ordres de grandeur supérieur à la densité intrinsèque initiale. xxi

25 (a) (c) (b) Electrical Input V z x V N+ IN OUT λ λ x P+ i OUT IN OUT Resonator λ x (x= m) OUT Ground V y Si slab-n+ x Ring Electrode +V Si-i type Si slab-p+ Electrical Simulation parameters: ring waveguide: 45nm xnm Slab height: 5nm Spacing electrode with ring:.6µm P+/N+ doping: 9 cm -3 i-region doping: 5 cm -3 Fig.8 Filtre «Add-drop»: (a) representation symbolique (b) layout (top-view), (c) layout simulé(crosssection) et des paramères du composant Le nombre de canaux pouvant être traités par un tel dispositif, c'est-à-dire le nombre maximum, m, de bits de sortis fournis par l OLUT, est directement lié au FSR (Free Spectral Range) du micro-résonateur. Pour une technologie laser basé sur les semiconducteurs III-V, on peut considérer une largeur spectrale du gain de l ordre de nm à.5µm (puits quantiques InP). Le FSR doit donc être inférieur à /m nanomètres pour la réalisation d une n-m-olut. Comme le FSR est inversement proportionnel au rayon r de micro-anneau par la relation x FSR λ / πrn (ou n g est l indice de groupe), r doit être plus grand que ~8m (nm) g (calculé pour λ x ~.55µm et n g ~4.3). En fait, un filtre add-drop avec un plus grand FSR peut accueillir moins de bits de sortie, puisque chacun d'eux est associé à une longueur d'onde dans la n-m-olut. Par exemple, les micro-anneaux comportant au moins 5 µm de rayon doivent être utilisés pour mettre en œuvre une -6-OLUT, et ce rayon peut être diminué jusqu'à.7µm pour une --OLUT. La dimension n-m de l OLUT influe donc directement sur la taille du filtre add-drop. Transmissions d un filtre «Add-drop» Le mode de fonctionnement du filtre add-drop actif est résumé dans la Fig.9 (les équations sont données par la théorie des modes couplées temporelle, CMT). Chaque scénario est associé à une valeur logique destiné à OUT, aux valeurs de transmission sur le port Through et Drop, et les spectres de transmission correspondent à OUT. En fonction de la longueur d'onde de résonance initiale du dispositif par rapport à la longueur d'onde du signal d'entrée, le filtre add-drop peut être configuré selon deux modes de fonctionnement : xxii

26 Mode A : Fig.9 a) et b) illustrent comment un signal optique injecté dans le port IN est acheminé à travers le filtre add-drop actif lorsque ce dernier est dans l'un des deux états (Through et Drop), et la table de vérité indique les valeurs des transmissions qui sont ciblés pour les deux états contrôlés par la polarisation. Comme indiqué précédemment, lorsque la diode est polarisée en direct, la densité de porteurs injectés dans la région intrinsèque augmente fortement, ce qui conduit à un changement de l'indice de réfraction, cependant, accompagné d une absorption optique supplémentaire qui tend à réduire le rapport Q L to Q c et, par conséquent, dégrada la transmission T sur le port Drop quand V=V op Mode B : Alternativement, si nous assurons que le filtre add-drop est à l'état DROP lorsqu aucuns porteurs n est injecté (nécessite un pré-calibrage), les signaux optiques peuvent se propager sur le port Drop sans obtenir la perte d'absorption supplémentaire dans le résonateur. Alors que l'add-drop est commuté dans l'état Through, les porteurs sont remplis dans la région intrinsèque du résonateur en anneau. Toutefois, pour ce cas, le signal d'entrée sera transmis directement au port Through, de sorte qu'il n est pas couplé et ne subit donc aucune d absorption. Il est donc énergétiquement plus favorable d utiliser le mode B plutôt que le mode A. Si nous supposons que la résonance du filtre add-drop est configurée pour être initialement alignée avec la longueur d'onde du signal incident λ i (i.e. λ=) en l'absence de polarisation externe (V=), on obtient T V = ) = ( Q L / Q andt V = ) = ( Q L / Q. Dans ( c ) ( c ) ce cas-la, l expression Q L est également différent de celui de la Mode A car il exclut le Q a supplémentaire qui est apparu pour le Mode A quand V=V op. Les colonnes c) et d) dans la Fig.9 montre la propagation du signal optique et la table de vérité correspondant à cette configuration. En comparant avec les valeurs de T atteint pour le mode A (voir Fig.9 (b)), nous voyons que le problème de la réduction de la transmission par absorption de porteurs dans le ring est évitée dans cette configuration. Considération sur la vitesse pour les filtres add-drops électro-réfractifs Le taux maximum de données pour un tel modulateur en anneau SOI sans polarisation en inverse est limitée à ~ Gbit/s, comme indiqué par le temps de montée/descente de la réponse du système qui peut être obtenu directement en résolvant les équations transitoires dans une jonction PIN polarisé en direct (voir la section 4..). La section 4.. a également mis en évidence que le max {temps de montée, temps de descente} était essentiellement limité par la durée de vie des porteurs libres pour un guide d'onde SOI standard et ne peut être réduite en utilisant une polarisation directe plus grande. Dans la même section, nous avons relaté certaines démonstrations de fonctionnement au-delà de.5gbit/s. Cependant ce xxiii

27 régime nécessite l implémentation de signaux électriques complexes et de tensions élevées, peu compatible avec un circuit de contrôle CMOS de faible consommation. Signal propagati on scenario Targeted Signal logic at OUT T IN a) Mode A (V=) b) Mode A (V=V op ) c) Mode B (V=) d) Mode B (V=V op ) OUT V= THROUGH OUT IN OUT OUT OUT V V= V DROP DROP THROUGH OUT OUT OUT IN IN IN IN IN IN ( QL / Qc ) Qc / Qi Qc / Qa ( ) + Q / Q + Q / Q [ Q λ / λ] + L c + c i i c a Q / Q ( ) Q / Q + [ Q λ / λ] + c i ( Q L L / Q ) c T (QL / Qc ) ( ) + Q / Q + Q / Q [ Q λ / λ] + L c i c a ( Q ) c / Q i (Q / Q + [ ] Q / + L L λ λ c ) T T T λ i T Spectrum λ i λ i λ i λ res λ λ res λ λ res λ λ res λ Fig.9 Fonctionnement du filtre add-drop actif selon les modes opératoires A et B. 5. Méthodologie pour l évaluation de la performance Fig. illustre la méthodologie de conception. Idéalement, pour une application de calcul donnée (par exemple un ALU ou un additionneur complet), notre approche commence avec les spécifications au niveau architectural (notamment en ce qui concerne le nombre de OLUTs, les dimensions des entrées et des sorties des OLUTs, ainsi que l'option complémentaire) et passe ensuite progressivement jusqu'au niveau composant afin de concevoir un OLUT fonctionnel. Les paramètres au niveau du dispositif incluent la taille (rayon de l'anneau), le facteur de qualité et le décalage de longueur d'onde des filtres add-drop. Ces paramètres seront utilisés pour évaluer les caractéristiques clés du dispositif optique en effectuant la simulation physique (par exemple par FDTD), la simulation électrique et la modélisation avec la théorie des modes couplés (CMT). Les caractéristiques des autres composants (par exemple, les lasers et les photodétecteurs, ainsi que les guides d'onde) dans la boîte à outils fonctionnelle utilisant la technologie photonique sur silicium sont extraits de la bibliothèque. La configuration des données d'entrée et des mémoires différentes (indiquées par l'application cible) sont considérés pour calculer la consommation d'énergie d'un seul bloc de OLUT. xxiv

28 L'analyse est réalisée en s'appuyant sur un taux d'erreur par bit («BER») donné et le résultat est donné en termes d'énergie. Ceci permet d'élaborer l'espace de conception possible d'un OLUT, représenté par le facteur Q et le décalage de la longueur d'onde du filtre d add-drop. L'efficacité énergétique optimale d'un OLUT est obtenue par une exploration automatisée de l'espace de conception des paramètres des dispositifs optiques (par exemple des facteurs Q et les décalages en longueur d'onde). Les autres caractéristiques de l OLUT, tels que la performance, la latence ou l encombrement, peuvent également être évaluées en fonction des paramètres physiques dans l'espace de conception. Après cela, nous montons de nouveau au niveau du système: nous évaluons la performance et l'efficacité énergétique de l'architecture selon diverses options de conception au niveau système tels que le nombre et la taille des OLUTs et la topologie d'interconnexion (par exemple le nombre de guides d'onde et le nombre des longueurs d'onde utilisées), ainsi que les caractéristiques de l'interface. Cependant, au niveau système, l'exploration de l'espace de conception est actuellement un processus manuel. Il a besoin d'être automatisé entre les résultats obtenus et les spécifications au niveau système pour explorer les architectures alternatives, susceptibles de donner de meilleurs résultats (par exemple, une meilleure efficacité énergétique) pour une application donnée. Une telle exploration de conception nécessite des outils benchmarks (par exemple MCNC [7]) en tenant compte de l'avantage principal de l OLUT, c'est à dire le calcul parallèle sur un même ensemble de données. La mise en œuvre d'un tel outil fait partie des travails futurs. System level specification: Number of OLUTs, n, m, complementary, etc. Device level specification: r, λ, Q c Test bench Application Application (e. (e. ALU, ALU, full full adder) adder) Test bench Input Input data, data, configuration configuration BER< -8 Energy efficiency analysis library PD, PD, laser, laser, waveguide waveguide losses, losses, etc. etc. library Interconnect Interconnect topology, topology, interfaces interfaces Design Space Exploration Result: A functional and energy-efficient OLUT Design Space exploration Result: A functional and energy-efficient reconfigurable computing architecture using silicon photonics technoloy Fig. Illustration d une méthodologie de modélisation multi-niveau pour la conception d une architecture de calcul photonique functionnelle et efficace en consommation énergétique, basée sur des OLUTs xxv

29 Modèle d énergie Ici, nous examinons les principes de base pour re-clarifier la relation entre les paramètres décrivant les filtres add-drop, et la consommation d'énergie pour l OLUT, basée sur l'effet électro-optique. Les équations et les valeurs constantes utilisées par le modèle sont présentées dans la Fig.. Nous rappelons ici que la consommation globale d'énergie de l OLUT E OLUT (i.e. energy-per-output-bit, donnée par l équation (a) sur la figure) est la somme des contributions suivantes: i) E d (cf. Equation (4.7)) représente l'énergie dynamique dissipée par les filtres adddrop pour effectuer la transition d'état (Drop to Through), qui doit injecter des porteurs pour régler la longueur d'onde de résonance; ii) E s (cf. Equation (4.8)) représente l'énergie statique consommée par les filtres adddrop et est déterminée par la polarisation électrique et le courant obtenu selon la simulation électrique de la jonction PIN du résonateur micro-anneau en silicium; iii) E laser (cf. Equation (4.9)) représente la puissance optique minimum d'entrée délivrée par le laser pour distinguer le niveau logique du niveau logique (selon la dissipation de l'énergie laser dans la OLUT) pour atteindre un taux d'erreur par bit acceptable (BER= -8 est choisie ici). iv) E pd est une estimation de l'énergie dissipée par chaque photodétecteur et est quantifiée à fj/bit pour une fréquence de GHz Comme indiqué précédemment, les paramètres nécessaires pour décrire complètement l opération d un filtre add-drop sont : le facteur de qualité de couplage Q c ; le décalage en longueur d onde λ entre la longueur d'onde de résonance et la longueur d onde du signal d entrée ; et le facteur de qualité intrinsèque Q i. Comme Q i est généralement fixé pour une technologie donnée et pour un rayon d'anneau donné, les transmissions du filtre add-drop dans le régime actif sont ainsi exprimées selon les valeurs de Q c et λ. De ce fait, on peut construire l'espace de conception possible sur la base des valeurs du facteur de qualité de couplage Q c, ainsi que du décalage de longueur d'onde λ. Pour un nombre de bits d'entrée donné n, et un nombre de bits de sortie donné m: Des valeurs plus élevées de E d et E s sont nécessaires pour le fonctionnement du n-m- OLUT pour un décalage en longueur d'onde λ plus élevé, parce qu'il y a plus de porteurs libres à injecter. Toutefois, les valeurs de E d et E s sont indépendantes de Q c xxvi

30 Cependant, E laser est inversement proportionnelle à la différence minimale entre les valeurs de transmission pire cas pour les niveaux logiques et ( min and max dans l'équation (b) dans la Fig.) et s appuie donc sur les valeurs de Q c et de λ. D'une part, pour un plus grand décalage en longueur d'onde λ, une valeur élevée de transmission sera généralement obtenue au port Through du filtre add-drop dans l'état Through, facilitant ainsi la distinction des niveaux logiques et, ce qui devrait conduire à une valeur plus faible de E laser, à utiliser pour les OLUTs. D'autre part, comme indiqué par les expressions de transmission dans la Fig., pour une valeur plus grande de Q c (ou plus précisément du rapport Q c /Q i ), il est plus difficile d'atteindre l'état Drop lorsque le filtre add-drop est éteint (puisque T devient plus faible), mais il n'aide pas à atteindre l'état Through (où T augmente) car une augmentation Q c conduit à une réduction de la largeur spectrale de la résonance. Ceci implique que l'impact de la valeur de Q c sur celle de E laser n'est pas toujours le même et dépend de l'état du filtre add-drop (Drop ou Through), car c'est celui-ci qui déterminera essentiellement la valeur de transmission dans le pire cas. Par exemple, si la transmission dans l'état Through est inférieure que dans l'état-drop, une valeur inférieure de E laser est nécessaire pour augmenter Q c. Inversement, E laser augmente avec Q c lorsque la transmission de l'état Through est plus élevée que celle de l'état Drop. Pour résumer brièvement, pour une technologie donnée et un rayon d'anneau fixe (Q i constant), l'énergie dissipée dans l'olut (E OLUT ) repose essentiellement sur les valeurs du facteur de qualité de couplage Q c et le décalage en longueur d'onde λ. La valeur optimale de E olut peut être réalisée à partir d'un compromis entre la dissipation de l'énergie des lasers et les filtres add-drop, pour différentes valeurs de Qc et λ. Pour étudier les rapports entre la dissipation d'énergie et ces paramètres physiques et ainsi obtenir la valeur minimale de E olut, nous présentons le calcul de l'espace de conception possible du Q c et λ pour l'architecture d une --OLUT dans la figure. xxvii

31 Energy-per-output-bit (fj/bit): Constants: a. E ( λ, Q, n, m ) = E + E + E + E OLUT c d s laser V dd b. E Laser ( λ, Q c, n, m) = P laser P Laser = P recv /( min max ) η B c. E d ( λ,n,m) E sw ~.5q tot V d. E s ( λ,n,m) P s ~ IV e. E pd = fj/bit pd N λ (fj/bit) Data rate (B): Gb/s Bit error rate (BER): -8 Detector frequency : GHz Wavelength λ:.55µm Transmissions: ( Q T ( V = V ) = T Q L ( V = ) = ( /( + Q = Q op c + Q a [ Q λ / λ ] + Q c i L / Q )) i L / Q c ) + Fig. Les équations de base et les valeurs constants utilisé dans le model 6. Conclusions et perspectives L'architecture OLUT est indépendante de la technologie. Nous avons proposé une mise en œuvre physique spécifique pour l'olut, ce qui pourrait ne pas être optimale mais bénéficie de la maturité de la technologie de la photonique sur silicium. Dans cette mise en œuvre, nous nous sommes concentrés sur la réalisation des OLUTs électro-optiques, où les données d'entrée et de sortie restent dans le domaine électrique. Nous avons développé et mis en œuvre un filtre add-drop à contrôle électrique basé sur micro-résonateur optique en anneau qui répond aux besoins fonctionnels pour le routage et le filtrage des signaux optique à différentes longueurs d'onde dans l'architecture de l OLUT. L'inconvénient essentiel de cette proposition est associé à l'approche électro-optique, qui a besoin de conversions optiqueélectriques pour la mise en cascade des OLUTs. L'autre inconvénient majeur de ce choix est que les micro-résonateurs en anneau de silicium sont des dispositifs sensibles à la température, car la largeur spectrale des longueurs d'onde de résonance est étroite (~, nm pour un Q ~ 5, ) et le silicium a un grand coefficient thermo-optique. Le contrôle de la température est donc nécessaire pour maintenir l'état des résonateurs en anneau durant le fonctionnement des OLUTs. En effet, dans un système photonique utilisant le WDM, le réglage de la longueur d'onde est indispensable pour compenser la non-uniformité de fabrication. Ceci n'a pas été pris en compte dans l'estimation de la consommation d'énergie pour l OLUT dans le chapitre 5. Une autre limitation qui se pose au choix de la mise en œuvre spécifique est la limite de vitesse à laquelle les interrupteurs électro-optiques (introduites dans le chapitre 4) peuvent fonctionner. En effet, ces interrupteurs, construits sur la base d'une jonction PIN, s'appuient sur l injection de porteurs libres. Cependant, il existe de nombreux autres moyens xxviii

32 d implémenter le filtre add-drop : par exemple le coupleur directionnel, les cristaux photoniques ou l'interféromètre Mach-Zehnder. En plus, en considérant les progrès de la technologie, des composants plus compacts et plus économes en énergie deviennent disponibles. Il est à noter que la frontière de la photonique sur silicium évolue extrêmement rapidement avec de nouveaux dispositifs intégrés reportés chaque année. Cependant, notre travail de modélisation ne repose pas sur des nouvelles contributions dans les performances du dispositif (vitesse, puissance ou efficacité). Au lieu de cela, nous nous sommes concentrés sur l'étude de la façon dont certains dispositifs photoniques sur silicium devraient être conçus pour l'architecture de calcul pour atteindre les exigences de performance au niveau du système. Dans ce contexte, nous avons également proposé une approche de modélisation multi-niveau basée sur l'exploration de l espace de conception et des paramètres de composant pour estimer la performance du système. Cette méthode nous permet d'étudier la faisabilité de l'architecture OLUT et d'explorer l'espace de conception de dispositifs photoniques pour réaliser des calculs fiables et efficaces dans les architectures OLUTs. Cette méthode pourrait donc être étendue à l'évaluation de la performance des OLUTs s appuyant sur différentes implémentations physiques, simplement en changeant le modèle physique utilisé au niveau de composant. L'évaluation des performances pour les architectures de l'olut électro-optique a été présentée en utilisant l'approche de modélisation multi-niveau et le modèle physique. L'impact des dimensions d'entrée d OLUT sur les paramètres des composants, et par conséquent sur l'efficacité énergétique du système, est étudié par le calcul de l'espace de conception possible pour les OLUTs. Les résultats analytiques ont montré le potentiel des architectures de OLUT d'accéder au dessous de fj/opération logique, ce qui est en effet comparable à la dissipation totale d'énergie par l opération logique pour les dispositifs actuels de CMOS en silicium (au niveau du femto Joule, selon ITRS [5]). En outre, nous avons illustré le potentiel de l'architecture n-m -OLUT pour améliorer l'efficacité du matériel et de l'énergie par rapport à la n-m-olut en utilisant la mise en œuvre d'une unité logique arithmétique -bit (ALU). Les résultats d'analyse ont mis en évidence l'avantage clé des sorties complémentaires pour augmenter la capacité de calcul d'une OLUT jusqu'à %, avec un surcoût raisonnable sur la puissance du laser optique d'entrée et de la surface du système. Cependant, il est bien de souligner que le modèle proposé n inclut pas certaines sources de dissipation d'énergie, qui devraient être pris en compte dans un environnement réel. Il s'agit par exemple de la consommation d'énergie statique pour les lasers, de l'énergie xxix

33 requise par les filtres add-drop de pré-calibration en temps réel et de réglage thermique. Ces points feront l'objet de sujets de travail futur. Pour compléter les perspectives de ce travail de thèse, nous avons proposé une version plus avancée de l'olut pour compenser les faiblesses associées à la mise en cascade des OLUTs, grâce à l'utilisation d'un filtre add-drop tout-optique. L'interface tout-optique proposée permet de cascader plusieurs OLUTs ensemble pour construire éventuellement une architecture FPGA tout-optique, éliminant ainsi la latence et la consommation d'énergie associée avec des interfaces opto-électriques. Cette approche permettrait également de bénéficier de vitesses de calcul potentiellement plus élevées, car le filtre add-drop tout-optique a un débit bien plus élevés que celui des dispositifs électro-optiques introduits dans le chapitre 4. xxx

34 TABLE OF CONTENTS REMERCIEMENTS... I ABSTRACT... VII RESUME FRANCAIS... IX CHAPTER INTRODUCTION.... Background.... Lesson from the history of optical computing Early days of optical computing Golden Age of optical computing Lessons and observations Optics in computing: what next?....4 Objectives and thesis outline... 4 CHAPTER EMERGING TECHNOLOGIES FOR RECONFIGURABLE COMPUTING Emerging technologies for reconfigurable computing architectures Introduction to computing architectures FPGA Overview FPGAs challenges and emerging technologies Non-volatile nano-memory devices D technology Optical technologies for reconfigurable computing State-of-the-art: Silicon photonics based computing architectures Background Directed Logic Reconfigurable Directed Logic Conclusions CHAPTER 3 OLUT ARCHITECTURE DESIGN AND IMPLEMENTATION Single-output OLUT Architecture From electrical LUTs to optical LUTs Basic principle and switching operation n-m-olut architecture Operation principles Preliminary evaluation of n-m-oluts Evaluation Metrics Scalability of OLUT architecture Case study: k-bit full adder with carry n-m -OLUT Architecture OLUT with Complementary Logic Output Filtering Scheme in the complementary part... 5 xxxi

35 3.4 Conclusions... 5 CHAPTER 4 FROM ARCHITECTURE TO DEVICE: MULTI-LEVEL MODELLING AND SIMULATION Functional toolbox based on silicon photonics for implementing OLUT Passive Add-Drop Filters (Microring resonator) Basic Principles Passive add-drop filter transmission and Coupled Mode Theory Silicon waveguides, integrated photodetectors and micro-lasers Design of active add-drop filters for OLUT architectures Electrically-controlled modulation of an optical signal Electro-optic effect Thermo-optic effect Free carrier dispersion and electro-refractive effect Carrier electrical manipulation with PIN junction From the OLUT system dimension to the device building block geometry Transmission characteristics of the active Add-drop filter Calculation of electrical control and power consumption Speed consideration for electro-refractive add-drop filters Multi-level modelling of OLUT and impact on the low level design of the OLUT building blocks Overview of the multi-level modeling methodology Optical losses in OLUT architectures OLUT energy model Dynamic Energy E d Static Energy E s Energy dissipated by the photodetectors E pd Energy dissipated by the laser E laser Conclusions CHAPTER 5 PERFORMANCE EVALUATION OF THE ELECTRO- OPTIC OLUT IMPLEMENTATION Case study and result analysis for n-m-oluts A review of the energy model introduced in chapter Feasible design space for the --OLUT From to m output bits Scalability and energy efficiency Case study: -bit Arithmetic Logic Unit (ALU) From to n input bits Performance evaluation for the n-m x -OLUT Architecture Feasible design space for the - x -OLUT Area and optical power overhead Case study: a -bit ALU implemented by a n-m x -OLUT Conclusions... 9 CHAPTER 6 CONCLUSIONS AND PERSPECTIVES Conclusions... xxxii

36 6. A possible all-optical implementation of OLUTs: towards all-optical FPGAs Cascading of OLUTs Interconnect network ORNoC λ-router Case study: 4-bit full adder Discussion... 3 REFERENCES... 5 APPENDIX xxxiii

37 xxxiv

38 LIST OF ACRONYMS A ALU ASIC Arithmetic Logic Unit Application Specific Integrated Circuit C CLB CMOS CMT CW Configurable Logic Block Complementary Metal Oxide Semiconductor Coupled Mode Theory Continuous Wave E EDA Electronic Design Automation F FDTD FSR FPGA Finite Difference Time Domain Free Spectral Range Fidel Programmable Gate Array G GPP General-Purpose processor I InP Indium Phosphide L LUT Look Up Table xxxv

39 O OLUT ONoC Optical LookUp Table Optical Network On Chip R RAM Random Access Memory S SOA SOI Semiconductor Optical Amplifier Silicon On Insulator T TSV Through-Silicon-Via V VCSEL Vertical Cavity Surface-Emitting Laser W WDM Wavelength Division Multiplexing xxxvi

40 Chapter Introduction Chapter INTRODUCTION. Background Today s era of high-performance computing and big data analysis promises to bring profound and far-reaching changes to society []. These changes are made at all levels of information systems from data acquisition in distributed sensor networks to storage and processing in the cloud. Many computationally demanding applications, e.g. social network analysis, quantum physics simulation, weather forecasting, disaster prediction, oil and gas exploration, molecular simulation, increasingly require high-performance, cost-effective, energy-economic computing hardware [3]. However, these constraints are conflicting in conventional or incremental computing systems, and have also proved to be a major challenge in disruptive approaches. New computing paradigms are thus required to address the energy and performance challenges of computing in the data explosion era. In the past, advances in semiconductor technology have been the main vehicle for expanding the boundaries of computing. The long-term trend in semiconductor technology was famously predicted in a paper by Gordon Moore in 965 [4], in which he observed that the number of electronic transistors that could be fabricated in an integrated circuit (IC) would approximately double every year (later, the time between technology generations was extended to two years). Circuit miniaturization through down-scaling of the critical dimensions of transistors has thus been the primary driving force for the increase in the microprocessor computational power. Following Moore's law for almost five decades, today's microprocessors have already broken the billion transistor barrier. The ITRS Semiconductor roadmap [5] shows yet further reductions in transistor feature sizes from nm down to the sub-nm regime in the next decade. However, the scaling of physical dimensions and device speed are now mainly limited by energy dissipation [7]. According to the physical laws such as Heisenberg uncertainty principle and Landauer rule (the minimum energy required to generate a bit of information is KT ln, where K is the Boltzmann constant and T is the temperature in Kelvin), the maximum operation frequency of a switch is 5x Hz. If the device operates at this frequency, the resulting integrated circuit would consume more than 4x 6 W/cm. The heat generated would thus vaporize the circuit immediately once it is turned on [7]. Moreover, not

41 Chapter Introduction only does clock frequency appear to be limited, but also memory performance improvement has not kept pace with processor performance scaling. The mismatch between memory read/write speed and computational speed presents a wall to the scaling of overall computational performance in CMOS technology. To address these issues, the computing architecture has been shifted from a single microprocessor to multi-core (parallelism-driven) processor architectures. Computing parallelism has been exploited by using more CPUs and processing units, data/instruction parallel execution units, additional register sets, more cache and heterogeneous processors (e.g. Graphic Processing Units) [3,6] on the chip. Such a shift from sequential to parallel computer architecture would help to increase performance and robustness while keeping power consumption relatively constant. However, parallel computing architectures have to face new challenges compared to single processor architectures. A critical issue is the energy dissipated by the interconnect required to realize high-speed data communications between various computing resources in the multi-core computing system. Although its computing performance could scale with the growing number of cores, the electrical interconnects increasingly present a bottleneck due to their physical limitations in terms of loss, dispersion, cross-talk and bandwidth [-3,7,,3]. It therefore becomes very difficult to improve the computing performance when interconnect densities continue to rise. For instance, a total interconnect data rate of 5- TBit/s in future multicore chips is expected by 5 and more than the double of that by, with a maximum average allowed data communication energy dissipated on a chip ranging from. to pj/bit [3]. In high-density electrical interconnect, because the time constant of electrical wires increases as device dimensions are scaled down, the energy costs for transporting information electrically can be extremely high. From [8], the projected energy cost of off-chip electrical communication is expected to be 5.8 pj/bit in 7 while the current practice reaches about pj/bit. At this cost, therefore, most of the available power will be consumed to move data between processors and off-chip computing resources. Yet, as we demand more from the computing architectures, even such parallel computing systems will be increasingly energyconstrained. Therefore, producing computing systems that meet the performance, energy and communication demands of emerging applications will likely be impossible. As a result, to improve the energy efficiency of the computing system, emerging technologies are urgently needed, such as silicon photonics, three-dimensional integration, emerging memories and near-threshold voltage etc. In particular, optical cables have been considered as a viable alternative to copper interconnect for transferring information between

42 Chapter Introduction 3 computing elements and systems, and can potentially help the intrinsic limitations of electrical interconnects to be overcome [6]. As witnessed from the telecommunication industry with mature optical fiber technology, optics has already proved to be the best technology for conveying information from one point to another over long distance. In 3, US National Research Council published a report on the advantages of photonics [8], which wrote: The remarkable growth of networks and the Internet over the past decade has been enabled by previous generations of optical technology. Optics is, furthermore, the only technology with the physical headroom to keep up with this exponentially growing demand for communicating information. The fact that light can be easily transmitted in parallel in free space or in a guiding medium, with very low crosstalk, is of great importance. Fig. summarizes the evolution in optical interconnects observed by [9]. The past two decades have witnessed milestones of single-mode fibers in replacing telephone lines as the primary mechanism for transmitting data over medium to long distances (WAN, LAN), mostly thanks to the extraordinary growth of the Internet and network traffic. From 998 when Harnessing light [4] was published to today, the capacity per wavelength in commercial WDM long-distance networks has increased from a maximum of Gb/s per wavelength to more than Gb/s [8]. In addition, with increasing bandwidth demands, optical technology is increasingly used in short-distance data communication within local networks for high-performance computing systems [], such as data centers, clustered supercomputers and storage area networks (specifically for distance from several kilometers down to less than meters). Considering that low cost is particularly critical for short-reach applications, technologies such as VCSEL laser arrays and multimode fibers (rather than single-mode fibers and DFB lasers) are becoming widely employed [8] [].

43 Chapter Introduction 4 Fig.. Evolution of optical technology for interconnect (source from [9], ) Silicon photonics technology has matured significantly over the years and has become more cost effective [, 3, 7, 8, 8]. As illustrated by Fig., since the mid, the use of optics is not restricted to telecommunication applications but has emerged as the favored option for ever-shorter distances (from meter down to several millimeters) at board level (module-to-module), module level (chip-to-chip) or even on-chip level. The key is to achieve sufficient data communication density to enable higher computational bandwidth (from 4GBit/s to several TBit/s) without increasing power consumption in the interconnect. According to [] and [7], optical interconnects seem to be the best candidate to achieve reliable and energy-efficient communications in distributed and parallel computing systems. Beausoleil et al. [] reported in that the communication bandwidth per unit of dissipated power provided by on-chip optical interconnect technology exceeds the maximum available from purely electrical interconnects by a factor of. This can be interpreted in three ways: firstly, that light can carry information at much higher data density (higher carrier frequencies and multiple parallel channels) than electrons in electrical wires, as is essential for meeting future data-rate demands; and secondly, optics can fundamentally save energy in interconnect because the need for charging wires is completely obviated (in electrical interconnects, the capacitive effect of charging electrical wires to the signal voltage dominates energy dissipation). Thirdly, at the chip-scale, long distance has less influence on the bandwidth of optical interconnect compared to that of electrical interconnect [][]. As a result, optical interconnect has a higher bandwidth-distance product than copper interconnect. Moreover, by utilizing a mature CMOS fabrication process, this technology is available to produce highly integrated assembly with most components fabricated on the CMOS platform,

44 Chapter Introduction 5 thus greatly reducing the manufacturing cost. Numerous research efforts have focused on optical interconnects based on silicon photonics (or optical network-on-chip, ONoC) to prove its feasibility and benefits over electrical interconnects (THz bandwidth, low power, low loss and low crosstalk). Several projects targeting high performance computing systems based on photonic interconnect have been launched by industrial companies such as Intel, IBM, Oracle, HP and Avago since 9. However, the key challenges for on-chip optical interconnect are technological: CMOS compatible, low energy dissipation and high performance compact novel optical devices are required to be integrated at a large scale with low manufacturing cost, as pointed out by Miller[3] in 9. Today optics is likely to be very successful for on-chip interconnect/communication in computing systems [5,7-]. But optical technology is believed to hold the promise to go beyond realizing communication channels or networks for ultrafast massive data transmission, and could also be exploited to perform digital computation in an all-optical way as well. This can potentially lead to an additional increase in speed, bandwidth and energy efficiency as compared to transistors based computations in electrical domain. Such idea of using optics for computing as a replacement to electronics has attracted attention for more than half a century but has never becomes reality. This has been recognized by most experts in the field. Caulfield wrote in his paper on the perspectives of optical computing in 998 as follows [3]: The only way for optical practitioners to win the war with electronics is to abandon it. He described the evolution of viewing optics over electronics in computing: the first phrase is the ignorance and underestimation of electronics then awakening and fear of inferiority and now realistic acceptance that optical computing and electronics are eternal partners. But he also pointed that optics could do useful things electronics cannot and it is worth exploring what roles optics is best at. In, he wrote another paper investigating the requirement of optics in future supercomputing, where he pointed out that the potential of optics for computing particularly lies in parallel real-time information processing and the future of optics might be the use of nanotechnologies. However, since the origin of optical computing research in early 5s, there have always been many doubts about the potential of optics for computing [5]. The reasons are various and worth to be investigated. Therefore, by reviewing the historic evolution of optical computing, we investigate in the next section why optical computing could not compete with electronic over the past few decades, where the limitations are and conversely what can be hoped for.

45 Chapter Introduction 6. Lesson from the history of optical computing.. Early days of optical computing Optical computing is more than 7 years old. Using optical components for numerical computing was considered as early as the 94's by Von Neumann. In the 95s and 96s, the research field of optical computing started from the classical optical processor architecture exploring the processing power of coherent light and particularly its Fourier transform ability. The basic principle is, when using coherent light, a standard lens processes in its back focal plane the operation of Fourier transformation for a D image that is located in its front focal plane, such that the exact Fourier transform with the amplitude and the phase is analogously computed by the lens. An example of a classical optical processor architecture (so-called 4-f correlator [47]) is illustrated in Fig.. Commonly, the optical processor at that time was composed of at least three planes [49]: the input plane, the processing plane and the output plane. The input plane consists of a Spatial Light Modulator (SLM) to perform electrical-tooptical conversion; the processing plane serves as the core of processing and is based on lenses or nonlinear optical components, which can operate near the speed of light; the output plane is usually composed of a photodetector array or camera for detecting the output results. The example of Fig. uses two lenses one between the input plane and the reference plane, and the other between the reference plane and the output plane. The output of such a processor results from the correlation of images, and the information is computed by the complex optical wave amplitude. This analog architecture was used for pattern recognition and was considered to be the most promising application of optical processor at that time. Input plane Processing plane Output plane Fig.. Example of classical optical processor architecture [49]

46 Chapter Introduction 7 Since holography was invented by Gabor in 948 [8], research development in the field of optical computing was limited until the invention of the laser as a coherent light source in 96 [5], which then led to rapid progress in the design of optical correlator architectures for real-time information processing. Coherent processor architectures like the joint Fourier transform correlator were presented (e.g. by Goodman [48]), as well as incoherent architectures to compute information through wave intensities for character recognition [5]. However, due to the poor performance and high cost of critical components such as the SLM, the advancement of optical processing was slow [4]. At the beginning of the 97s, rapidly developing digital electronic computers were demonstrated to compete successfully with coherent optical computers for specific defense applications, such as the processing of synthetic aperture radar data [5]. Without major showstoppers, the path to higher performance computing with electronics was clear, and massive investments in this sector led to significantly cheaper and more mature solutions than optics in most of computing applications. However, the first years of optical computing still generated much enthusiasm concerning the potential of optics for information processing, in specific domains. In 96, researchers at a symposium on optical processing [5] recognized that specialpurpose optical processors could be used in the fields of pattern recognition and information retrieval since optical systems offer in these cases the ability to process many items in parallel, while the generous-purpose optical processors were questioned. It was recognized that optical technology was not ready to compete with electronic computing and that perhaps optical computers would have a different form than electronic ones. Several decades after that conference, it is of course clear that the general-purpose optical computer has not appeared, and even optical correlators for pattern recognition have almost disappeared due to its size and lack of accuracy... Golden Age of optical computing Fortunately, the slowdown period was then followed by a so-called golden age of optical computing from the 98s to s [5]. Although no longer directly in competition with electronic computing, the generated research results in optical computing have contributed strongly to the development of new research topics such as biophotonics, nanophotonics, optofluidics, and femtosecond nonlinear optics. In this period, remarkable progress was made in specific research topics of optical computing such as pattern recognition and optical memories. Various analog processors were constructed by taking

47 Chapter Introduction 8 advantage of technological advancement in SLMs, optical filters and analog optical processor architectures. Most of these processors remained at laboratories, but some were tested for real-time applications. For example, in 98, Cleland et al. [38] developed an optical processor for detecting signal tracks based on a matrix of LEDs as the input plane, and was also evaluated in a high-energy physics experiment in Brookhaven. In 986, Ambs et al. implemented an optical processor based on a matrix of optically recorded holograms [39]. A prototype of a correlator processor compliant with the PCI (Peripheral Component Interconnect) interface, which can be used for processing video data at 65MB/s, was also constructed [4]. In addition, optical processors were designed for many other information processing applications such as matrix operations [4], systolic array processing [4] and neural networks [43]. To become commercially feasible and to compete with electronic computing in specific applications, research effort has focused on moving from analog optical processors to digital optical processors. Thanks to the invention of vertical-cavity surface-emitting lasers (VCSELs) in the early 99s, several digital optical computer architectures were demonstrated. For instance, sponsored by the Naval Research Office and NASA, Stone et al. proposed a 3-bit fully-programmable digital optical computer (DOC II) designed to operate in a UNIX environment and run basic RISC microcode [45]. The system is based on laser diode arrays, multichannel SLMs, and avalanche photodiode arrays. By using data input in a dual rail format, parallel microcode implementation was achieved, including an architectural balance of optical interconnect and software code efficiency. Rudokas et al. demonstrated a programmable optical digital ALU by implementing some RISC instructions on DOC II, demonstrating gate interconnect bandwidth products (GIBPs) of up to 6 with power consumption of the order of W [46]. However, optical processors still have no solution to tackle computing science issues such as complexity, accuracy, decisions and reliability. Indeed, electronics is far more mature and can do almost anything optics can do in digital computing applications with much lower cost. Moreover, as highlighted by Caulfield and other researchers [3], even in domains more naturally suited to optics, e.g. Fourier transforms, electronic chips have overwhelmed optics in terms of throughput and accuracy...3 Lessons and observations Much can be learned from this lesson and some of the most important reasons behind the predominance of electronics over optics for computing can be summarized as follows:

48 Chapter Introduction 9 - The accuracy advantage of electronics results from its being digital. Arbitrary accuracy can be achieved at the cost of breaking computation tasks into smaller tasks such that error rates are minimized, and errors can be corrected with more computation. The use of analog optical processors implies the use of a large, not-so-accurate computation system. In addition, a digital computer is more flexible than an analog one - to change functionality, analog hardware must be changed since there is no provision for hardware reconfiguration; while changing functionality in a digital computer can be achieved by changing the instruction inputs. Therefore, it is crucial to design reconfigurable optical computing hardware which is flexible to evolve with the evolution of the computing applications. - A common term used in reference of optical computing is computing at the speed of light. Processing information by light can be faster than by electronics under some circumstances, but there are limits to this. Firstly, according to [3] and [38], electronic signals in copper wires and optical signals in guiding materials (e.g. fibers, silicon) have approximately the same upper speed limit. We know that a closely spaced bundle of wires suffers from some physical effects, such as capacitive coupling and electromagnetic interference of electrical signals, which can dramatically reduce the transmission speed of electrons by some orders of magnitude. However, closely spaced optical fibers (or optical waveguides) lead to an even worse situation: information leaks between them within the nominal numerical aperture of the fiber (or due to phase coherent energy transferring between waveguides) [3], such that the received information is not the transmitted information. And secondly, computational performance is obviously not measured in centimeters per second, though the speed is one factor in performance of computing components. Indeed, in current silicon CMOS transistors with ~nm critical size, electron can travel at the speed in the picosecond range with a future projection in the range of femtosecond (considering that the typical saturation velocity that can be reached by an electron is x 7 cm/s []), which is comparable to the internal propagation speed can be achieved by photon in an optical switch (assuming a typical optical signal propagation length of tens of micrometers and the photons travel at a speed close to ~ c/3 (c is the light speed in vacuum). The carrier velocity in transistors definitely contributes to the device switching speed, as does the channel length of transistors and the voltage applied across the transistor tunnel. While reducing the transistor size reduces propagation delay at constant carrier speed and consequently increase the device operating speed, the energy dissipated by transistors increase significantly. In contrast, the only fundamental limit on the switching time of optical switching devices arises from the

49 Chapter Introduction energy-time uncertainty [53]. In principle, the switching energy consumption of an optical switch can be as low as several hundred attojaules if the device operates at a very high speed ~c/3 (the switching time in a range of sub-picosecond). In particular, the switching time will be accumulated for (larger) electronic circuits with more transistors in series, while it is noncumulative for larger photonic structures consisting of more optical switching elements, since all these elements integrated in a photonic circuit can be driven simultaneously, thereby potentially leading to low latency and high bandwidth. - Lower interaction between photons makes it more difficult to construct switches similar to electronic transistors (fundamentally two electrons cannot be in the same place at the same time due to their strong interaction), which are the core component for computing. Although a lot of research progresses were made in optical switches processing logical operations using nonlinear optical effects [33], it is impossible in the foreseeable future that optical devices can have a size roughly equal to that of the electronic switches, and most importantly, optical switch would consume a lot more power for generating nonlinear effect between photons and the material used. Moreover, a fundamental difference is that an electronic switch will block the current flow, while an optical switch deviates the photon flow to somewhere other than where the information will be detected. Whatever the state of the optical switch, light is being generated and energy consumed. Also, optical memories that are based on the storage of photons have been difficult to achieve, whereas electronic memories rely on the simple storage of electrical charges on a capacitor. However, optics is still potentially suitable to design switches in future. On the one hand, potential breakthrough may be made with the technological advance of the materials with optical nonlinearities in the coming yeas. On the other hand, the unique properties of light (e.g. light spectrum, phase, and polarization) and the pulse-based representation of information, rather than levels of light intensity, might play a beneficial role for computation. Furthermore, for non Von- Neumann computing paradigms, e.g. neuromorphic computing, some fast optical nonlinear effects can be used to design high speed switches with rich intrinsic dynamics and consequently facilitate the neural behaviors in these systems [77]. - The featured advantage of optics over electronics for massive data transmission comes from the fact that incoherent light beams do not interact with each other during propagation, and each can behave independently in some respects. But it happens to be a critical drawback for optical computing, since even the interference of two optical signals takes place under specific conditions [53,5]. Therefore, writing information (like

50 Chapter Introduction bitstreams of data) onto the light beam commonly uses electronics - electro-optic modulators and photodetectors explicitly serve at this role. Implicitly, even switching devices based on nonlinear optics have to use electronics (i.e. carriers) for achieving much lower power consumption than those use pure optics. Consequently, the physical conversion between optics and electronics is a prerequisite component of optical computing systems. But ironically, with the use of electronics, the overall performance of an optical computing system is often limited by that of the input and output interfaces, which are commonly the slowest (i.e. highest latency) and most energy consuming parts. In short, the limitations of the optical computing systems are within the electronic interfaces, and it is therefore difficult to improve the performance by directly replacing electronics with optics in the computing systems. Therefore, the future optical computing architecture has to stay in the domain of optics as much as possible and limit the usage of electro-optic interfaces..3 Optics in computing: what next? In light of these experiences, what now are the appropriate roles that optics can play for information processing and what are the perspectives for optical computing? It would appear clear that while it is illusory to consider that optics can directly compete with electronics based computing, it can fill a useful role in niche functions to help computing systems work better [3-34]. In terms of the different formats of the information that are required to be processed: - If the input and output information are in optical form (e.g. optical images), then when performing operations such as correlation, convolution and optical Fourier transformation in real-time image processing, optical approaches are favorable. In this situation, electro-optical conversions are no longer needed. Moreover, there is no need to force optics to behave as electronics in such systems, thereby taking advantage of the intrinsic properties of light for achieving computation with potentially high bandwidth and low power consumption. - On the other hand, if the input and output data are non-optical, then it might be better to associate optics with electronics to implement some functionalities that pure electronics is less efficient at doing. This can be interpreted as follows:

51 Chapter Introduction - Electronics commonly handles complexity in two ways: the use of space (e.g. parallel buses, multi-cores) and time (e.g. pipelined datapaths), but optics has a third vector: wavelength. Many independent light beams at different wavelengths can be modified, commonly or independently, by a single control signal in an optical information processing system. This is very promising to create highly-parallel powerful computing architectures. Indeed, as we will discuss in the following chapters, the wavelength vector plays a fundamental role in the reconfigurable photonic logic architecture proposed in this thesis. Additionally, optical technology can implement massive, parallel, arbitrary mapping from an NxN input array form to an N N output array form using N weighted interconnections through N wavelengths [3], where the phase of optical signals is critical for weighted interconnections. Such a function can serve as the backbone of a massively parallel neural network e.g. reservoir computing [77] [35]. Because of this, optics can be exploited to perform parallel computation tasks for parallel computing architectures integrating massive logic components. - Optical computing may help to alleviate heat generation issues in electronic processors. As mentioned before, the heat problem of electronic devices worsens as operation speed increases and device geometry decreases: faster operations require more power, while smaller devices occupy less area from which the resulting heat is more difficult to remove. Optical systems, however, do not increase heat dissipation significantly as compared to electronic chips when increasing the operation speed. This aspect has been demonstrated by many computing systems based on optical network-on-chips (ONoCs). - Digital computing systems do not handle continuous data well. It was once thought that continuous-time computations could be approximated arbitrarily with current computing systems. However, the study of chaos shows that this is not true, for example when using such systems to manipulate continuous variables [37][4]. For example, it is possible to transform a continuous-time function into the discrete-time domain using digital sampling and transformation techniques, but it is impossible to perform continuous-time transformations on continuous-time signals directly in the digital domain. In this case, analog techniques (i.e. in the optical or electrical domains) are needed. Optics has the inherently continuous properties defined by wave theory and wave equations, so optics might be favorable for solving this type of problems. From this point of view, an analog optical processor could operate at a much higher data rate than analog electronics in analog computing systems processing continuous operation. This is seen from recent trends in designing optical reservoir computing systems

52 Chapter Introduction 3 for carrying out the recognition tasks and generating continuous signals [77][35], which typically use an interconnected array of nonlinear optical components. - Power consumption is one of the main bottlenecks in current computing systems. In electronic circuits, performing any logic operation consumes a finite (and small) amount of energy. As a complex logic function is commonly decomposed into small sub-functions, a great number of intermediate logic stages are necessary. These logic stages generate useless logic data and lead to high energy dissipation. However, this could be avoided in an optical computing system that generates results by the manipulation and the propagation of light. For example, Directed Logic [34] (see section.. for more details) has been recently proposed. It performs logic operations by directly propagating a light beam through a network of interconnected optical switches. Since the intermediate logics and their dissipated energy are avoided, the total energy dissipation of the logic circuit could be potentially reduced. - Finally, optical memories, i.e. holographic memories, seem to be very attractive for being potentially high density and enabling parallel data access, as compared to conventional memories [4]. Research in this aspect has been started from the early 96s, which is marked by the development of the theory of optical storage through using 3D materials []. Shortly after that, holographic memories using films such as synthetic holography has been proposed for recording and storing digital data in the Human Read/Machine Read (HRMR) system [3]. Rapid progress was made in the 98s and 99s in developing 3D parallel access optical memory. For instance, Marchand et al. proposed a motionless-head parallel readout optical-disk system with a maximum data rate of.gb/s [4]. In addition, there were some start-up companies created for developing holographic memories but most of them disappeared. One of them however has commercialized a holographic disk memory product based on photopolymer material [7]. Today the holographic memory is still a candidate for future memories. However, this choice is limited by the recording material, and particularly by the fact that there is no explicit method to use cheap rewritable material [3]. We discussed here some roles in future computing systems that optics could be suitable for. There are probably other roles that optics could play that electronics cannot, such as zero-energy logic, or quantum computing etc. However, all these propositions are still in the early stages of research and need to be investigated further.

53 Chapter Introduction 4.4 Objectives and thesis outline The work described in this thesis aims at the design of a new reconfigurable computing architecture that can be implemented in a silicon photonic integrated circuit, so as to address the energy, bandwidth and reconfiguration issues of conventional computing architectures. This work lies in the context of optical computing but with a focus on on-chip reconfigurable computing, at the boundary of computing system design and photonic device modeling. The outline of this thesis is given as follows: This chapter has given an introduction to the background of information processing systems, including an overview of the technological challenges in electronic computing systems and trends of using optical technology for on-chip communication. It then reviewed the historical evolution of optical computing with a focus on the lessons and the reasons behind the lack of success of optical computing. Finally, we summarized the roles that optics could play in computing systems by analyzing some important features that optics has. Chapter reviews the various types of computing architectures and highlights the major challenges in conventional reconfigurable computing architectures (e.g. FPGAs), particularly the high power consumption and low computation capacity. It then discusses the current trends of emerging technologies for implementing reconfigurable computing architectures, such as 3D technology, emerging nano-memories and optical technologies. This chapter then focuses on the state-of-the-art optical computing architectures. The analysis shows that the optical approach can be used to implement reconfigurable computing systems with the promise of reduced latency and energy dissipation. Chapter 3 proposes a reconfigurable block based on silicon photonics, the optical look up table (OLUT) and associated logic architectures. We start by introducing a basic OLUT block that is equivalent with an electrical LUT. It then presents the OLUT with multiple outputs by taking advantage of WDM for parallel computation, thereby resulting in higher bandwidth, higher hardware efficiency and potentially lower energy consumption. The operation principles and filtering schemes of OLUTs are investigated followed by a preliminary performance evaluation of OLUTs through an example of a full-bit adder. Progressively, we extend the initial OLUT architecture by proposing a complementary logic output to simultaneously perform a pair of complementary logic functions, leading to higher computational efficiency with reasonable hardware overhead.

54 Chapter Introduction 5 Chapter 4 proposes one physical implementation of OLUTs. It is thus devoted to the multilevel modeling of this OLUT architecture, including the physical-level design of its key building block, i.e. an electrically controlled add-drop filter. It lays the foundation for the system-level performance evaluation with a strong emphasis on the energy dissipation of OLUTs. It offers an analysis of the transmission response of the add-drop filter in both passive and active regimes through coupled mode theory and explores a range of electrically controlled optical signal modulation schemes, focusing on carrier manipulation through a PIN junction. It then subsequently analyzes the optical losses occurring in the photonic circuit layout for the OLUT system. Finally, the complete energy model including the contribution of all the active components in OLUT is described. Chapter 5 presents the performance evaluation results for the OLUT architectures by using the multi-level modeling approach and the energy model described in chapter 4. In the fist part, the energy dissipation of the n-m-olut architecture is evaluated by calculating the feasible design space for the parameters of add-drop filters. The impact of the input and output dimensions of OLUT on its energy efficiency is well studied. Its second section explores the OLUT with the complementary logic interface for further improving the computation performance and energy efficiency of OLUT. The input optical laser power and area cost for performing complementary logic computations in the n-m x -OLUT architecture is also analyzed. Chapter 6 concludes the thesis and discusses the perspectives of the proposed OLUT as a reconfigurable computing paradigm for the future. In particular, an all-optical OLUT based on an all-optical input and output interface is proposed for the cascade of multiple OLUTs.

55 Chapter Introduction 6

56 Chapter Emerging technologies for reconfigurable computing 7 Chapter EMERGING TECHNOLOGIES FOR RECONFIGURABLE COMPUTING This chapter reviews emerging technologies for implementing reconfigurable computing architectures, with a focus on silicon photonics technology. Due to a variety of reasons such as increased power consumption, heat generation and current leakage in integrated circuits, the performance of microprocessors is no longer increasing exponentially. Silicon photonics is considered as a potential solution to help microelectronic chips continue to improve performance per unit energy ratios. Silicon photonics is already widely used for optical interconnects and data communication in high-end computing systems, i.e. data centers, networks etc. It also holds the promise for realizing on-chip reconfigurable computing architectures. The chapter is organized as follows. Section. first gives a brief introduction of the FPGA architectures, and then discusses key challenges and solutions, including a survey of some important trends to design future FPGAs. The potential benefits of emerging technologies, such as low power consumption, low latency, low cost and high performance are analyzed. Section. introduces the silicon photonics technology and shows the related work that exploits it for implementing reconfigurable computing architectures.. Emerging technologies for reconfigurable computing architectures.. Introduction to computing architectures The computer architecture is the conceptualization of the fundamental operating principles of a computing system [55]. It commonly considers how to use hardware components and design the software to implement the computing systems that meet functional, performance and cost targets. Three main architectural options are general-purpose processors, application-specific integrated circuits (ASICs) and reconfigurable computing systems (usually) based on field-programmable gate arrays (FPGAs). General purpose processors (GPPs) execute sequentially a set of software instructions to perform a computing task. They are applicable to most of the tasks thanks to their flexibility introduced by software programming. However, since their hardware is not optimized for a specific application [56], they are energy consuming and performance inefficient for many emerging tasks. Conversely,

57 Chapter Emerging technologies for reconfigurable computing 8 ASICs are dedicated hardware devices that are specialized to a particular application. For a given computing task, ASICs achieve better performance with lower power consumption and less area utilization than GPPs. However, due to their fixed nature, ASICs cannot be modified when the target application changes, such that, although it can offer the best performance for a specific application, it cannot be used for other applications. Additionally, an ASIC chip is considered to have higher non-recurring engineering costs, implying that development is time-consuming and fabrication expensive [57]. Reconfigurable computing offers an alternative architectural option to GPPs and ASICs by allowing its hardware components (i.e. logic blocks and interconnects) to be configured and customized to suit a specific computing task through post-fabrication and user-defined programming [54]. They offer higher performance than GPPs while achieving a higher level of flexibility than ASICs. For instance, a point multiplication with a key size of 7 bits can be computed in.36ms in a reconfigurable system implemented in an XCV6 FPGA driven at 66MHz while an optimized software implementation takes 96.7ms on a dual-xeon computer driven at.6ghz [55]. This therefore demonstrates a 54x computation speed-up in reconfigurable systems while its clock rate is almost 4 times slower than the microprocessor. The main issue to be addressed for reconfigurable computing is that its flexibility comes at a higher cost in speed, area and power consumption than the ASICs [55][59][6]. But the flexibility may advantageously lead to a shorter time-to-market and lower non-recurring engineering costs, thereby relaxing the budgetary and R&D constraints. This makes reconfigurable computing systems a better alternative than ASICs for many applications in future network, computer, data centers and communication systems. This trend has been recognized by researchers in the FPGAs in 3 workshop in. By reviewing the history of programmable devices over the last years and then extrapolating it for the next years, they concluded: in 3, every system-level device will have to be programmable: at run time, the chip will have to configure its still-functioning resources into a working system. [56] To date, most reconfigurable computing architectures commonly rely on FPGAs as the core processing unit. This will be introduced in the next section. We then discuss the challenges of FPGAs and take a look at the emerging technologies for reconfigurable computing.

58 Chapter Emerging technologies for reconfigurable computing 9.. FPGA Overview FPGAs are prefabricated semiconductor chips that typically consist of a large number of configurable logic blocks ( CLB ) which are interconnected via a configurable dynamic routing network, and configurable I/O (Input/Output) blocks [58], as illustrated in Fig.3. (a). If initial FPGAs were homogeneous and only included the above-mentioned resources, they are now heterogeneous and integrate complex blocks such as dedicated multipliers, memories and even GPPs. The logic functionality for each block is provided by Lookup Tables (LUT), which contains SRAM (Static Random Access Memories) for storing the configuration bits of the required function. The n-luts produce a single-bit Boolean data output that is stored by n bit memories by propagating it from a n -to- multiplexing circuit through a data path specified by the input data, allowing any Boolean logic function of up to n variables to be implemented. Fig.4 (a) shows a -LUT circuit layout. It is built out of 4bit memories and a 4: multiplexer. Fig.4 (b) presents the truth table of the AND function, and Fig.4c) illustrates the -LUT used to implement an AND function associated with data paths according to different incoming data. Additionally, the basic logic elements (BLEs) that are included in the CLB contains a D-type flip-flop (DFF) for registering the output of the LUT in situations where sequential logic or clocking is required, such as pipelining, state-holding functions for finite state machines etc, as illustrated in Fig.3 (c). A complete CLB is a fully connected cluster of BLEs: each input of a BLE can be either connected to the same data input of the CLB or any output bit of other BLEs, while all the outputs of BLEs can be connected to the FPGA routing fabric as the output data of this logic block. The FPGAs are commonly programmed with a high-level language or hardware structural languages, e.g. VHDL or Verilog, to create the required logic functionality and interconnect architecture. The configuration bit stream needs to be generated through the synthesis process by using a commercial FPGA tool, e.g. ISE Xilinx. By downloading the bit stream onto the FPGA board, the values stored in SRAM cells are changed to implement the logic functions or realize a new connection.

59 Chapter Emerging technologies for reconfigurable computing (a) (b) CLB CLB Outputs (c) Programmable I/O Programmable Interconnect Inputs BLE Fig.3. a) FPGA architecture b) Architecture of the configurable logic block (CLB) based on a cluster of BLEs c) A basic BLE element includes a 4-LUT, a flip-flop and a multiplexer[57] / Input x Data Output x y z / Data a) / / y Z b) Inputs Outputs SRAM Multiplexer c) AND AND AND AND Fig.4. a) Diagram of a -LUT and b) Illustration of the AND function implemented by a -LUT

60 Chapter Emerging technologies for reconfigurable computing The primary trend impacting FPGA-based reconfigurable computing systems is Moore s Law. According to [6], since the birth of FPGAs, the gate capacity and device performance have improved at an exponential growth rate that is roughly identical to that of CMOS technology scaling. Due to the reconfigurable property of FPGAs, the computational performance penalty for a computing system implemented by LUT-based FPGAs compared to that implemented directly by ASICs is of the order of a factor of five. Regarding the energy consumption, it becomes the main limitation for the improvement of FPGAs. According to [67], the penalty of the static energy needed for maintaining the configuration data in FPGAs is more than ten times than that of ASICs, which is mainly consumed by the SRAM (38%), the interconnect (34%) and the LUTs (6%)[7]. The penalty of dynamic energy is of the order of 7 to 4, since the interconnection is not direct and the SRAM memories occupy a large area on the chip and consequently increase the wire length for interconnection. According to [66-69], the dynamic power is dominated by the interconnects ( in Virtex- FPGAs, interconnect, logic, clocking and I/O accounts for 6%, 6%, 4% and % of the total dynamic power [7]). In order to reduce the power consumption, some works have studied the power trade-offs according to different routing architectures, LUT size and cluster size. Results from [69] suggest that 4-LUT is the best logic block for area-efficiency and for minimized dynamic power consumption. Additionally, [7,7,66] proposed to use sleep transistors and dual supply voltage techniques into FPGAs for achieving a 5% reduction of power consumption. From the CAD aspect, [73] proposed a low-power operation mode for switches along with some power-aware mapping algorithms, and [73,74] proposed some high-level synthesis techniques such as behavioral transformation, variable supply voltages, low power binding and scheduling...3 FPGAs challenges and emerging technologies Past FPGA architectures relied on the predictable performance improvements of CMOS technologies. Fig.5 presents the evolution of the FPGA technology projected by the ITRS roadmap in terms of the number of configuration bits per chip evolving with years [75][5]. It shows that even though the cell size is decreasing and functions per chip are increasing, eventually standard FPGA technology cannot improve performance, while CMOS technologies come to reach their fundamental scaling limits. Traditional approaches in increasing FPGA computational power will ultimately lead to higher heat generation and

61 Chapter Emerging technologies for reconfigurable computing more stringent power/area requirements. Therefore, it is impossible for the pj/bit performance indicator to continue to decrease indefinitely with each technology generation. Alternatively, emerging technologies can help to break the performance/power (or energy/operation) barrier in FPGAs and potentially close the performance gap between FPGAs and ASICs. As initially projected by the 7 edition of ITRS, FPGAs using optical technology can potentially overcome the configuration complexity plateau, as shown in Fig.5. Emerging technologies promise to provide significant improvements in performance, energy dissipation, area and cost over conventional standard FPGA technology. They can be used to design new I/O interfaces, the dynamic interconnect fabrics, configurable logic cells, on-chip memory and improve the fabrication process of FPGA devices. Current trends for exploiting emerging technologies include the increasing interest in using 3D technology for interconnect and packaging [93-5], using nano-memories (e.g. STTRAM and ReRAM)[83-9], carbon nanotubes (CNT) to implement LUTs or switch blocks [78], and using silicon photonics technology to partially replace high level copper interconnect to increase the system bandwidth with low power consumption [5]. Configuration bits (Millions) EFPGA OFPGA Electronic FPGA(EFPGA) Optical FPGA(OFPGA) Fig.5. FPGA technology trend for EFPGA and OFPGA (taken from [75], initially derived from ITRS [5])..3. Non-volatile nano-memory devices The first important trend considers the use of non-volatile (NV) nano-memories. In FPGAs, the SRAM occupies a large die area and consumes high static power due to leakage

62 Chapter Emerging technologies for reconfigurable computing 3 current. Moreover, the SRAM is volatile, which requires all functions to be reprogrammed at each power-up. Replacing SRAMs with non-volatile memories to implement logic functions has been suggested many times in recent years, commonly including using Spin-transfer torque RAM, ReRAM or Nanocrystal Floating Gate FETs [5]. These emerging memories offer opportunities to incorporate more programmable logic resources and interconnect in FPGA chips, as they can create more compact and energy-efficient LUTs or configurable switch blocks in FPGAs. By leveraging the benefits of these devices, an improvement of typically to 3 times in the performance/power ratio of FPGAs at the current technology node is expected to be achieved [95]. Spin-transfer torque RAM (STT-RAM) is considered to be one of the most promising candidates for non-volatile memory using spintronics technology [76] which combines nonvolatility, excellent scalability and endurance with lower power consumption and high read and write speeds. Spin-transfer torque data writing is performed by passing an electric current to change the magnetic orientation of the information storage layer in a magnetic tunnel junction. By using such writing schemes, STT-RAMs promise to greatly reduce the power and die area and improve the write selectivity over conventional magnetic memories [77]. Compared with SRAMs, STT-RAMs have a much smaller cell size and an equivalent write speed. The non-volatile memory based FPGA architecture was proposed by Zhao et al. [77] in 9 and Torres et al. [79] in. In 4, FPGAs using STT-RAMs have been commercialized by Altera and Everspin, with the expectation of improving the application performance, data security and system crash recovery time according to the designers of Altera Inc. [8]. The configuration bits can be stored in STT-RAM cells and logic blocks can then be safely powered off, avoiding significantly noise or power failure. Moreover, the application of such FPGAs using magnetic memories can be considered to extend to aerospace or military fields which enable new computing features that conventional FPGAs cannot offer. For example, Goncalves et al. [83] demonstrated a -LUT using a compact model of the magnetic tunnel junction on hybrid magnetic/cmos 3nm technology, which allows an FPGA to be protected against radiation with low area overhead. The main challenges faced by the STT-RAM technology are i) the stochastic nature of magnetic tunnel junction, which leads to a non-deterministic transient behavior during switching activity caused by thermal stability, and ii) the high write energy consumption, given by the high intrinsic current when switching magnetization[95]. Many schemes have been proposed to minimize the writing energy while maintaining sufficient thermal stability for acceptable error

63 Chapter Emerging technologies for reconfigurable computing 4 rates, including relaxing the non-volatility of STT-RAMs through reducing the planar area of magnetic tunnel junction [85], tuning the saturation magnetization and the thickness of the free layer, etc. In [85], a cache model is developed to explore the trade-off between the nonvolatility, latency and energy in STT-RAMs, and a more than 7% reduction in energy-delay product is achieved by using a hybrid design of SRAM-based L caches with reducedretention STT-RAM L and L3 caches. Ping [86] proposed an early write termination scheme to improve the STT-RAM cache, which reads out the content of the cache before doing a writing operation, leading to 8% reduction in writing energy and 33% saving in total energy in their experiments. In addition, some new techniques have been invented to make use of the stochastic nature of magnetic tunnel junction. Zhang et al. use the stochastic feature as a way to maintain the thermal stability by proposing a multi-level programmable cell that can change states randomly. Another emerging memory technology for FPGA architectures is the rapidly evolving ReRAM, standing for Redox memory or resistive RAM. ReRAMs are based on a metal-ion conductor-metal (MIM) structure, which utilizes ion migration with a redox process to perform the resistive switching operation, involving the dielectric and/or electrode materials. Since the ReRAM device has the potential to scale down to very small feature sizes, the switching time can be as low as a few nanoseconds. However, many of the details of the ReRAM switching mechanisms are still unknown, which is the key challenge for the development of this technology. Rapid improvement has been made in several kinds of ReRAM and towards a commercial product, such as: the Conductive Bridge RAM that has been demonstrated exhibiting very good scalability and ultra-low energy dissipation[87], the Valence Change Memory which has progressed a lot in scaling (~nm critical size), endurance and retention time[89], The Thermo-Chemical Memory which can advantageously enable the vertical stacking of memory devices in a dense crossbar array [9]. In 3, Toshiba Inc. reported a basic read/write circuit for prototyping a -layer 3Gb ReRAM memory [9] on a 4nm CMOS platform, although details of the switching material and performance parameters were not given. Using ReRAMs in a reconfigurable switching application is also very promising [88]. Miyamura et al. proposed a programmable cell array and a 3x3 crossbar switch using a nonvolatile and rewritable solid-electrolyte switch, with

64 Chapter Emerging technologies for reconfigurable computing 5 each individual cell functionally equivalent to a 4-LUT. An 8% reduction in cell area and a 7% reduction in total chip-area compared with that of a standard SRAM based design is achieved on a 9nm CMOS platform D technology The second important trend is Three-dimensional (3D) technology. 3D integration technology allows for the vertical stacking of layers of basic electronic components that are laterally connected by using D interconnect fabrics. 3D integration includes 3D bonding, 3D stacking, and the use of a Si interposer structure that only contain interconnect layers. Several vertical interconnect methods have been explored recently, such as wire bonding, microbumps, contactless interconnection, and particularly the TSV (Through-Silicon-Via), which seems to be the most promising of all the candidates [5]. 3D integrated technology is increasingly viewed as an attractive solution in responding to the critical process-scaling issue for reducing area and power consumption [87]. As mentioned previously, interconnects have emerged as the main source of delay and power consumption in microelectronic chips. 3D integration may offer significant benefits for interconnect such as reduced wire length, higher memory bandwidth (by stacking the memory and computing cores with TSV connections), heterogeneous integration and smaller form factor, which can potentially lead to higher packing density and smaller footprint, and thereby lower fabrication costs [5]. However, 3D brings new challenges of its own, such as thermal issues, passive and memory interposer design, clock tree and power grid design as well as other challenges relating to physical and EDA tools [5,87]. As previously mentioned, the circuit delay in FPGA architectures is determined by the configurable interconnect part that might need to connect two computing resources at a significant distance between each other. 3D integration technology can reduce the interconnect length, thereby providing significant improvement in FPGA performance and power consumption [93,96,98-]. Moreover, as the interconnect accounts for a large portion of the silicon die area, the reduction of the interconnect area results in the reduction of manufacturing cost for FPGAs. In the past, much work has been done to implement 3D FPGAs by using 3D routing switches based on electrical or optical technologies [3], or by partitioning memory elements and routing functions over different layers []. Rahman et al. [] proposed an analytical model to predict the interconnect bandwidth requirements in FPGAs, which shows the opportunities for 3D implementation of FPGAs. They use 3D (6-

65 Chapter Emerging technologies for reconfigurable computing 6 direction) switching blocks for vertical interconnection, and all the FPGA elements were distributed between layers in a form of fine granularity. Experimental results showed that in a FPGA containing 7K logic cells that were fabricated in a.5µm process, the LUT density was improved by 5-6% in their proposed 3D implementation. Moreover, the interconnect delay was also significantly reduced by 45%-6% and the reduction in power dissipation ranged from 35% to 55%. [97]proposed a 3D non-volatile FPGA architecture, in which the basic FPGA structures were renovated, as well as the layer partition and logic density evaluation for 3D die stacking. By replacing SRAM cells in FPGAs with PCM cells (Fig.6), their simulation results showed that the logic density per bit can be significantly improved over 6 times against SRAMs in a basic FPGA architecture. In their work, the 3D integration is realized by using two layer die stacking: all the interconnect and switch components, as well as the memory elements in logic blocks are put in one layer; while all the logic blocks are located in another layer, and in between are the TSVs for corresponding vertical interconnections. Experimental results showed that the improvement in wire length, interconnect delay and power consumption was 55%, 45% and 35% respectively in 3D implementation compared with D baseline FPGAs. They also showed better results in logic density, interconnect delay and power consumption compared to Rahman s proposal. Fig.6. The basic FPGA architecture and the PCM cell used in a 3D non-volatile FPGA (source from [97]) In addition, researchers have developed some CAD tools to explore and evaluate the design using 3D FPGAs. Alexander et al. [98] proposed 3D place and route algorithms. Ababei et al [4] presented a fast placement tool for 3D FPGAs, in which the effects of 3D integration on circuit delay taking into account the interconnect wire length are investigated.

66 Chapter Emerging technologies for reconfigurable computing Optical technologies for reconfigurable computing Optical solutions have been proposed for on-chip interconnects and Input/Output (I/O), which could potentially significantly influence the field of FPGAs. As mentioned in previous section, 3D technology allows the heterogeneous integration of various types of components with different technologies on different layers, thereby allowing a layer with optical devices to be stacked on top of a layer implementing computing resources (i.e. microprocessors or configurable logic blocks). Optical solutions focus on increasing the interconnect bandwidth while decreasing the energy per bit by overcoming the intrinsic limitations imposed by the high losses of electrical interconnects, and on cost-efficient implementations that make the most of the unique properties of optical computing architectures. Although this is not yet mature, significant progress continues to be made in this emerging technology. For example, Altera Inc. demonstrated optical interfaces integrating state-of-the-art lasers and photodetectors on its most advanced FPGA in [5]. Fig.7 shows the architecture of this FPGA with its associated optical interfaces. The FPGA is integrated with transmitter optical sub-assemblys (TOSAs) and optical receiver sub-assemblys (ROSAs), such that chip-to-chip links between FPGAs can be implemented through high bandwidth optical fibers instead of electrical wires. This optical interface currently provides maximum data rates of 8Gbps on the 8nm process node, and probably will increase to 4Gbps at the nm or 4nm node. In addition, Altera argued that the use of this FPGA with optical interfaces in a data center could provide significant power, density and cost saving advantages over conventional technology for wire distances in the range of less than.3m up to more thanm [5]. Fig.7. Altera optical FPGA architecture[5] In standard FPGAs, routing delays typically account for 5-95% of the total system delay, and more than 6% of the total power can be dissipated by electrical interconnects (including clock networks). The die area and power consumption both increase dramatically if electrical interconnect scales up. The potential advantage of optical technologies is that the

67 Chapter Emerging technologies for reconfigurable computing 8 power consumption of an optical link is relatively independent of the line length, and the optical waveguide loss can be as low as.db/cm in an SOI platform. In addition, unlike electrical signals, optical signals are immune to electric-magnetic interference and have less crosstalk, providing better signal integrity. Moreover, with WDM technology, multiple independent signals can be transmitted in each optical waveguide, leading to high bandwidth and lower hardware utilization. [75] predicted in their experiments that if the interconnect delays could be mitigated through the use of optical technologies, the Celerity TM accelerator would go from 3MHz to 65MHz with a 5% clock rate improvement. In addition, an increase of approximately times in configurable logic blocks and computational power with higher parallelization could be achieved if the interconnect area was decreased by using silicon photonics and the WDM technology. Indeed, an optical FPGA made with programmable optical logic cells and optical interconnects was identified as a future direction for signal processing and optical supercomputing in DARPA/MTO Microsystems technology symposium in 7 [56]. The main challenge is to design efficient reconfigurable optical routers and interconnect architectures that satisfy the flexibility, power, area and cost requirements. Recent progress has been made by D. Prather et.al [75] who proposed an optically interconnected reconfigurable switching system based on the confinement and dispersive properties of photonic crystal structures, which includes fixed planar and 3D routing structures, crossbar switches for reconfiguration and electro-optic modulators for signal encoding. Preliminary results show that this system is very promising to replace the full crossbar switching system. To take full advantage of optics in future FPGAs architecture, it is crucial that the programmable optical computation core performs logic operations in the optical domain. If such an optical logic core could be realized, the optical routing fabric could seamlessly interconnect all optical logic blocks without electrical-optical conversion interfaces, leading to a significant reduction of power, area and delay, in a true all-optical FPGA. Within this context, our work is to propose an optical core implementation of reconfigurable computing cells by taking full advantage of the silicon photonics technology. In this section, we briefly overviewed the FPGAs with a focus on emerging technologies that could offer better performance, energy-efficiency and lower cost for reconfigurable computing systems. However, to realize their full potential, architectural innovation is required. For example, emerging non-volatile memory requires re-architecting memory and storage systems, and optical technologies imply a rethink of the computing

68 Chapter Emerging technologies for reconfigurable computing 9 architecture to make the most of the properties of light. In the next section, we will discuss state-of-the-art optical reconfigurable computing architectures.. State-of-the-art: Silicon photonics based computing architectures.. Background Silicon photonics is an emerging technology platform for implementing photonic integrated circuits (PIC). On a PIC, information is transferred and processed by using photons instead of electrons on a chip. There are a range of material candidates for PIC technology: doped glass, III V semiconductors, polymers, silicon, and others. Silicon is the most promising among them due to the high refractive index contrast in the silicon-on-insulator (SOI) platform. It supports strong confinement of light through defining submicron waveguide circuits and thus allows the large volume integration of optical functions on a single chip. As mentioned earlier, the main driving force for silicon photonics is the development of optical interconnects. But due to its compatibility with CMOS technology platform, the potential of silicon photonics can be extended to computing as well. Within this context, new optical computing paradigms inspired by silicon photonics technologies have been proposed. In this section we first introduce the directed logic circuit and the reconfigurable directed logic circuit, and finally we discuss their limitations and challenges... Directed Logic Directed logic (DL)[] was introduced as a logic architecture based on modified optical Fredkin-like gates. A DL architecture is composed of optical switches interconnected through waveguides. The switching state is controlled by an electrical input logic signal. All switches can change their state simultaneously with this input electrical signal, and the operation of each switching element is independent of the operation of the other elements in the circuit. Fig.8 a) illustrates the basic switching element operations in the DL architecture for an input vector (, ). If the control signal is logic, the input vector will pass through the switch to produce the same result at the output ports as its input (,), otherwise, if the control signal is logic, the components of the input vector will be switched at the output, thus producing a logic vector (,).

69 Chapter Emerging technologies for reconfigurable computing 3 The computation of the logical function is performed by the directed circuit as a whole. Considering an OR/NOR circuit that is implemented by 3 optical switches []: Fig.8 (right hand side) depicts the circuit with input optical vector (,), the input signals A and B control the operation of each element, and A is the replication of A. The output vector of the switch with control A is split to form intermediate vectors serving as the input of the subsequent switches (i.e. with control B and A ), which then output the pair of complementary bits of the required logic operations. For example, if A is logic, the scalar takes the bottom path and then it propagates to the OR output port without being affected by the value of B; otherwise, if A is logic, then the outputs depend on the value of B. Similarly, if B is logic, it will pass the logic to the second downside switch and yields the value at the output port OR, and the zero value of B will yield the value at the output NOR. The optical signal representing the value will always arrive at one of the NOR or OR outputs, while the other will have the value. In the same way, other basic logic circuits such as AND/NAND and XOR/XNOR could be implemented but require a different interconnect. The main advantage of the DL architecture is the reduction of the latency. Latency is the sum of the propagation delay on the signal path and the switching delay associated with the switching state changes. In traditional logic architectures, the switching time for state change upon the input values are accumulated before the final result is computed. The operation speed thus decreases with the increasing circuit complexity. However, in this directed logic circuit, all the switching nodes perform change simultaneously, such that the circuit is slowed by only a single switch delay on entire path. Another advantage is that the directed logic can be conservative and reversible, since its number of inputs is equal to its number of outputs. The main limitations of this original DL architecture are: first, while DL circuits improve the computation latency as compared to traditional logic architectures, the interconnections are fixed and the optical switches are non-configurable, leading to an application specific architecture. Second, the optical switches are cascaded in such a way that light has to propagate through a long chain of switches in the worst-case scenario, which imposes a significant limitation on the scalability of the DL paradigm due to the losses encountered by the optical signal. Logic minimization and optimization are thus required to expand the DL paradigm from the implementation of a single logic operation to more complex computing operations. Moreover, the long optical path will increase the propagation time of the optical signal. Specifically, when optical micro-resonator based add-drop filters

70 Chapter Emerging technologies for reconfigurable computing 3 are used as the switch, the optical signal going to the cross port of the switch experiences an additional delay determined by the photon lifetime of the resonator. Hence, cascading a large number of add-drop filters can result in a large latency that is comparable to that of the electronic transistor based logic. Fig.8. Conceptual architecture of dedicated Directed Logic circuit []..3 Reconfigurable Directed Logic The DL architecture can benefit from the recent advances in silicon photonics technology (e.g. silicon microring modulators [5,6,8]). Significant improvements in reconfiguration capability and scalability have thus been offered with the proposal of the Reconfigurable Directed Logic architecture (RDL) []. The RDL architecture is composed of two planes of (re)configurable add-drop based cells (Fig.). It allows logic functions (written as sum-of-products operations) to be mapped: the first and second planes are configured to implement products and sums, respectively, with the sums are expressed using the relationship between OR and NAND functions. Each plane is based on optical switches interconnected through an array of optical waveguides. Two implementations of optical switching elements have been proposed for the RDL circuit: the x switch cell, or the expanded switch cell, as shown in Fig.9 a) and b). The x switch is a single microring resonator side-coupled to a straight waveguide, while the other one consists of a x switch plus a x switch. The incoming optical signal can be passed or blocked depending on its wavelength relative to the resonant wavelength of the switch, which can be modified in different switch modes. By using different reconfiguration signals (e.g. thermal signals) to tune the initial resonant wavelength of ring resonators, the switch states can be reconfigured for implementing different logic functions. Fig. shows the corresponding switch operations and their corresponding representations. The black lines represent optical waveguides, while the red lines represent the electrical lines carrying the logic signals. Solid

71 Chapter Emerging technologies for reconfigurable computing 3 squares represent the switches configured to allow an optical signal to pass (or block) when the logic input is (or ), while the switches pass (or block) the optical signal when the logic input is (or ) are represented by hollow squares. For expanded cells, the square is replaced by a triangle to represent the case when the optical signal crosses the x switch and then it propagates on a waveguide different with the initial one (equivalently represented by the symbol with two crossing lines in Fig.). (a) ring (c) (b) Fig.9. RDL basic circuit example and switching cell: (a) optical micrograph of a x electro-optic switch [5] (b) a RDL circuit implemented by x switches [5] (c) an expanded RDL cell based on a x switch [] for realizing XOR port

72 Chapter Emerging technologies for reconfigurable computing 33 Control= Control= Blocked Template pass cross not pass cross yes cross pass not cross pass yes Fig.. Representation of the switching elements in RDL circuits and their different configurations x = y = c in = c out = Sum = D D λ x y c in = λ x y = D λ ( x y ) c in = λ λ Fig.. A -bit full adder implemented by RDL architecture and the associated light paths when the input data is set to x = y = and c in =. The D element is a photodetector that effectively performs an optical-electrical conversion Fig. illustrates a -bit full adder implemented by such an RDL architecture using microring resonators. The basic logic equations for sum and carry in a -bit full adder are: sum = x y cin, cout x y + cin ( x y) =. The XOR function can be directly implemented with the logic cell but the OR function cannot be implemented directly. Therefore it should take advantage of the inverted output function that is expressed as c = x y + c x ), and out in ( y then converted into c = x y c x ). This is the expression that is mapped onto the RDL out in ( y circuit in Fig.. It is worth noting that the inverted product is realized by using the switches in the fourth configuration mode in Fig., which functions as a switch passing light to produce a logic when the input data (control bit) is. In Fig., the red line indicates the incoming continuous-wave laser signal at the wavelength λ, while x, y and c in represent the input data, and Sum, c out represent the sum

73 Chapter Emerging technologies for reconfigurable computing 34 and carry-out data at the output. The first plane, based on three pairs of parallel waveguides, computes three products (one for the Sum and the other two for calculating c out ), which are then converted into electrical signals to control the switches in the second plane through an OE conversion module (an array of photodetectors, represented by grey squares in Fig.). In the example of Fig. (when x = y = and c in =), the optical signal injected on the highest horizontal waveguide propagates through the first switch, crosses successively the second one and the third one before reaching the OE conversion module, thereby generating an electrical signal of logic for tuning the switch on the second output column to the pass state. As a result, light injected from the bottom of the vertical waveguide in the second plane can reach the photodetector, thus producing a logic at the output port Sum. For computing the c out, since the input optical signals are blocked by the second switch in the first plane, the control bits for the switches on the first vertical waveguide are logic. Upon the configuration of these switches, light directly passes them and generates a logic on the output port c out. In the worst-case scenario, light has to pass two crossing-state switches and one pass-state switch in the product plane, photodetector between the two planes, 3 off-resonant switches in the sum plane and photodetector at the output port. The RDL architecture has significant limitations. In RDL, logic functions must be expressed in the form of sums of products, which are typically fed into the integrated photonic circuit via a two-plane cascaded full cross-bar network of electrically controlled microresonators, leading to significant hardware cost for this programmable architecture. For example, to implement a k-bit full adder (the number of input bit is k+, the number of output bit is k+) with RDL architecture using expanded cells (each requiring three microrings), k +k+ products are required, and 3(k +k+)(3k+) microring resonators, as well as k +k+ lasers and photodetectors are needed. Indeed, considering the history related to the design of reconfigurable computing architectures, the area costs of two-plane implementations quickly become prohibitive. In addition, RDL circuits do not allow multiple and distinct operations to be computed simultaneously using different wavelengths. Yet, the parallelism as offered by WDM to save energy and hardware resources is a major advantage of optics for computing. As we will present in Chapter 3, to make the most of silicon photonic technologies, the use of WDM is a fundamental vector for creating powerful computing architectures. In RDL multi-spectral circuit, multiple wavelengths are used to perform a single operation and generate one output bit[5]

74 Chapter Emerging technologies for reconfigurable computing 35.3 Conclusions In this chapter, we presented an overview of FPGA architectures and discuss the current trends of emerging technologies for implementing reconfigurable computing architectures that could offer better performance, energy efficiency and cost. We then examined the stateof-the-art optical computing architectures, and showed that the optical approaches can be used to implement reconfigurable computing systems with the promise of reduced latency and energy dissipation.

75 Chapter Emerging technologies for reconfigurable computing 36

76 Chapter 3 OLUT Architecture Design and Implementation 37 Chapter 3 OLUT ARCHITECTURE DESIGN AND IMPLEMENTATION In this chapter, we propose a novel reconfigurable logic architecture, the so-called OLUT architecture, specifically designed to exploit integrated silicon photonics for on-chip reconfigurable computing. The logical architecture introduced here enables the parallel implementation of combinational Boolean functions on input data through the use of WDM, making the most of silicon photonics technology. Section 3. first presents the principle of the OLUT architecture through a basic OLUT block with single output, which performs logic operations as an electronic LUT. We generalize the basic OLUT block to produce multiple output bits for performing parallel computations simultaneously (Section 3.), by taking advantage of a unique feature of optics, i.e. WDM. We then qualitatively evaluate the performance of this architecture through the example of -bit full adder. In section 3.3, we further increase the parallelism level of OLUT architecture by exploring the complementary logic interface, which enables better computation performance and lower energy-per-bit over the initial OLUT architecture with reasonable area and hardware overhead. 3. Single-output OLUT Architecture 3.. From electrical LUTs to optical LUTs OLUTs are directly inspired from electrical LUTs [8]. As presented in Section., an n-input LUT is interfaced through n data inputs, one data output and n configuration inputs connected to n bits static RAM (SRAM) memory. Computation is achieved by directly indexing, from input data, the operation result stored in the memory. Fig.(a) shows an electrical -LUT circuit layout. It is built out of 4 memory bits and a 4: multiplexer. In electrical FPGAs, the main advantages of LUTs are the constant computation time and their ability to realize any Boolean function depending on the state of the SRAM, leading to highly flexible architectures [54, 55]. A -OLUT block, providing a behavior equivalent to that of an electrical -LUT, is presented in Fig.3 (b). It uses an input optical signal at a wavelength λ as the equivalent of a

77 Chapter 3 OLUT Architecture Design and Implementation 38 power supply. The OLUT block has its input and output data in electrical form. Similarly to the electrical LUT, the OLUT is composed of two parts [8]: Routing part (left half of Fig. (b)): According to the electrical data inputs, a set of interconnected optical routers (for a possible implementation, see section 4..) drive the optical signal into one of the horizontal waveguides, acting as a :4 demultiplexer network. Memorization part (right half of Fig. (b)): composed of four electrically controlled add-drop filters and interconnected by four horizontal waveguides, it produces the required Boolean computation on the incoming electrical data. As for electrical LUTs, the executed Boolean function depends on the configuration bits stored in the SRAM memories that control the optical switches: logic '' and '' will respectively turn the attached add-drop filter to on- or off-resonance, thereby generating the corresponding output logic at the photodetector (brightness: logic and darkness: logic ). / Input Data Input Data Output y Data x y x z SRAM D λ / λ / / Output Data Z λ λ λ λ / λ λ / λ / SRAM Multiplexer Routing λ λ / λ λ stage Memorization (a) Electrical -LUT (b) Optical -LUT Fig.. Schematic representation of (a) an electrical -LUT and (b) its equivalent OLUT. 3.. Basic principle and switching operation The switching element actually holds the key functionality of selecting and redirecting an optical signal based on its wavelength. For clarity, we use different symbols for the optical routers and the optical switches in Fig., in the routing and the memorization part respectively, although these could all be physically implemented with the same optical component, for instance a microring resonator based add-drop filter (as explained in chapter 4). The relevance of this distinction will become more explicit when introducing the use of WDM in OLUT architectures in order to parallelize computations.

78 Chapter 3 OLUT Architecture Design and Implementation 39 For a given geometry and material parameters, the transmission spectrum of the optical switch is typically a spectral comb of lines and it can be modified through a control signal, resulting in a Through-state and a Drop-state: Through-state: the switch resonance (i.e. associated with a transmission peak) is mismatched with the wavelength of the incoming light, so that the optical signal continues on the same waveguide. Drop-state: the switch resonance is aligned to the wavelength of the incoming light, upon which light is redirected from the input waveguide to the other (e.g. orthogonal) waveguide, thereby exiting the component through another output port. The switching element can thus be considered to act either as a dynamically controlled x optical spatial router (unit cell in the routing part) or as a statically controlled optical switch that may change the direction of the optical signal depending on the data stored in memory (unit cell in the memorization part). Note that they require different performance characteristics: the former unit cell requires high speed dynamic modulation for operation with high data rate, while the latter has low or even no requirement in modulation speed as it is a steady-state switch that is only changed for reconfiguring the OLUT. For the rest of the thesis, we use the equivalent term add-drop filter for the switching element. Finally, although the symbol chosen for the optical switch seems to convey the idea of a microring, we highlight that this only represent one possible (maybe the most obvious one at the moment) implementation for the OLUT switch building block. a) AND b) AND c) AND d) AND Electrical -LUT e) AND D f) g) h) AND D AND D - x -OLUT λ λ λ λ λ λ λ λ λ λ λ λ λ λ λ AND λ D Fig.3. Example of an AND function implemented by a -LUT and a -OLUT: (a-d) the corresponding data paths/output on the incoming data in -LUTs, (e-h) the corresponding data paths/output on the incoming data in -OLUTs. Fig.3 (a-d) illustrates the data paths and output results when the electrical LUT is configured to implement a logic operation AND, each output generating a logic value or

79 Chapter 3 OLUT Architecture Design and Implementation 4 according to the electrical voltage. Fig.3 (e-h) show the corresponding scenarios in a - OLUT configured to process the equivalent logic function using a light beam at λ. In OLUTs, the corresponding output logic is generated according to the presence of light (scenario (e): logic ) or its absence (scenario (f)-(h): logic ) at the photodetector. For clarity, we represent the on(/off)-resonance switches that are spectrally (mis)matched with the incoming light signal by solid (/dotted) lines. 3. n-m-olut architecture 3.. Operation principles As mentioned previously, to make the most of silicon photonic technologies, the use of WDM is a fundamental vector for creating powerful computing architectures. While the OLUT described in Fig. (b) uses a single optical signal at wavelength λ thereby computing a single operation as in traditional LUTs, WDM can be advantageously implemented in OLUTs to realize simultaneous logic operations on the same input data. In this way, OLUTs potentially allow us to increase the performance/power ratio as compared to electrical LUTs. An m operation OLUT (so-called n-m-olut) thus interfaces n electrical data inputs to m electrical data outputs, using m optical signals at distinct wavelengths (λ,..., λ m- ). In the routing part, the m optical signals λ i ( i = m-) share the same optical path specified by the electrical input data set. In the memorization part, they are driven into m memorization stages (represented by m distinct columns), each of which is composed of n identical add-drop filters and interconnected by n horizontal waveguides. Each stage of the memorization part performs a basic Boolean function through a specific wavelength, all the stages operating in parallel thanks to WDM. Fig.4 depicts the example of a -4-OLUT configured to simultaneously process logic operations AND, OR, XOR, and XNOR at four different wavelengths, namely λ, λ, λ and λ 3 respectively. All four optical signals are driven, through the routing part, into one of the four horizontal waveguides of the memorization part according to the values of x and y input data. In the example of Fig.4, the input values x= and y=, drive the optical signals towards the first waveguide at the top. The optical signals will then propagate across the memorization part and, depending on the state of the crossed switches (as controlled by the SRAM configuration), each wavelength will continue on the same horizontal waveguide or will be

80 Chapter 3 OLUT Architecture Design and Implementation 4 selectively dropped to the vertical one, thereby producing a logic or a logic at the associated outputs. In this example, the optical signals at wavelength λ, λ and λ 3 are redirected into the vertical waveguides, resulting in logic values on the Z, Z and Z 3 output ports, while the optical signal at λ continues along the horizontal waveguide, resulting in logic at the output Z. X Y Z Z Z Z 3 AND OR XOR Buffer λ D D D D λ λ λ 3 λ λ λ λ3 λ x λ x λ λ λ λ λ λ λ 3 λ 3 λ x λ λ λ λ 3 Routing part Memorization part Fig.4. Functional representation of a -4-OLUT configured for processing parallel logic operations at four wavelengths. In the OLUT architecture, WDM is implemented by using two different wavelength filtering schemes (i) in the routing part, where all the optical signals, independently of their wavelength, are propagated along the same path, and (ii) in the memorization part, where each spectrally distinct optical signal is individually routed according to the configuration. For the -4-OLUT example (Fig.4): Routing part: The behavior of the switch in the routing part is illustrated in the Fig.5 (a) according to its DROP state (solid line) or THROUGH state (dashed line). The arrows represent the four incident optical signals for which the wavelength values λ, λ, λ and λ 3 are either ideally aligned with the switch resonant wavelengths (represented by peaks in the transmission spectrum) in the DROP state, or detuned by a wavelength difference λ in the THROUGH state. The wavelengths of the injected optical signal are regularly spaced consistently with the Free Spectral Range (FSR x ) of the switch. Hence, in case the add-drop filter is in the DROP state, all the signals are redirected to a given waveguide while, in the THROUGH state, all the signals propagate along the other waveguide.

81 Chapter 3 OLUT Architecture Design and Implementation 4 Memorization part: Fig.5 (b) and (c) illustrate the operation of the add-drop filters in the memorization part as well as their transmission spectrum. Compared to those of the routing part, their FSR is slightly larger (see FSRm and FSRm in Fig.5 (b) and (c)) so that at most one resonant wavelength is aligned with one wavelength of the injected optical signal: λ in (b) and λ in (c), respectively. In addition, their relative FSR should be slightly different to avoid the potential scenario where the add-drop resonances become aligned with the wavelength of the other optical signals after the tuning/detuning process. Having different FSR and distinct resonant wavelengths in the memorization part can be achieved by changing the device geometry (e.g. the microring radius) or through a thermal control [9]. As a result, only one signal wavelength is redirected to the vertical waveguide when the add-drop is switched to the DROP state (solid line), the other ones propagating through the same waveguide. Similarly to the add drop used in the routing part, all the signals propagate along the horizontal waveguide if the add-drop filter is in the THROUGH state (dashed line). While the -4-OLUT example is used to illustrate how basic logic operations are processed in OLUTs when using the WDM scheme, it should be reiterated that the dimension of OLUTs can be extrapolated to perform complex Boolean logic function on a larger number of inputs. By exploiting this feature, OLUTs can realize more specific applications such as full adders or Arithmetic Logic Units (ALU).

82 Chapter 3 OLUT Architecture Design and Implementation 43 a) Router ON Resonance DROP λ x λ λ3 THROUGH OFF Resonance DROP λ x λ THROUGH λ3 Transmission Spectrum at Drop port FSR x λ λ λ λ 3 λ b) λ Memorization Stage λ c) Memorization Stage DROP λ λ λ DROP λ λ λ λ 3 THROUGH λ λ λ 3 THROUGH λ λ DROP λ λ λ λ 3 THROUGH DROP λ λ λ λ 3 THROUGH FSR m λ λ λ λ 3 FSR m λ λ λ λ 3 λ λ Fig.5. Illustration of wavelength filtering schemes in the -4-OLUT. In a) router: when the add-drop filter is in the DROP state, all the signals are redirected to the DROP port and when in the THROUGH state, all optical signals propagate along the other waveguide. The transmission at the DROP port is represented on the right column. In b) λ and c) λ memorization stage, only one signal wavelength (i.e. λ and λ ) is redirected to the vertical waveguide when the add-drop is switched to the DROP state, the other ones propagating through the same waveguide, and all the signals will be forward to the THOUGH port if the add drop is in the THROUGH state 3.. Preliminary evaluation of n-m-oluts The motivation of this early comparison is to i) evaluate the scalability and ii) qualitatively estimate the potential of OLUT architectures as compared with RDL architectures []. Therefore, here we introduce a few key metrics to evaluate the hardware efficiencies (i.e. area size and power consumption) and the performance of n-m-oluts when increasing the number of input and output bits. Hence, the scalability of the OLUT architecture using WDM is estimated and the performance of OLUTs is compared with RDL for the full adder case. An in-depth study of OLUT performance and power consumption, taking into account the system constraints, will be carried out through the design space exploration in Chapter Evaluation Metrics The area and power consumption relies on hardware resources used in OLUTs. The area is an estimation of the surface occupied by the add-drop filters. Here, we estimate the system area size by qualitatively counting the total number of add-drop filters (N AD ) in the n-

83 Chapter 3 OLUT Architecture Design and Implementation 44 m-olut, as the sum of the number of add-drops in the routing part (N R ) and in the memorization part (N S ) (see Fig.6): AD R S n n N = N + N = + m (3.) In n-m-oluts, the electrical power consumption depends on the number of active devices, i.e. the number of lasers (m), photodetectors (m) and add-drop filters (N AD ). Note that for increasing n and m values, the add-drop filters rapidly pre-dominate the whole n-m-olut architecture, and become the critical building block. The detailed calculation of the energy consumption will be presented in the section 4.3 of the next chapter along with the device physical parameters, since these matters strongly depend on the specific implementation chosen for building the OLUT. In the following full adder case though, we analyze the scalability through counting the number of active devices for drawing an early comparison with RDL architectures. The last metric is the latency. The main contributions to the latency consist of the conversion time at the O/E interface (the time delay introduced by photodetector, τ conv ), the switching time for the routing part (τ sw ) and the accumulated time to cross each add-drop in the resonant state (for example τ res ~ps for a microring-based add-drop filter with Q~), both in the routing and the memorization parts. This time is much larger than the one needed to cross the add-drop in the THROUGH state. In addition, note that τ sw is equal to the switching time of a single router unit cell (i.e. ~ns for the example of electrically controlled silicon microrings [6,5,,5]) since all the router cell states are changed by the data in parallel. By considering the worst-case scenario, where light passes through n resonant routers in the routing part and one resonant switch in the memorization part, we estimate the associated total n-m-olut latency to be τ = + + ( + ) (3.) olut τ conv τ sw n τ res

84 Chapter 3 OLUT Architecture Design and Implementation 45 Input data: n bits / Output data: m bits m photodetectors / m lasers n - adddrop filters n n add-drop filters m memorization stages / / Routing part Memorization part Fig.6. General OLUT architecture and the associated number of components 3... Scalability of OLUT architecture Here, we study how the use of multiple wavelengths in OLUTs impacts the hardware resource (i.e. N AD ) to perform simultaneous computations, and how this scales with the number of input data, n. The result for an eight-operation test case is plotted in Fig.7. The latter provides a comparison of the total number of add-drop filters in n-m-olut systems that need to be replicated 8/m times (with m varying from to 8, respectively for eight n-- OLUTs to one n-8-olut) in order to perform the eight logic functions simultaneously. As expected, the number of add-drop filters in n-m-oluts increases with the number n of input data. However, the increase rate is lower for larger m, by taking advantage of wavelength multiplexing. The benefit of WDM in OLUTs therefore increases with the number of data to be handled. This can be readily understood from Fig.4: for example, where computing a logic function with 8 input bits, using a number of OLUTs having more output bits consumes less add-drop filters in total (the number of add-drops used ( N AD ) by the four architectures i.e. 8 n--olut, 4 n--olut, n-4-olut and n-8-olut are 488, 368, 558 and 33, respectively). The obtained result highlights that the hardware and energy resources of the n- m-olut routing part are shared by the m wavelengths, with the complexity of this part increasing with the number of input data.

85 Chapter 3 OLUT Architecture Design and Implementation n--olut 4 n--olut n-4-olut 3 n-8-olut N AD Number of Input Data (n) Fig.7. Total number of add-drop filters (N AD ) required for computing 8 operations simultaneously and according to n of input data,. The results for n-m-oluts replicated m/8 times are shown, with m varying between and Case study: k-bit full adder with carry The full adder is a critical building block for Arithmetic Logic Unit in computation applications such as the creation of microprocessor architectures, DSP, microcontrollers and data processing units. The basic logic equations for Sum and Carry bits in a -bit full adder are Sum = X Y C and C XY + C ( X Y ) in out =. Here we study the potential of OLUTs in terms in of low latency and low power consumption in the example of k-bit full adders. We compare the OLUT needed to implement this system with the previously discussed RDL architecture [] (see section..3). Fig.8 illustrates a schematic example of the -bit full adder that can be achieved using a 3--OLUT including 3 add-drop filters, lasers and photodetectors. The first and second memorization stages are configured to realize the Sum and C out computations on the wavelength λ and λ respectively. In the scenario (a), all the inputs are set to and the optical signals are thus driven, through the routing part, into the uppermost waveguide of the memorization part. Since both switches dedicated to λ and λ in the memorization part are configured to the DROP state (i.e. the attached RAM memories contain the logic value), both optical signals are redirected to the vertical waveguide and propagate through the DROP port, resulting in a logic value on the C out and Sum outputs. In scenario (b), a single input is set to ; the optical signals will thus be driven to the penultimate waveguide for which only the add-drop filter at λ is set to the DROP state, resulting in the logic value on the Sum output and the value on the C out port. By considering the worst-case scenario in terms of latency, where the optical signals cross 4 (on-resonant) add-drop filters in the DROP-state

86 Chapter 3 OLUT Architecture Design and Implementation 47 (e.g. C in =X=Y= and the add-drop filter in the memory is set to ), a latency of τ conv +τ sw +4 τ res is obtained. Sum C out C in X Y D D Sum C out C in Y X D D λ λ λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ λ λ x λ λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ λ x λ λ Routing part Memorization part Routing part Memorization part Fig.8. Illustration of OLUT configured for -bit full adder when inputs (a) x=,y=,c in = and (b) x=,y=,c in = OLUT (i.e. n =k+ for the number of inputs and m=k+ for the number of output bits), ~ k 4 k add-drop filters (obtained from k k + (k + ) by assuming k greatly larger than ) and k+ lasers with k+ photodetectors are required, and the latency is equal to τ conv +τ sw +(k+) τ res. We see that the number of add-drop filters used by an OLUT grows exponentially with the number of input bits when it is used to implement a full adder. One solution to overcome this scalability issue would be to split such a large logic function into smaller ones. For example, a k-bit full adder can be split into k -bit full adders with each implemented by a 3--OLUT with two output bits (one for Sum, the other for the carry bit C out ), and all of them cascaded by propagating successively their carry bits. By using this approach, the OLUT circuit would only use 3 k add-drop filters to construct the full adder. However, it would require a greater number of lasers and photodetectors (k lasers and k photodetectors). Tab. Comparison of RDL and OLUT performance for k-bit full carry adder When considering the implementation of the k-bit full adder application using an n-m- k-bit full adder Numbers of Active Devices Latency Laser Photodetector Add-drop filter RDL k +k+ k +k+ ~9k 3 τ conv +τ sw +(k+) τ res OLUT k+ k+ ~k 4 k τ conv + τ sw +(k+) τ res

87 Chapter 3 OLUT Architecture Design and Implementation 48 When considering the RDL implementation (see section..3) for the k-bit full-adder, the RDL circuit based on the expanded x unit cell structure requires k +k+ product to generate k+ output bits, and it consumes ~9k 3 microrings, k +k+ lasers and k +k+ photodetectors (each product or sum requires one laser and one photodetector in RDL). We do not consider the basic x cell structure of the RDL approach as it would use more microrings (~6k 4 k ) for this case. The latency of RDL is (k+) τ res + τ sw + τ conv, where τ conv accounts for two O/E conversions, and τ sw for the switching time in both stages. This is obtained by considering the worst-case scenario where light passes through a maximum of k+ cross-state (on-resonant) switches at the product plane and k +k+ pass-state (offresonant) switches at the sum plane before producing a logic value on the output port. By assuming that the OLUT add-drop filters are also implemented using microrings (see Chapter 4), a direct comparison can be drawn between the latency and hardware resources used in the RDL and OLUT architectures for implementing the k-bit full adder, as summarized in Table.. We can see that in this full adder configuration, the OLUT uses much less lasers and photodetectors than RDL, and it has less latency than RDL because τ res is one of two orders of magnitude smaller than the other terms in the latency expressions. However, without using the cascading approach discussed above, OLUT uses fewer microrings than RDL only when k is less than 3, otherwise it requires much more than the latter, as illustrated in Fig.9. By contrast, if the OLUTs can be cascaded to realize the full adder, much fewer microrings would be required as compared with the RDL architecture. This shows the interest in exploring the OLUT architectures that can be readily cascaded, as this would increase the potential of OLUT architectures for computation. This topic will be discussed in chapter 6.

88 Chapter 3 OLUT Architecture Design and Implementation 49 7 Number of microrings OLUT : k + + RDL : 3( k OLUT RDL k + ( k + ) + k + )(3 k + ) k Fig.9. Total number of microrings required for implementing a k-bit full adder with the OLUT architecture (represented by red lines with square) and the RDL architecture (represented by blue lines with triangle) Therefore, we may conclude that OLUTs allow for lower latency and a reduced number of lasers and photodetectors, hence reducing the energy consumption in this full adder configuration when compared to RDL circuits. It also indicates the potential for further parallel computation through using a higher number of multiplexed wavelengths, which is possible by exploiting integrated silicon photonic technology. 3.3 n-m -OLUT Architecture In the last section, we proposed the OLUT architecture to perform parallel logic computations. Could we readily increase the degree of parallelism into the OLUT architecture to maximize its computational performance? Here, we propose a n-m -OLUT architecture to compute the logic function and its complementary logic output simultaneously. This section will present the architecture and discuss its operation principle OLUT with Complementary Logic Output Fig. shows a - -OLUT architecture example, with two inputs. The computation result of the OLUT is provided on output Z similarly to the electrical -LUT (see Fig.3 (a)). In addition, the - -OLUT provides a second output Z on which the complementary result

89 Chapter 3 OLUT Architecture Design and Implementation 5 of the operation is computed. The computing performance of the OLUT using the complementary output interface is thus increased compared to the OLUT architecture, with a minimum of additional hardware (no active add-drop filter, just some passive ones and some waveguide crossings in this simple case). As mentioned in section 3.., the computation in OLUT relies on an optical signal at wavelength λ, which is the equivalent of a power supply. Similarly to the n-m-olut, the OLUT with complementary interface uses the electrical form for input and output data. With respect to n-m-oluts, a complementary part is added as described as follows. Complementary part (Fig.): Similarly to the memorization part of the n-m-olut, the complementary part is composed of four add-drop filters (in the case n=, m=) at resonant wavelength λ that are interconnected by horizontal waveguides and redirect the optical signal to a vertical waveguide, thereby producing the complementary result of the targeted Boolean function stored in the SRAM of the memorization part, at the complementary output port. Note that in contrast with the devices in the memorization part, the add-drop filters contained in the complementary part are only passive. The same data coding of the results is used in the complementary part and the memory (i.e. brightness: logic and darkness: logic ). Input Data x y Output Data z z D D / λ λ λ x / λ λ λ λ x / λ λ λ x / λ λ Routing part Memorization part Complementary part Fig.. Illustration of a - -OLUT Architecture

90 Chapter 3 OLUT Architecture Design and Implementation 5 X Y Z Z Z Z 3 AND D OR D XOR D Buffer D λ λ λ λ 3 Z D Z D Z D Z D 3 NAND NOR XNOR NOT Y λ λ λ λ 3 λ λ λ λ3 λ x λ x λ λ λ λ λ λ 3 λ λ 3 λ λ λ λ λ λ 3 λ λ 3 λ x λ λ λ λ 3 λ λ λ λ 3 Routing part Memorization part Complementary part Fig OLUT architecture configured to execute 4 Boolean functions and their complements on four wavelengths. While the OLUT described in Fig. uses a single optical signal at wavelength λ to compute one pair of complementary functions, we can once again take advantage of WDM to realize multiple pairs of logic operations on the input data, thereby computing output data with m bits along with m complementary bits. Similarly to the n-m-olut, m optical signals at distinct and regularly spaced wavelengths (λ,..., λ m- ) are used, representing m pairs of complementary Boolean functions. The complementary part is composed of m stages (represented by m distinct columns), each of which is composed of n identical passive adddrop filters and interconnected by n horizontal waveguides. To illustrate the computation process of n-m-oluts with a complementary part, we take the exmple of the -4 -OLUT (Fig.) configured to simultaneously process logic operations AND/NAND, OR/NOR, XOR/XNOR, and BUFFER/Invert at four specific wavelengths, namely λ, λ, λ and λ 3 respectively. In Fig., the input values x= and y= imply that the optical signals are driven towards the uppermost waveguide in the routing part. The optical signal at wavelength λ is dropped towards output Z, since the SRAM controlling the state of the corresponding add-drop filter is configured with logic. In the same way, the signals at wavelength λ and λ 3 are dropped, thereby producing the result on output Z and Z 3 respectively. Since the SRAM controlling the add-drop filter associated with λ is configured to logic, the optical signal at λ continues propagating on the horizontal waveguide towards the complementary part. It will be dropped towards Z, thus producing the bit. We reiterate that the logic value is obtained when there is no light reaching an output. In this example, the result is thus obtained on outputs Z Z Z 3 and Z.

91 Chapter 3 OLUT Architecture Design and Implementation Filtering Scheme in the complementary part The n-m -OLUT adopts the same wavelength filtering scheme in the routing part and in the memory part as in the n-m-olut. However, the filtering scheme in the complementary part is realized by taking advantage of passive add-drop filters to select and drop optical signals without requiring any dynamical control. Fig. illustrates the operation of the passive add-drop filter in the complementary part. Similarly to the memorization part, their FSR is slightly larger than the spacing between the adjacent wavelengths of the incident optical signals, so that only one resonant wavelength is aligned with one injected optical signal wavelength. However, as passive add-drop filters are used, their resonant wavelengths are fixed by design and, ideally, do not need to be changed. a) b) Z 3 D DROP λ 3 FSR i3 λ 3 THROUGH λ λ λ λ 3 λ Fig.. Operations of passive add-drop filter in the -4 -OLUT: (a) Layout (b) Wavelength spectrum 3.4 Conclusions In this chapter, the concept and the architecture-level design of OLUTs for reconfigurable photonic computing are presented in a progressive way, as illustrated in Fig.3: First, we showed a basic OLUT block that is functionally equivalent to the electrical LUTs, but it makes use of light to transport information inside the LUT block. This basic idea is illustrated through the example of a --OLUT. Then, by taking advantage of WDM for parallel computation, we proposed the n-m- OLUT that can simultaneously perform multiple logic operations on the same input data, thereby allowing a reduced number of optical devices and potentially an increased energyand area- efficiency. Finally, we extended the n-m-olut architecture by adding the complementary logic output to the n-m x -OLUT architecture. This allows the OLUT architecture to process a pair of complementary logic functions with a reasonable hardware overhead, leading to the computation capacity increase by up to % with respect to the n-m-olut. The OLUT architecture and concept presented in this chapter could be physically implemented using a variety of approaches, which would certainly impact the performance of

92 Chapter 3 OLUT Architecture Design and Implementation 53 the resulting computing architecture. In the next chapter, we will propose one specific physical implementation for OLUTs, which might not be the optimal one but takes advantage of the mature silicon photonics technology. In this implementation, we will focus on the realization of electro-optic OLUTs, i.e. where the input and output data are kept in the electrical domain. We will discuss the modeling of the associated building block devices and whole structure of the OLUT, thereby highlighting the feasibility of the architecture presented here and preparing the groundwork for the performance evaluation presented in chapter 5. However, we should distinguish the limitations that might arise from the specific implementation choice (e.g. the speed limit at which the switches can be run, see chapter 4) with those linked with the OLUT architecture itself (e.g. the number of switching elements as presented in section 3..). Finally, the OLUT concept presented here is just a starting point. It could be refined and some weaknesses (for instance associated with the prospects of OLUT cascading) could be addressed in a more advanced version, which is the subject of chapter 6. Input Data Output Data x y z SRAM D / λ --OLUT λ λ λ / λ / λ λ / λ λ stage Routing Memorization X Y Z Z Z Z 3 AND D OR D XOR D Buffer D λ λ λ λ 3-4-OLUT λ λ λ λ3 λ x λ x λ λ λ λ λ λ 3 λ λ 3 λ x λ λ λ λ 3 Routing part Memorization part X Y Z Z Z Z 3 AND D OR D XOR D Buffer D λ λ λ λ 3 Z D Z D Z D Z D 3 NAND NOR XNOR NOT Y λ λ λ λ 3-4 -OLUT λ λ λ λ3 λ x λ x λ λ λ λ λ λ 3 λ λ 3 λ λ λ λ λ λ 3 λ λ 3 λ x λ λ λ λ 3 λ λ λ λ 3 Routing part Memorization part Complementary part Fig.3. Incremental presentation of OLUT architectures

93 Chapter 3 OLUT Architecture Design and Implementation 54

94 Chapter 4 From architecture to device: multi-level modelling and simulation 55 Chapter 4 FROM ARCHITECTURE TO DEVICE: MULTI- LEVEL MODELLING AND SIMULATION This chapter deals with the technological aspects required to practically implement the OLUT introduced in Chapter 3 and addresses the following questions: How can we properly design its constituent building blocks using a mature silicon photonics technology? How can we achieve the required system performance when these building blocks are integrated in OLUT architectures? A multi-level modeling approach including both the physical and system aspects is required for investigating the full potential and performance of OLUTs. At the physical level, we model the behavior of photonic devices using analytical tools such as Coupled Mode Theory [3] and commercial tools, such as RSoft FDTD and multiphysics utility software [7]. The device metrics (e.g. transmission, geometry) are then extracted to describe the system behavior of the resulting OLUT. This model also allows the estimation of the required optical laser power to ensure a certain level of performance for the OLUT system, e.g. a given BER at all outputs. This model will allow us to explore the design space of the silicon photonic devices for performing reliable and energy-efficient computation in OLUT architectures, as detailed in Chapter 5. The chapter is organized as follows. Section 4. provides an overview of the basic functional toolbox relying on silicon photonics technology for implementing OLUTs, such as micro-lasers, photodetectors, waveguides and add-drop filters. In section 4., we discuss in further detail the design of the electro-optic add-drop filters using optical modeling and electrical simulations. Additionally, different schemes for electrically controlling these adddrop filters are investigated. Section 4.3 focuses on system level aspects, in particular the impact of system-level parameters, i.e. the BER, and the OLUT dimensions, on the design of the devices that are needed to implement the system efficiently. We investigate the optical losses associated with the silicon photonic layout, and build the energy model for estimating the total energy consumption in the OLUT system.

95 Chapter 4 From architecture to device: multi-level modelling and simulation Functional toolbox based on silicon photonics for implementing OLUT The OLUT has the potential to make the most of silicon photonics through WDM, thereby allowing parallel computation. This requires wavelength selective optical components to route and filter different wavelength channels according to the control signal. The most compact way to implement such function is to use a resonator-based add-drop filter, for instance made of a microring resonator (Fig.4 a) [39,5]. In this chapter, we describe a physical implementation of the electro-optic OLUT that can be realized using a mature photonics technology. This implies an electrical bias voltage to be used as the control signal of the microring based add-drop filter. Electrically-controlled silicon microring resonators are commonly used in optical interconnects and optical computing architectures, since they combine the key characteristics for such applications, i.e. i) a ten-to-hundred µm-scale footprint ii) Gigabit/s data rate iii) picosecond transmission delay (latency), iv) low switching energy (e.g. ~fj/bit [7]), and v) large-scale integration for on-chip photonic applications. We adopt these devices as the essential switching elements for OLUTs. Alternatively, it is possible to implement these optical switching elements with twopath interference structures such as Mach-Zehnder interferometers, but their physical size might be too large to be integrated on a chip at a large scale, as compared with compact ring resonator based devices. In this section, we introduce all the optical building blocks of OLUTs, with a strong emphasis on the add-drop filter for which we first establish the transmission model in the passive regime. 4.. Passive Add-Drop Filters (Microring resonator) 4... Basic Principles Basically, the SOI-based add-drop filter that we choose to use in OLUTs is a silicon microring resonator side-coupled to two crossing waveguides. A schematic is shown in Fig.4 a) and the associated transmission response is displayed in Fig.4 (b). It exhibits a spectral comb of regularly spaced resonance peaks (each peak is typically a Lorentzian-shape function, and their spacing is related to Free Spectral Range (FSR)), and each of the resonance wavelengths could serve as a filtering channel for the data input (Fig.4 (b)) [53]. We next focus on one specific resonance wavelength and its closest signal wavelength. As presented before (see section 3.), the add-drop filter acts as an optical router or an optical switch

96 Chapter 4 From architecture to device: multi-level modelling and simulation 57 depending on the (de)tuning between its resonant wavelength with respect to the incoming signal wavelength. Note that passive add-drop filters can be directly used to implement the complementary part of the n-m x -OLUTs. As represented in Fig.4 (a), the signal arising from the input port IN is then redirected either on the OUT (DROP) or OUT (THROUGH) output port when the signal is in or out of resonance with the microring, respectively. We can thus define the associated transmission T and T as the ratio of the output powers at OUT and OUT to the input power at IN (see Fig.4 (a)). (a) OUT (DROP) S d Resonator λ x (x= m) OUT T = = IN S S d in τ i, a, τ c K OUT T = = IN S t in S IN (b) S in K IN S t OUT (THROUGH) (c) 6 x 5 Transmission FSR Q i 4 λ λ λ λ 3 λ Radius r (µm) Fig.4. (a) Representation of an add-drop filter based on microring resonator (b) Illustration of the transmission spectrum for an add-drop filter, including the signaling of resonant wavelengths and free spectral range(fsr) (c) Measured intrinsic quality factor, Q i, versus radius of the ring [Source from [38]] The key parameter that determines the add-drop filter characteristics, i.e. transmission values and losses, is the resonator dimensionless quality factor Q. The fundamental definition of Q is EnergyStored Q = ω averageenergyloss (4.) The Q factor is the ratio of the total energy stored into the cavity to its energy loss per unit time, at the resonant frequency ω of the cavity. It is thus essentially governed by the energy coupling efficiency between the cavity and the associated channels and the intrinsic power

97 Chapter 4 From architecture to device: multi-level modelling and simulation 58 loss within the cavity (associated with an intrinsic Q factor), which typically depends on the cavity geometry and roughness induced scattering for a given material platform and technology like silicon photonics [38][53]. Fig.4 (c) plots an estimation of the intrinsic quality factor (excluding coupling loss) as a function of the radius of the microring based on experimental data from [38]. Since a microring resonator has an additional surface that can induce more scattering loss than the microdisk resonator, the experimental values of intrinsic quality factor associated with a microdisk resonator extracted from [38] are divided by a factor of two for the ring resonator, to produce the estimated data of Fig.4 (c). This curve will be used in the performance evaluation of the next chapter to account for the experimental trend of decreasing losses for larger microrings. A high Q cavity allows for slower loss rate, thus achieving a stronger resonant effect. If τ represents the decay time of the electric field amplitude A(t) of an optical mode in the resonator (i.e. A (t) varies as t e τ ), Equation (4.) gives: Q = ωτ / (4.) In the transmission spectrums presented in Fig.4(b), the ratio between the resonant wavelength λ (transmission peak) and the Q factor (λ /Q) is the full spectral width at half maximum (FWHM)δλ, i.e. δλ = λ / Q. Hence, the resonant wavelength and the Q factor fully describe the add-drop filter response close to one resonance. In the following, we express the resonator transmission as a function of the Q-factor and the wavelength shift, using the Coupled Mode Theory (CMT [3]) in time Passive add-drop filter transmission and Coupled Mode Theory We now derive the add-drop filter transmissions as a function of the Q factor and wavelength detuning between the incoming signal and the microring resonance. For this, we directly use the set of equations describing the coupling of the cavity and the two waveguides according to the temporal Coupled Mode Theory (CMT). The derivation of these equations can be found in many references and books (see [3, 3][44] [45] [53]) and we will not fully detail them here. This factor is a rough estimation for the ring. It is optimistic if two horizontal surfaces of the ring are taken into account.

98 Chapter 4 From architecture to device: multi-level modelling and simulation 59 We consider an optical signal with an field amplitude S in injected into the input port IN and routed by a classical add-drop filter resonator. We note S d and S t the field amplitudes at the Drop port and Through port respectively (see Fig.4a). In order to use CMT to model the behavior of the add-drop filters, we use the following simplified assumptions: - The coupling between the waveguides and the cavity is weak, such that the cavity energy leaks slowly into the waveguide. Because of that, we can further assume that the cavity mode decays exponentially over a given lifetime τ. - The system is linear, and the conservation of energy applies. - The materials and geometries of the device do not change with time. - The waveguides are single mode and their dispersion is neglected. - The cavity is single mode in the spectral range of interest, and no signal is injected from the input port IN (see Fig.4a). The cavity mode amplitude is proportional to a variable denoted as a such that a is the energy stored in the cavity. In such a linear cavity, the optical field oscillates as j t e ω if the input optical signal has a frequency ω. From the CMT, the operation of the add-drop filter is governed by the following equations [3]: da dt = jω a = jω a + KS in (a) τ S t = S K a (b) in * (4.3) * S d = K a (c) where ω is the input optical signal frequency, ω is the cavity resonant frequency, K i are the coupling coefficients (see Fig.4 (a)). We assume that the spacing between the ring and both straight waveguides is the same and the K i may differ only by a de-phasing factor so that K = K = K. /τ represents the total decay rate in the cavity. The latter can be calculated through /τ =/τ i +/τ c +/τ c, wherein /τ i is related to the intrinsic losses in the cavity and /τ c represents the energy coupling rate between the cavity and either ones of the adjacent waveguides (assumed to be identical). By applying the energy conservation into the system, the coupling coefficient K of the single-direction propagating mode can be derived

99 Chapter 4 From architecture to device: multi-level modelling and simulation 6 as. The absolute squared value of this coupling coefficient (/τc ) is equal to the total rate τ c of power decay from the cavity into both adjacent waveguides. The optical power transmission at the Through port and the Drop port is defined as T = S t / S in and T = S d / S in. To solve for these transmission variables, we divide Equation (4.3)(b) and Equation (4.3) (c) by S in and then substitute a from Equation (4.3) (a). We obtain the transmissions in the stationary state: T T S = S S = S t in d in τ c = j( ω ω) + τ τc = j( ω ω) + τ (4.4) This then yields: T T S = S S = S t in d in ( ) τ τ τ c = ( ω ω) + τ 4 τ c = ( ω ω ) + τ (4.5) Equation (4.5) gives a Lorentzian shape for both transmission values with a maximum at ω=ω for the Drop port and a minimum value for the Through port, i.e. when the incoming signal is spectrally aligned with the microring resonance. Commonly, it is useful to write the above transmission equations using Q factors for describing the various loss contributions. Using the relation (4.) and converting the angular frequencies into wavelengths, we finally obtain: T T ( Q = = [ Q λ / λ] (Q / Q ) [ Q λ / λ] + L L L c L / Q ) c + (4.6) Where λ is the difference between the input wavelength and the closest resonance wavelength, Q L is the total quality factor of the ring cavity (Q L = ωτ/) and Q c is the coupling quality factor associated with the coupling rate into one waveguide (Q c = ωτ c / ). Q L can be

100 Chapter 4 From architecture to device: multi-level modelling and simulation 6 calculated through Q Q + Q, wherein Q i is the intrinsic quality factor limited by the L = c i scattering losses in the ring (Q i = ωτ i / ), which typically depends on the ring radius as illustrated in Fig.4 (c). From Equation (4.6), when the add-drop filter is in the Drop state (on-resonance state i.e. λ=), we can infer that the transmissions at the Through and the Drop ports are ( Q L / Q c ) T = and T = Q L / Q. If we assume the ring scattering loss is negligible ( c ) (Q i >>Q c ), it then follows that Q Q, resulting in the ideal and targeted values of L = c transmissions T = and T = for the Drop (on-resonance) state. In these conditions, without any other loss (e.g. free-space scattering or absorption), the transmission peak T can reach %. Additional loss contributions result in a decrease of Q i, thus degrading this transmission peak. A special case study: an optical signal is injected from port IN For completeness, we consider the case where the optical signal is injected from the input port IN of the microring add-drop filter, which occurs in a given column of the memorization stage of the n-m-olut for the signal arising from another add-drop filter in the Drop state. Indeed, the memorization stage is built such that all the add-drop filters of a given column have the same resonant wavelength (see Fig.4 in chapter 3). In this scenario, if the add-drop filter resonance λ x is aligned with the wavelength of the incoming light λ i, the optical signal will couple into the ring from IN and be redirected into the horizontal waveguide, thereby exiting from the OUT port. Fig.5 shows the result of an FDTD simulation describing this scenario. This situation should be avoided in the memorization part of the OLUT, since it would almost fully attenuate the signal coming from the downside, thereby generating a logic instead of a logic '' at the output of the associated photodetector. This issue can however be solved by using the layout represented in Fig.6. In this scheme, both an individual vertical waveguide and photodetector are assigned to each add-drop filter of one given column, and these add-drop filters are horizontally shifted with respect to one another instead of being vertically aligned. The vertical outputs of the add-drop filters of one given column are subsequently merged in the electrical domain to provide the intended Z logic value. In principle, this could be done without adding much optical loss apart from the contribution of the additional crossing points (considering that several design solutions exist for reducing the waveguide crossing losses) nor energy consumption since

101 Chapter 4 From architecture to device: multi-level modelling and simulation 6 only one of the photodectors associated with a given column is active (i.e. consumes some energy) at any time. For the performance analysis of the OLUT as carried out in chapter 5, we therefore chose to focus on the main contributions to the power consumption (given in particular by T and T deviating from the ideal and values) and neglected these additional losses that arise when considering a more accurate layout. These should however be included for a refined analysis of the OLUT power consumption. For the sake of clarity in the illustration of the OLUT however, we continue to use the same simplified schematic for the layout of the memorization part (and complementary part for the n-m x -OLUT) as introduced in chapter 3. An alternative solution to this problem is to reorganize the memorization part of the OLUT architecture so that one given column is not associated with the add-drop filters resonating at the same wavelength λ i. This layout is further detailed in the Appendix (including an evalution of the energy consumption) because it represents an elegant alternative that avoids the duplication of photodectectors and vertical waveguides as in Fig. 6. However, we note that although it can be adopted for any OLUT dimension, it is best suited for a square matrix of add-drop filters in the memorization part (i.e. n =m). OUT λ i =λ x DROP IN OUT λ i IN λi Fig.5. Illustration of the propagation of the optical signal injected from IN (left) and the FDTD simulation result (right). The optical signal routing direction is highlighted by red arrows.

102 Chapter 4 From architecture to device: multi-level modelling and simulation 63 Z D D D D λ λ λ λ X Y Z Z Z Z 3 AND D OR D XOR D Buffer D λ λ λ λ 3 λ λ λ λ3 λ x λ x λ λ λ λ λ λ 3 λ λ 3 λ x λ λ λ λ 3 Routing part Memorization part Fig.6. A more accurate memorization layout for OLUT architectures. As illustrated by the inset, the add-drop filters are horizontally shifted with respect to one another instead of being vertically aligned. The vertical outputs of the add-drop filters of one given column are subsequently merged in the electrical domain to provide the intended Z logic value To summarize, we have reminded here the transmission expressions associated with microring based add-drop filters in the passive regime using the CMT. In the section 4..4, we will generalize these equations to the case of active (electrically controlled) add-drop filters, which are adopted as the active switching/routing elements in the OLUT architecture. Before this though, we present the other key optical components for OLUT architectures in the next section. 4.. Silicon waveguides, integrated photodetectors and micro-lasers As with any other silicon photonic system, OLUTs make use of optical waveguides to interconnect the different components on the chip, i.e. the lasers, the modulators and the photodetectors. Silicon photonic waveguides that are typically fabricated on SOI substrates exhibit a top silicon layer with a thickness ranging between nm and 3nm to ensure monomode operation. The waveguide structure is generally patterned using e-beam

103 Chapter 4 From architecture to device: multi-level modelling and simulation 64 lithography or DUV lithography. In recent years, the SOI waveguide propagation losses have been greatly reduced to the range of.- db/cm (for a rectangular geometry with a crosssection of 45xnm [73,74][44][46][48]). However, a large number of waveguide crossings or bends still introduce relatively high signal losses (e.g..db per crossings [4]). Photodetectors are needed for converting the optical signal to the electrical domain at the end of each output port in the OLUT. These devices are required to work at high speed (~GHz) and with low noise to enable highly reliable computation (e.g. Bit Error Rate BER< -8 ). In addition, the device footprint and energy consumption are important metrics to satisfy system requirements. While silicon is transparent for near infrared wavelength, a Germanium layer can be integrated on the silicon platform to increase the absorption of photons and hence achieve a high detector responsivity of the order of A/W at 55nm (with relatively low dark current (a few na)) [48][37]. Basically, two types of structures can be used to implement the photodetector, i.e. P-I-N junction and M-S-M junctions (see Fig.7). MSM junctions are easy to fabricate and require only one lithography step to form the metal contacts. However, they suffer from much lower external quantum efficiency as compared with PIN diodes, and the latter commonly operates at a higher speed than the MSM junctions. Waveguide integrated Ge photodetectors on SOI platforms have been recently demonstrated [5,7,7]. As compared with photodetectors operating under surface illumination, these devices have no trade-off between device speed and responsivity. Hence OLUT systems would take a high advantage by using these waveguide integrated photodetectors relying on PIN junctions. (a) (b) Fig.7. Ge Photodetector integrated on SOI waveguide a) PIN[7] b) MSM [5] Regarding the light sources, OLUT architectures do not impose stringent requirements. Since the laser serves as a continuous-wave power supply, it does not necessarily have to be integrated on chip with a small volume and very high speed. Off-chip external III-V laser

104 Chapter 4 From architecture to device: multi-level modelling and simulation 65 diodes that deliver sufficient output optical power (which will be clarified in the section ) and well-controlled emitting wavelength are well-suited for OLUTs. 4. Design of active add-drop filters for OLUT architectures We next introduce and discuss our choice to implement the electro-optic add-drop filters that represent the main active components for the OLUT architecture proposed in section Electrically-controlled modulation of an optical signal By applying an external electrical signal (voltage) onto a dielectric material such as silicon, the amplitude and the phase of an optical signal can be modulated. More specifically, the optical signal that propagates into a silicon waveguide can be modulated by changing the refractive index of silicon, i.e. its real part or its imaginary part. The imaginary part of the refractive index can be changed through the electro-absorption effect, but this affects the intensity of the light that goes through by introducing additional optical losses, so that it is not energy conservative. In contrast, the modulation of the real part of the refractive index directly impacts the phase of the incident light, and together with an appropriate structure (such as a microring resonator or a Mach-Zehnder interferometer), it can be turned into a wavelength selective approach for modulating the intensity of the optical signal. Practically, three possible ways can be used to tune the real part of the refractive index: the thermo-optic effect, the electro-optic effect and the free-carrier induced electro-refractive effect. As summarized in Tab, these effects have different modulation strengths and time response: the electro-optic effect is the fastest effect but it has a limited tuning range; the thermo-optic effect is the strongest but is very slow; the response time and the modulation strength of the electro-refractive effect are in between. In the OLUT architecture, the add-drop filters in the memorization part and the routing part have different constraints: the first ones could use the thermo-optic effect since we do not need them to be fast, while the second ones could make use of the electro-refractive effect because of the required high operation speed. We next briefly introduce the electro-optic mechanism and then present the other two mechanisms in further detail as these are considered for the OLUT implementation. Tab. Different mechanisms for electrically-controlled optical modulation with typical values for tuning range, response time, power efficiency and energy consumption

105 Chapter 4 From architecture to device: multi-level modelling and simulation 66 Thermo-optic effect Electro-optic effect Electrorefractive effect Typical tuning range Typical response time ~ nm ~.nm[68] ~ nm ~µs ~ ps ~ns Typical power efficiency Typical energy consumption mw/nm [67] 3.5mW/nm [54] ~ pj/bit [67] ~ pj/bit [54] N/A mw/nm [37] N/A 85fJ/bit [37] 3fJ/bit [65] 4... Electro-optic effect The optical properties of several dielectric materials can be changed by applying an electric field (either a voltage or an optical signal). Common electro-optic effects used in semiconductor materials include the Pockels effect and the Kerr effect. However, due to the central-symmetric lattice, crystalline silicon does not exhibit the Pockels effect unless the symmetry of the lattice is broken [5]. The electro-optic Kerr effect in silicon can be very fast, since it involves a near instantaneous response of the bound electrons in the material, but is much weaker than the other ones in Si Thermo-optic effect The thermo-optic effect causes a wavelength red-shift upon increasing temperature due to an associated rise of the refractive index. Considering the temperature sensitivity of the 4 refractive index in silicon that is given by dn / dt =.8 K at room temperature, a change of refractive index of. can be achieved by increasing the device temperature by 6 C. The reverse direction i.e. cooling effect is also possible but is even slower. The thermo-optic effect is one of the commonly applied approaches for providing static control of the resonant wavelength in the microring based add-drop filters. It can shift the wavelength spectrum by up to more than nanometers, depending on the geometry of the microring resonator. For example, a thermal tuning range of more than nm with a heating efficiency of 8µW/GHz has been demonstrated in silicon microring resonators with a radius of 7µm (6nm FSR) [54]

106 Chapter 4 From architecture to device: multi-level modelling and simulation 67 (Fig.8). The thermo-optic effect can be obtained by simply applying an electric current to a micro-heater integrated onto or inside the device region. As illustrated in Fig.9, it can be realized by putting metallic resistors on top of the device claddings [46], or by heating the silicon device through doped/silicided resistors [47], or by directly integrating the heater inside the core of a silicon waveguide [48]. In OLUTs, the thermo-optic effect is typically needed to align the initial resonances of the ring resonators with respect to the incoming signal wavelengths in a step referred to as a pre-calibration. This would compensate for the fabrication inaccuracy of the microring, and stabilize the initial OLUT configuration (i.e. configure the state of the add-drop filters in the memorization part when the RAM value is applied). Some approaches are possible to reduce the temperature drift, e.g. incorporating the cladding material with a temperature dependency that is opposite to silicon [5]. However, they are not CMOS compatible at the current stage. It is also possible to improve the temperature stabilization through the use of higher order rings (i.e. cascading multiple rings), but the device complexity, footprint and power consumption will be disadvantageously increased [64]. Fig.8. Microring resonator with integrated heater structure [54] Metal resistor Heating current Top oxide cladding Silicon wire Silicon waveguide Buried oxide Silicon substrate Waveguide core