MAC based FIR Filter: A novel approach for Low-Power Real-Time De-noising of ECG signals

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1 MAC based FIR Filter: A novel approach for Low-Power Real-Time De-noising of ECG signals Ramandeep Kaur, Rahul Malhotra, Sujay Deb Department of Electronics and Communication Engineering, IIIT Delhi, India [ ramandeep13136, rahul13135, sdeb]@iiitd.ac.in Abstract Wearable real-time Electrocardiogram (ECG) monitoring is an emerging wireless technology enabling early diagnosis and increased ability of prevention of cardiovascular diseases. However, the ECG signal suffers from Powerline Interference (PLI) which corrupts the biomedical recordings. Low power and high speed filtering of the ECG signal is essential to make the monitoring device portable. This paper proposes an FIR (Finite Impulse Response) filter based on Multiply-Accumulator (MAC) Unit to suppress the PLI noise. The performance of this filter largely depends on the speed and power of the MAC unit employed inside the filter. The current work compares various MAC units on Power, Performance and Area (PPA) benchmarks. It is shown that Booth-Wallace-Carry Look adder(cla) based MAC is optimised for both timing and power which shows 6.2% improvement in performance and 12.1% reduction in power from other implemented designs. Thus, the real-time low power FIR filter is realised using Booth-Wallace-CLA MAC. The convergence time of the algorithm is observed to be less than 0.2 µsec with significant power savings to improve battery life. which is a low frequency noise, PLI, electromyogram (EMG) which is caused because of muscle motion during recording. From all these noises, Powerline interference is the most common type of noise in the ECG signal[1]. The human body acts like an antenna for 50Hz signals, by absorbing electromagnetic (EM) radiation of the same frequency from the powerlines. This is because the average height of a person is almost comparable to the wavelength of the ECG signal. Various other causes of powerline noise are stray effects of the alternating current fields due to loops in the cables, improper grounding of ECG instrument or the patient, disconnected electrodes, electrical equipment s such as air conditioner and -ray machines draw heavy power line current, which induces 50 Hz signals in the input of the machine. Keywords ECG, PLI, FIR, Wallace, Booth I. INTRODUCTION Biomedical signal processing is widely used to medically diagnose various parts of the body where ECG signal analysis is the most widely used technique for getting information on cardiac health and pathology. Through enabling continuous remote cardiac monitoring one can improve the quality of care and achieve enhanced patient autonomy and mobility for older patients. The ECG signal gives a composite snapshot of the electrical and mechanical performance of heart vs time from several different projections or directions (different electrodes are placed on different parts of the body). ECG signal works by detecting and amplifying the tiny electrical changes on skin caused by heart muscle depolarisation during each heart beat. ECG signal of a normal heart beat consists of a three parts P wave, QRS complex and T wave as shown in figure 1. However, the ECG signals get distorted due to various noise sources and the extraction of information gets negatively influenced and maybe interpreted wrongly. Proper acquisition of weak signals in diverse noisy environment is one of the biggest challenges while developing an ECG filter. Interferences in ECG signals may have a technical source like power supply, or a biological source, like muscle movement while recording. The different kinds of noises in ECG signals include Baseline wander (BLW) Fig. 1: A typical ECG signal Several techniques have been proposed in literature to tackle the problem of energy-efficiency in wearable ECG sensors and monitors. However, most of them focus on the ECG compression using compressed sensing signal acquisition[2] to reduce the airtime over energy-hungry wireless links. This paper pivots around the fact that the ECG signal de-noising filter for proper interpretation of the cardiac information should be high speed and energyefficient in addition to the embedded compressed sensing which will further improve the battery life and give a better performance. Removal of the power line interference, base line wander and high frequency noise has been illustrated[3], by applying digital Infinite Impulse Response (IIR) filter on the raw ECG signal. The response of the IIR filter is not linear thus, phase distortion can occur. This paper employs a fixed Window, Linear phase FIR filter for the design which produces no distortion due to time delay of frequencies relative to each other. Additionally, in FIR filters, the effects of quantisation error and roundoff noise are much less important and easier to analyse than in IIR filters since the errors are not fed back into /15/$ IEEE

2 the filter. Another approach of filter design[4] made use of a multiplication free FIR filter using Recursive Running Sum (RRS) Algorithm. This algorithm has the advantage of being fast however, the number of additions are increased many a fold and therefore more hardware is required which further leads to large area and power consumption. Adaptive filtering is used in [5] reduces noise more effectively, however the convergence time is larger and has higher complexity. Recent research[6] proposed a State Space Recursive Least Square (SSRLS) filter based method for the removal of 50Hz PLI noise from the ECG signal. This algorithm shows superior performance as compared to Notch filter but is exceedingly complex and requires initialisation. This initialisation ingests additional time and power for implementation. This paper proposes an FIR filter design which is linear, low-power, high-speed, easy to implement and requires less hardware to overcome the limitations discussed in the previous section. The remaining paper is organised as follows: Section II explains the MAC based FIR filter design and discusses the implementation of MAC using Radix-4 Modified Booth Algorithm followed by Wallace Tree Reduction and CLA in the final addition stage. Section III presents the experimental results, analysis and comparison of various MAC implementations for filter design. Finally, the Section IV concludes the paper. k[n] Input D D D D: Delay 1 cycle n 2 n Fig. 2: FIR Filter Design y[n] = Scale l y[n] Output N.k[n i ] (1) i=0 To suppress the 50Hz interference in ECG signal, a band-stop filter is designed whose coefficients are obtained from the MATLAB function of FIR filter. The normalised frequency response of the designed stop-band filter is shown in figure 3. This filter is designed using the Hamming window which is a fixed window thus, only one independent parameter, window length is required which controls the main-lobe width. Also, the Hamming window is comparatively stable and has less ripples in pass band in comparison to Rectangular and Hanning window[7] and thus, is the preferred window for analysis. The Hamming window function is given by equation 2. II. PROPOSED FILTER DESIGN A. FIR Filter FIR filter is a digital filter i.e. it operates on discrete time signals which have several advantages over analog filters. They are more accurate, highly immune to noise, easy to implement and inexpensive to change the operating characteristics like cutoff frequency etc. Also, their performance is not a function of component ageing, temperature variation, and power supply voltage. These characteristics are significant in medical applications where most signals have low frequencies that might get distorted due to the drift in the analog circuit. FIR filter output is computed non-recursively as a weighted, finite term sum, of past and present values of the input. Finite impulse response implies that the effect of transients on the filter output will eventually subside. The impulse response is equal to the tap weights, thus, the filter has a difference equation given by equation 1. As shown in figure 2, tap-summer pair at each stage is implemented with a MAC unit. For each delay block, MAC is reused where the accumulator stores the previous sum and the present tap-summer pair generates the cumulative result in the accumulator. Thus, a 100th order filter can be realised using a single MAC Unit in time-division multiplexed form making it an area efficient design. The tap weights are scaled to integer values by multiplying all weights with power of 2 at the input. The output is shifted right to compensate for the input scaling. Fig. 3: Normalised Frequency Response of Band-Stop FIR Filter w(n) = cos( 2πn N 1 ) (2) The MAC unit design is significant for FIR filter design because it is used at every tap-summer stage and forms the core of the filter. Thus, if we are able to make a high-speed MAC unit, an efficient FIR filter can be autonomically designed which is high speed and expends less power. B. MAC Unit Design MAC stands for Multiply-Accumulator Unit which suggests that there is a multiplication operation at every clock edge and the result in the Accumulator register is updated in the next clock edge as shown in figure 5. The figure depicts that (A) and Multiplicand (B) of 16 bits each have to be kept stable for a specific time before and after the clock edge which is the setup and hold time of the system. The basic architecture of a MAC is shown

3 in figure 4. The inputs ( and Multiplicand) are of 16 bits each. The output is 32 bits after the Wallace Tree Reduction stage. This output is then given as the input to the final stage adder which generates a 33 bit result.the multiplier in the figure 4 limits the speed of the MAC unit. To design a high speed multiplier in MAC unit there can be 3 approaches: Reduction in the number of partial products. Acceleration in the formation of partial products. Acceleration in the addition of the partial products. Modified Booth Encoder R31 Two s Complement Generator Partial Product Generator Wallace Tree CLA Adder multiplicand multiplicand R0 Accumulator Fig. 4: Basic Architecture of MAC Unit The proposed MAC takes into consideration all the 3 ways to increase the performance and at the same time, maintain low power. The number of partial products are reduced to half by using Radix-4 Modified Booth Algorithm in comparison to Array and Vedic multiplier. Acceleration in the reduction of partial products is done using Wallace Tree Reduction method. The final stage of MAC is addition which is done by using Serial Adder or Ripple Carry Adder (RCA) and CLA adder. The next section discusses all the mentioned algorithms in detail. 1) Stage: The in the MAC unit can be built using Array s which use simple hardware but the time required is more because the number of partial products equals the number of bits of the multiplier. Vedic can also be used which uses the Urdhva-triyagbhyam Sutra[8] which is a simplistic algorithm but requires more hardware thus, more area. Using Radix-4 modified Booth s multiplier, the number of partial products are reduced to n/2 if we are multiplying two n bits numbers, if n is even number, or (n+1)/2, if n is an odd number. By reducing the number of partial products, we can effectively speed up the multiplier by a factor roughly equal to 2. The Booth Encoding scheme for Radix-4 Algorithm is shown in Table I. Select Line (Encoding) Partial Products (Operation) 000 Add Add Multiplicand 010 Add Multiplicand 011 Add 2*Multiplicand 100 Subtract 2*Multiplicand 101 Subtract Multiplicand 110 Subtract Multiplicand 111 Subtract 0 TABLE I: Truth Table for Radix-4 Modified Booth Algorithm 2) Partial Products Reduction stage: Wallace tree reduction[9] is used to arrange the partial products in a tree structure to reduce the number of computations by the use of full adders and half adders. However, in the reduction phase half adders do not reduce the number of partial product bits. Full adders are used in each column where there are three bits whereas half adders are used in each column where there are only two bits. Any single bit in a column is passed to the next stage in the same column without processing. This reduction procedure is repeated in each successive stage until only two rows remain. Thus, Wallace tree is used to produce two rows of partial products that can be added in the last stage. Figure 6 shows the algorithm to reduce 8 partial products to 2 rows in the final stage. Matrix of Partial Products T c ycle CLK A B Multiplicand Multiplicand ACC Previous Output Valid O/P t a Fig. 5: A single cycle waveform of proposed MAC Unit Carry Propogate Adder (Final Stage) Fig. 6: Wallace Tree Reduction for a 16*16 Booth 3) Final Adder Stage: The CLA adder[10] improves the summing speed by reducing the amount of time required

4 to determine the carry bits. It calculates one or more carry bits before the sum by using the concept of generating and propagating carries. The carry propagator transfers the carry to the next level whereas the carry generator generates the output carry, regardless of input carry bit. The propagating and generating carries are given by equation 3. A prefix graph for carry computation in a 32-bit CLA adder used in our design is depicted in figure 7. Alternatively, a Serial or a Ripple carry adder can also be used, however it is inherently slower. P i = A i B i G i = A i.b i S i = P i C i C i+1 = G i + P i.c i Fig. 7: Prefix Graph for 32 bit adder Although, this paper focuses solely on suppressing the Powerline Interference, it can be extended to eliminate the effect of other mentioned noises in section I (ex. Baseline Wandering). The precision of the FIR filter designed can be improved further by increasing the number of taps in the filter. In addition, if a higher bit MAC is used, it will improve the quality of the ECG signal to a greater extent by reducing the quantisation noise, however the area would significantly increase. III. EPERIMENTAL RESULTS A high-performance MAC Unit is essential to design a linear FIR filter. In this section, we present the comparison of different multiplier types such as Booth-Wallace, Vedic and Array s along with Wallace Tree, RCA and CLA adders for the final stage addition in the accumulator. Table II shows the comparative analysis of the various implemented designs according to power, performance and area benchmarks. Performance is measured in terms of Critical Path Timing which is the time taken for the 1 st multiplier bit to multiply and store the result in the last Accumulator bit. The power comparison includes the sum of static and dynamic power calculated using the maximum transition bits. Overall, any implementation which includes the CLA adder is superior in performance than the Wallace Tree adder by approximately 18.6% because the former adder does not wait for the carry to be propagated from the previous stage. By contrast, the RCA is the slowest adder which shows 25% average degradation in performance as compared to CLA. Although the Vedic multiplier (3) Type Modified Booth Vedic(Urdhva Triyakbhyam Sutra) Array Adder Type Critical Path Timing Total Area Total Power [nsec] [µm 2 ] [µw/mhz] Wallace Tree Serial Adder Carry Look Carry Look Serial Adder Carry Look Serial Adder TABLE II: Comparative analysis of different MAC Units uses a simplified algorithm for high-speed multiplication, it consumes largest area and power, out of all implemented designs. It is a well-known fact that timing and area are conflicting constraints which can be clearly seen from the results. Booth-Wallace MAC occupies less area and is one of the slowest MAC units with high power expenditure. For low power and not so timing critical applications, Array can be used. It can also be inferred that Booth- Wallace-CLA MAC is the fastest MAC unit with 6.2% boost in performance and requires 12.1% less power than Vedic-CLA MAC. Consequently, as the order of the filter is increased to achieve higher precision, the savings in power would be more significant. Hence, the fastest low-power Booth- Wallace-CLA MAC, is used to design the Digital FIR filter. A noise-free ECG signal is generated in MATLAB[11] with a sampling frequency of 1000Hz and bandwidth of 100 Hz. This ECG signal is normalised for a peak-to-peak value of 1. A 50Hz sinusoidal noise is generated (figure 9) with a sampling frequency of 1000Hz and added to the ECG signal (figure 8). The noise-affected ECG signal is then applied to the filter input. The Signal-to-Noise ratio of the noiseaffected ECG signal is 10.08dB. It was observed that almost all of the 50Hz noise is suppressed at the output of the filter as depicted in figure 10 and this signal can be reliably used for diagnosis. The MAC unit design was simulated using Cadence NCSim simulator and synthesised on Synopsys Design compiler and Primetime-P was used for power analysis. All the results of timing, power and area of MAC unit are computed using 28nm UTBB-FDSOI (Ultra Thin Body and Box Fully Depleted Silicon on Insulator) technology. The Filter has been designed in Verilog HDL and ilinx ISE is integrated with MATLAB to apply the ECG signal to the filter and view the output. The convergence time for the algorithm was calculated using a Linux platform with x86, 64 bits working on 2.8GHz. IV. CONCLUSION Low-power and high speed filtering is required for wearable real-time monitoring of the ECG signal. To design the filter, low-power and high performance MAC unit is

5 Fig. 8: ECG Signal with Noise Fig. 9: ECG Amplitude vs Frequency Fig. 10: Filtered ECG Signal essential which has been discussed in this paper. The performance of the developed MAC has been analysed and compared with other implemented MAC Units on power, timing and area benchmarks. Booth-Wallace-CLA MAC confirms 6.2% improvement in performance and 12.1% less power consumption than Vedic-CLA MAC. Hence, Booth- Wallace-CLA is the preferred MAC to use in portable ECG processing applications. The FIR filter designed uses Time Division Multiplexed MAC and thus, the area of the processing unit is also minimised. Digital filter with Hamming Window is the favoured technique for filtering because it is linear, high speed and easy to implement. The total convergence time of the algorithm is µsec. Thus, this high speed-low power-high density filter design can be used in portable or wearable ECG monitors. REFERENCES [1] J. C. Huhta and J. G. Webster, 60-Hz interference in electrocardiography, Biomedical Engineering, IEEE Transactions on, no. 2, pp , [2] H. Mamaghanian, N. Khaled, D. Atienza, and P. Vandergheynst, Compressed sensing for real-time energyefficient ECG compression on wireless body sensor nodes, Biomedical Engineering, IEEE Transactions on, vol. 58, no. 9, pp , [3] M. S. Chavan, R. Agarwala, and M. Uplane, Design and implementation of digital FIR equiripple notch filter on ECG signal for removal of power line interference, WSEAS transactions on signal processing, vol. 4, no. 4, pp , [4] Y. Lian and P. C. Ho, ECG noise reduction using multiplier-free FIR digital filters, in Signal Processing, Proceedings. ICSP th International Conference on, vol. 3, pp , IEEE, [5] J. Gao, H. Sultan, J. Hu, and W.-W. Tung, Denoising nonlinear time series by adaptive filtering and wavelet shrinkage: a comparison, Signal Processing Letters, IEEE, vol. 17, no. 3, pp , [6] Y.-D. Lin and Y. H. Hu, Power-line interference detection and suppression in ECG signal processing, Biomedical Engineering, IEEE Transactions on, vol. 55, no. 1, pp , [7] H. Rakshit and M. A. Ullah, A comparative study on window functions for designing efficient FIR filter, in Strategic Technology (IFOST), th International Forum on, pp , IEEE, [8] Y. B. Prasad, G. Chokkakula, P. S. Reddy, and N. Samhitha, Design of low power and high speed modified carry select adder for 16 bit Vedic, in Information Communication and Embedded Systems (ICICES), 2014 International Conference on, pp. 1 6, IEEE, [9] C. S. Wallace, A suggestion for a fast multiplier, Electronic Computers, IEEE Transactions on, no. 1, pp , [10] M. W. Ernest, Critical ALU Path Optimization and Implementation in a BiCMOS Process for Gigahertz Range Processors. PhD thesis, Rensselaer Polytechnic Institute, [11] A. L. Goldberger, L. A. Amaral, L. Glass, J. M. Hausdorff, P. C. Ivanov, R. G. Mark, J. E. Mietus, G. B. Moody, C.- K. Peng, and H. E. Stanley, Physiobank, physiotoolkit, and physionet components of a new research resource for complex physiologic signals, Circulation, vol. 101, no. 23, pp. e215 e220, V. ACKNOWLEDGEMENTS This work is partially supported by the DST INSPIRE Faculty Fellowship granted by the Department of Science and Technology, Government of India.