Marx dc dc converter for high-power application

Transcription

1 Published in IET Power Electronics Received on 10th January 2013 Revised on 30th April 2013 Accepted on 22nd May 2013 Marx dc dc converter for high-power application Etienne Veilleux 1, Boon-Teck Ooi 1, Peter W. Lehn 2 1 Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Canada H3A 2A7 2 Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada M5S 3G4 etienne.veilleux@ieee.org ISSN Abstract: This study presents a dc dc converter based on the Marx generator principle of charging capacitors in parallel followed by reconnection in series for discharging and for creating higher voltage. The topology uses solid-state switches like IGBTs as well as diodes. The concept and the operation of converter are described as well as design steps. The validity of the design is confirmed using PSCAD/EMTDC software package. The topology is compared with the conventional boost where the Marx dc dc converter is shown to be competitive and even advantageous for higher dc gain. A cascade configuration is also presented and a 5 kw prototype with two stages made of two capacitors per stage is presented for experimental validation of the concept. 1 Introduction One of the first high-voltage dc dc converter topology is the Marx generator invented by Marx [1] in The concept of the Marx generator consists of charging capacitors in parallel followed by a reconnection in series for creating higher output voltage. The classical Marx generator uses spark gaps to connect capacitors in series and to create a single high-voltage pulse. Adaptations of the original topology have been made for insulation testing of high-voltage equipment [2] and X-ray generation [3]. Nowadays with solid-states switches, modern topologies based on the same principle have been presented for many applications such as electromagnetic radiation [4] and research laboratory [5]. However, most of the topologies presented are pulse generation type of converter and they are not suitable for continuous high-power application. The research of this paper is oriented towards applications where heavy ac transformer should be avoid but dc voltage step-up is still required to bridge the low voltage to high voltage such as for high-voltage dc grid [6]. This paper revisits the Marx generator concept to be suitable for continuous current operation. Modern Marx generators using solid-state devices have been studied [7, 8]. Their applications are for very sharp pulse at high voltage and not for continuous operation as intended in this paper. The principle of using switched-capacitor has been presented for step-down purposes [9], but this paper studies a similar approach but for stepping-up the voltage. For step-up application, switched-capacitor converters have been suggested for low and medium power application [10 12]. In addition, switch-capacitor converter has been shown to be superior to conventional boost converter at high-voltage gain [13]. Multilevel modular switched-capacitor converters has also been introduced for a general range of application [14 16]. The latter topology uses stray inductance of the circuit which makes it a less attractive solution for high-voltage high-power application. In this paper, the concept of cascading stages is also considered to reach higher dc voltage gain [17]. The concept and the operation of the Marx dc dc converter are described in Section 2. The design of the converter is done in Section 3 and simulation results are shown in Section 4 for simulation proofs of concept. In addition, Section 5 compares the topology with the conventional boost for competitive evaluation. The cascade configuration is described in Section 6. Laboratory test results are obtained from a 5 kw prototype with two stages and it is shown in Section 7. A discussion on method for obtaining variable gain is done in Section 8. Finally, the conclusion is in Section 9. 2 Marx dc dc converter operation The operation of the converter is based on the principle of charging capacitors in parallel for a period and, in a subsequent period, to connect the capacitors in series to create a higher voltage. The two periods are chosen to operate with equal durations, T S /2, where T S is the periodicity of the switching frequency F S. The capacitors and inductors are selected such that the L C resonance frequency matches the switching frequency. The explanation of the converter is done with M capacitors in the middle stage as illustrated in Fig. 1. The theoretical dc voltage gain of this example is M. The input stage is composed of a voltage source and an input IGBT switch (S IN ). The middle stage is composed of one entry diode (D 1 ), sets of two IGBTs (S A /S AA ) and middle diodes (D A ). An inductor (L 1 ) is connected in series with the entry diode (D 1 ) and there are M capacitors (C 1 ) in the middle stage. The output stage has a diode (D OUT ) in series with an 1733

2 Fig. 1 Marx dc dc converter topology for a dc amplification of M inductor (L OUT ) but it has only one output capacitor (C OUT ). The load, modelled by a resistor R load, is connected to the output capacitor. The first state is identified by the logic state D and IGBTs S IN and S A are activated so that the capacitors C 1 are connected in parallel as shown in Fig. 2a. The second state configuration is identified by logic state D and IGBT S AA is activated. By doing so, the capacitors C 1 are connected in series to create a voltage of magnitude MV S as shown in Fig. 2b. The steady-state waveforms of the inductor currents and the capacitor voltages are shown in Figs. 3a and b, respectively. The current equation of inductor L 1 for (t 0 t t 1 ) is given as i L1 = 0.5C eq v S DV C1 sin v S t (1) where C eq is the equivalent capacitance formed by the parallel connected capacitors C 1. The voltage equation of capacitor C 1 for (t 0 t t 2 )isgivenas V C1 = V S 0.5DV C1 cos v S t (2) where ΔV C1 is the peak-to-peak voltage ripple and ω S is the resonance frequency as it is defined and discussed in Section 3. The operation in state configuration D, shown in Fig. 2a, the waveforms of the inductor currents and the capacitor voltages are shown from t 0 to t 1 in Figs. 3a and b, respectively. The converter is in this state configuration for duration of T S /2 and the M capacitors of the middle stage, C 1, are obtaining charged. To do so, switches S IN and S A are turned on, which forward biases diodes D 1 and D A. Charge transfer takes place during the first half cycle of the L C resonance. Fig. 3a shows the current in inductor L 1, i L1, conducting during state configuration D. The parameters are selected such that the resonance half-period terminates before t 1.Assoonasthe current reaches zero, diode D 1 stops conducting and blocks. This soft switching accounts for the negligible switching Fig. 3 Waveforms of Marx dc dc converter with M capacitors in middle stage a Inductor currents b Capacitor voltages loss of the method. From Fig. 4b, the capacitor voltage of C 1 is shown to increase. As shown in Fig. 2a, the output stage is isolated and the storage charge in C OUT feeds the resistive load. The voltage V OUT of the output capacitor is simply decreasing based on the R C time constant of the load and the output capacitor. In the second state configuration D, shown in Fig. 2b, the waveforms of the inductor currents and the capacitor voltages are shown from t 1 to t 2 in Figs. 3a and b, respectively. The duration of the state configuration D is the same as state configuration D, being T S /2. The capacitors C 1 are connected in series and they are discharging into the output stage. To do so, switch S AA is turned on which forward biases diode D OUT. Again, the parameters are selected such that the resonance half-period period terminates before at t 2. The diode D OUT stops conducting as soon as the current reaches zero. The waveform of the output inductor current, i LOUT, is shown in Fig. 3a. The voltage V OUT of the output capacitor voltage increases while V C1, of the series-connected capacitors C 1, are discharging as shown in Fig. 3b. The operation of the converter consists of repeating this sequence, charging/discharging, to transfer charge from the input to the output capacitor. The higher voltage is created by connected the capacitor in series while the charging occurs at input voltage level. Fig. 2 State configurations of Marx dc dc converter with conducting switches displayed a Charging of C 1 in parallel with logic state D b Discharging of C 1 in series with logic state Ō 1734

3 By combining (4) (5) (6) is rewritten as Q load = P rated MV S T s (7) Fig. 4 Output voltage waveform for the charging (D) between t 1 and t 2, the dead-time between t 2 and t 3, followed by discharge ( D) between t 3 and t 4 3 Converter design This section goes through the design steps of a converter with M capacitors as shown in Fig. 1. The analysis assumes the converter is in steady state. The switching period is T S (=1/F S ) and each sub-period is of duration T S /2. A turn-off margin, also called dead-time, can be introduced in the design to ensure that the resonance terminates before the next switching event occurs. As soon as the inductor current reaches zero, the series diode is reversed biased which creates the dead-time. Therefore it is important to distinguish the switching period (T S ) from the resonance period of the L C parameters ( ). The resonance period is defined by the L C parameters of converter which create the sinusoidal shape of the inductor current waveform. The switching period is selected based on the switching capability of the devices and it has to be larger than the resonance period. The difference between the switching period and the resonance period is the dead-time. The relationship is formulated as 2 = T S 2 T dead (3) where is the resonance from the L C circuit, T S is the switching period and is the dead-time for the sub-period. By neglecting the losses and the impact of the dead-time, the output voltage is V OUT = MV S (4) where V S is the input voltage and M is the number of capacitors in the middle stage. Based on the designed power rating of the converter, the output load is 3.1 Capacitor sizing R load = V 2 OUT P rated (5) The amount of charges required by the load is used in the evaluation of the capacitor sizing. The amount of charges in a complete switching period T S at the load is given by Q load = V OUT R load T s (6) Capacitor C 1 : The first step consists of determining the capacitor value based on the desired capacitor voltage ripple. By using Q load and the selected voltage ripple, the capacitance is calculated by using C 1 = Q load DV C1 (8) where ΔV C1 is the peak-to-peak voltage ripple in volts Capacitor C out : The results obtained from (8) are not accurate for the output stage. It is explained by looking at the capacitor voltage waveforms from t 1 to t 2 reproduced in Fig. 4. The output voltage waveform does not have the sinusoidal shape as of capacitor C 1. Nevertheless, the output voltage waveform is analysed by linear superposition of the sinusoidal waveform related to the charge transfer from middle stage to output stage and of the discharging waveform from the R C circuit with the load. Since the time constant T RC (=R load C OUT ) is much larger than /2, the discharge from the load is linearly approximated. The voltage waveform of the output capacitor being charged is approximated using the following equation V OUT (t) = Q load 2C OUT [ ] 2p 1 cos t 2t + V OUT t 0 (9) By taking the first derivative of (9), the first local minimum is found at t min = sin 1 1 Tres (10) p 2p and first local maximum at [ ] t max = p sin 1 1 Tres p 2p (11) Therefore the peak-to-peak voltage ripple on the output capacitor is calculated with DV OUT = V OUT t max VOUT t min (12) Using (9) (12), the output capacitor value is calculated using the expression C out = Q load 1 [ DV OUT 2p 2 p sin 1 1 ] p p (13) where ΔV OUT is the desired peak-to-peak voltage ripple on the output capacitor voltage. 3.2 Inductor sizing The inductor is tailored such that the resonance in all configuration states D and D is. It is important to note 1735

4 that, unlike the capacitors, each inductor is used only during one sub-period, D or D. The equations are derived based on the L C configuration for each state. A resistance, labelled R L, in series with the inductor is included in the analysis. It is intended to model various resistances present in the system including inductor, IGBT, diode and wire losses Inductor L 1 : The inductor L 1 is used when the capacitors C 1 are connected in parallel (sub-period D) as shown in Fig. 2a. The circuit equivalent model is simply composed of parallel-connected capacitors in series with an inductance and a resistance. This resistance introduces a damping factor ζ in the system. More specifically, the resonance frequency is calculated using v res = v 0 1 z 2 (14) where ω 0 is the undamped natural frequency calculated by 1 v 0 = (15) L 1 MC 1 where L 1 is the inductor and MC 1 is the equivalent capacitance of the M parallel-connected capacitors C 1. The damping factor ζ is calculated using z = R L1 2 MC 1 L 1 (16) where R L1 is the loss resistance. Using (14) along with (15) and (16), the inductor is calculated using L 1 = 1 T 2 res 8p C eq1 ( 1 2p ) 2 C T eq1 R L1 (17) s where the equivalent capacitance C eq1 is MC Inductor L OUT : Mathematical complication arises for the computation of the output inductor L OUT because the output load is modelled by a resistance R load. During the charging of the output stage, the electric charges in the M series-connected capacitors C 1 are transferred through inductance L OUT to capacitor C OUT which is connected in parallel to the load resistance R load. The state configuration is shown in Fig. 2b. Using the output voltage waveform shown in Fig. 4, the analysis starts with the charging, in sub-period D, occurring between t 1 and t 3 and the discharging, in sub-period D, from t 3 to t 4. In order to size the output inductor, recursive numerical computation is used to solve this third order system. By using linear state-space equations, the state configuration is written in the form d dt x(t) = [ A ]x(t) (18) where x(t)=[i LOUT V C1 V OUT ] T and [A] is a 3 3 time-invariant matrix obtained from the three linear ordinary differential equations associated with the charging state configuration D from t 1 to t 3. Therefore the matrix [A] is given as [A] = R LOUT L OUT M L OUT 1 C C OUT 0 The solution for initial states, x(t 1 ), is x(t) = e [ A](t) xt 1 1 L OUT 1 R load C OUT (19) (20) Using Fig. 4 as guide, V OUT (t) has discharged and takes a value V OUT (t 1 ) at the beginning of the sub-period D. The diode has blocked previously and, therefore inductor current i LOUT (t 1 ) = 0.0. The capacitors C 1 have previously been charged in parallel to V S + 0.5ΔV C1 by the input stage. Therefore the initial state vector is 0.0 xt 1 = V S + DV C1 ( 2 (21) ) V OUT t 1 The initial conditions of i LOUT and V C1 are known but the value of V OUT (t 1 ) is unknown. Its value is required in order to compute a precise value of L OUT. By using (20), the solution for the charging phase from t 1 to t 2 is xt 2 = e [ A] ( 0.5 ) xt1 (22) A time t = t 2, the current i LOUT reaches zero and D OUT stops conducting. The voltage of C OUT has been recharged to V OUT (t 2 ) and the voltage for one series-connected capacitor C 1 has fallen to V S 0.5ΔV C1. The state vector x at t 2 is 0.0 xt 2 = V S DV C1 ( 2 (23) ) V OUT t 2 The relationship between V OUT (t 2 ) and V OUT (t 1 ) is made using remainder of state configuration D (dead-time period from t 2 to t 3 ) and the state configuration D (t 3 to t 4 ). The previously charged capacitor C OUT is being discharged by the load resistance R load. The well-known solution of R C circuit in parallel is V OUT (t) = V OUT t 2 e ( t/t RC ) (24) for (t 2 t t 4 ) and where the time constant T RC = R load C out. The exponentially decaying output voltage V out (t) resembles a straight line in Fig. 4 for time (t 2 t t 4 ). From periodicity, V OUT (t 4 )=V OUT (t 1 ), and using (24) for a duration of t 4 t 2 = T dead + 0.5T S, (25) is obtained. V OUT t 4 = VOUT t 1 = VOUT t 2 e ( ( T dead +0.5T S )/T RC ) (25) 1736

5 By combining (21) (23) and (25), it gives 0.0 V S DV C1 2 V OUT t 1 e (( T dead +0.5T S )/( T RC )) 0.0 = e [ A] ( 0.5) V S + DV C1 ( 2 (26) ) V OUT t 1 The matrix e [ A] ( 0.5) is a 3 3 matrix of constant nine real numbers which are evaluated using MATLAB. Equation (26) yields a linear algebraic system of three equations where the unknown V OUT (t 1 ) is found. By defining G = e [ A] ( 0.5), VOUT (t 1 ) is calculated as G (3, 2) V S + DV C1 /2 V OUT t 1 = (27) ( ) G(3, 3) e ( T dead +0.5T S)/ T RC where Γ (i, j) is the element at location (i, j) in the matrix Γ. The iterative design steps are (i) construct matrix [A] for a selected L OUT value, (ii) compute V OUT (t 1 ) using (27) and use it to create the state vector x(t 1 ) from (21) and (iii) with x(t 1 ), calculate x(t 2 ) using (22). The inductor current i LOUT should be zero at t 2. Thus, the value of L OUT is refined and iterative computations are done until the requirement is met Peak current: The peak current of the inductor is calculated by making use of the sinusoidal shape of the inductor current. The area under the inductor current curve equals the amount of charges that needs to be transferred as calculated withthe following equation Q load = t res p I peak LOUT (28) By neglecting losses and using (7), the peak current is calculated using I peak L = M 2 k p T S V OUT R load (29) where k = 1 for the inductor L 1 and k = 2 for L out. durations are 6 μs for inductor L 1 and 5 μs for L OUT. The voltage waveforms are as expected: during the D phase, the capacitor voltage C 1 is decreasing, whereas the voltage at V OUT is increasing. The middle stage is charging the output stage. During the D phase, capacitors C 1 are obtaining charged by the input source, whereas only the load is connected to C OUT. In Table 1, the capacitor voltages and the inductor peak currents are noted under the PSCAD column and the difference with the design value is shown. The capacitor average voltage and voltage ripple are very accurate with results within 1.5%. The discrepancies for the voltage are explained with the approximations made in the design procedure. More precisely, the voltage calculation in the design does not consider the small inductor resistance and the dead-time requirement. Regarding the inductor peak current, it is very close to the design value with difference within 0.01 ka. Table 1 Design parameters with PSCAD results Capacitor Design PSCAD Difference, % Average voltage, kv C C OUT Voltage ripple, kv ΔC ΔC OUT Inductor Peak current, ka L L OUT Table 2 Parameters for PSCAD simulation Rated power, P rated,mw 1 Number of capacitors C 1 M 4 Switching frequency, F S, Hz 2000 Input voltage, V S,kV 1 C 1, μf C OUT, μf 86.1 L 1, μh/mω 2.4/1 L OUT, μh/mω 81.0/1 Output resistor R load, Ω 16 4 Simulation results A Marx dc dc converter is simulated in PSCAD/EMTDC software package. The converter is operating at 2 khz with a dead-time requirement of 5 μs, the input voltage is 1 kv and the power rating is 1 MW. The converter has four capacitors (M = 4) in the middle stage and the design is done using previously described steps. The capacitors are selected based on a desired voltage ripple of ± 10% and they are listed in Table 1 under design. The inductor value for L 1 and L OUT are calculated to obtain proper resonance and the peak currents, listed in Table 1 under design, are calculated using (28). The parameters of the simulation are given in Table 2 and it includes loss resistance as discussed earlier. The inductor currents, capacitor voltages and switching signal are shown in Fig. 5. The inductor currents show adequate resonance and the current reaches zero before the end of each the switching period. The measured dead-time Fig. 5 Simulation results for Marx dc dc converter with M =

6 Table 3 Simulation parameters for comparison Converter Gain Common parameters input voltage, V S,kV switching frequency, F S, khz output resistor R load, Ω Boost converter duty-cycle L, μh/mω / / /29 C OUT, μf Marx dc dc converter L 1, μh/mω 2.53/ / /0.05 C 1, μf L OUT, μh/mω 24/0.5 87/ /6.8 C OUT, μf Boost comparison The Marx dc dc converter topology presented in this paper is compared with the conventional boost. The comparison is made for three different converter gains: 2, 4 and 8. The two topologies have the same input voltage, same switching frequency and same load. For a reasonable comparison, the capacitor values are selected to have a voltage ripple of ± 10%. For the Marx dc dc converter, the inductor value is based on the resonance frequency as described previously. Regarding the inductor value for the boost converter, a 15% inductor current ripple is selected. The resistance of the inductor is modelled using a R/L ratio of 20 and the power electronics components (IGBTs and diodes) are modelled with a 3 mω on-state resistance [18]. The parameters of the boost and the Marx dc dc converters for the three different gains are detailed in Table 3. The power ratings of the components are evaluated for comparison. The evaluation is based on the average current in the components and on the maximum voltage the component has to withstand. It is important to note that voltage sharing is not considered for components connected in series. In addition, converters in steady state are considered. The volt amp (VA) rating is listed in Table 4 and the results are obtained via PSCAD/EMTDC simulation. At dc gain of 2, the Marx dc dc converter has a disadvantage on the VA rating for the capacitor compared with boost converter. However, as the dc gain increases, the capacitor rating in Marx dc dc converter remains roughly constant but it increases for the boost converter. At dc gain of 8, the Marx dc dc converter has lower VA ratings on the inductor, capacitor and IGBT. Table 4 Comparison between boost and Marx dc dc converters Gain = 2 Gain = 4 Gain = 8 Boost Marx Boost Marx Boost Marx Power ratings, VA inductor capacitor IGBT diode efficiency (P out / P in ), % Fig. 6 Cascaded Marx dc dc converter with multiple stages (N) composed of M capacitors per stage The efficiency of the converters is also evaluated. At the gain of 2, the boost converter is superior by only 0.3% but as the dc gain increases the advantage goes on the Marx dc dc converter side. It is also interesting to note that the efficiency of the Marx dc dc converter increases as the gain increases. For higher dc gain, the Marx dc dc converter has more capacitor branches. As a results the incoming inductor current is divided between more capacitors which results in smaller current in each branch switches and, therefore smaller I 2 R losses. At dc gain of 8, the efficiency of the Marx dc dc converter is evaluated at 98.3% compared with 96.8% for the boost converter. The Marx dc dc converter is, therefore very competitive compared to the conventional boost. 6 Cascaded Marx dc dc converter The Marx dc dc converter can take advantage of the cascade configuration by inserting multiple stages in series as shown in Fig. 6. The input and output stages are the same as for the single stage arrangement of Fig. 1. The cascaded Marx dc dc converter operates synchronously with the two sub-periods. In the first sub-period, D, odd-numbered stages are connected in parallel and they are obtaining charge by the even-numbered stages which are series-connected. For example, if N is an odd number, the charging goes from the input voltage source to stage 1, from stage 2 to stage 3 and from stage N 1 to stage N. In the second sub-period, D, the even-numbered stages are connected in parallel and they are obtaining charge by the odd-numbered stages which are series-connected. In this situation, the transfer goes from stage 1 to stage 2, from stage 3 to stage 4 and from stage N to the output stage. In this example, the output stage is on the D sequence like an even-numbered stage but it can clearly be on the D sequence if N is an even number. After each stage, the average voltage has increased by a factor of M which results in a total amplification of M N where N is the number of stages and M is the number capacitors per stage. Moreover, the VA rating of each stage remains constant since between each stage the current decreases by M, whereas the voltage increases by M. 6.1 Design The design of stage 1 and the output stage of the cascaded Marx dc dc converter is the same approach as described earlier. However, the design of the cascaded stages required some adjustments. By neglecting the losses, the capacitor voltage at each stage is V k = M k 1 V S (30) 1738

7 Table 5 Prototype parameters and modelling parameters Prototype parameters Experiment number of stage, N 2 capacitor per stage, M 2 switching frequency, F S, Hz 1949 input voltage, V S, V 110 C 1, μf/μf 366/366 C 2, μf/μf 151/152 C out, μf/μf 233 L 1 /R L1, μh/mω 4.9/3 L 2 /R L2, μh/mω 50/4 L OUT /R LOUT, μh/mω 95.3/4 output resistor R load, Ω 34.7 Modelling parameters Simulation input source Thévenin-equivalent, μh/mω 1.5/16 wire resistance between stages, mω 30 semiconductor forward voltage drop, V 0.6 semiconductor ON-resistance, mω 6 where k is the stage index number, ΔV Ck is the peak-to-peak voltage ripple in volts. For the inductor value calculation, (17) is used but instead of the equivalent capacitance MC 1, the equivalent capacitance used for L 2 to L N is C eqk = MC k 1C k C k 1 + M 2 C k (33) where k and k 1 are the stage index numbers. Referring to the iterative calculation for L out detailed in Section 3.2.2, the initial conditions at t 1 and t 2 for the capacitor charging the output stage are replaced by (M N 1 V S + ΔV CN /2) and (M N 1 V S ΔV CN /2) instead of voltages V C1 (t 1 ) and V C1 (t 2 ), respectively. The inductor peak current calculation is also update for cascaded stages as stated in (34) where k is stage number and k is assigned N + 1 for L OUT. Table 6 Experimental and simulation results I peak Lk = M 2N k+1 p T S V OUT R load (34) Measurements Experimental Simulation average input voltage, V average capacitor voltage, V C1, V average capacitor voltage V C2, V average output voltage, V average input power, kw average output power, kw peak current I L1, A peak current I L2, A peak current I LOUT, A where k is the stage index number which excludes the output stage. For the output voltage, it is calculated using simply V OUT = M N V S (31) where V S is the input voltage, M is the number of capacitors per stage and N is the total number of stages excluding the output stages. By using the same approach as for (8), the capacitance is calculated by using C k = Q load DV Ck M N k (32) 7 Experimental results A 5 kw prototype converter has been constructed to acquire experimental results. The configuration of the prototype is two stages (N = 2) with two capacitors per stage (M = 2) for a total dc gain of M N = 4. The complete list of parameters for the experiment is included in Table 5 and some measurements are listed in Table 6. The waveforms of the inductor currents are shown in Fig. 7a and the capacitor voltages are shown in Fig. 7b. The dc amplification gain of the prototype is 3.58 as opposed to the theoretical gain of 4. The voltage drop associated with the IGBTs and the diodes explains in part that discrepancy. A voltage drop of 1 V from the input switch is almost a 1% drop right at the beginning in this prototype. By considering all the switches in the circuit, it certainly influences the overall dc gain. However, by operating at higher voltage ratings, the forward voltage drops associated with the switching devices would be mitigated and it would be expected to have a lower impact on the dc gain. Nevertheless, the amplification has been demonstrated by having the average voltage at 102 V at stage 1, then at 197 V for stage 2 and finally at 390 V for Fig. 7 Prototype experimental results for 5 kw converter with two stages and two capacitors per stage a Inductor current waveforms of experimental results b Voltage waveforms of experimental results 1739

8 Table 7 Semiconductor power ratings Component Average current, A Maximum withstand voltage, V Power ratings, VA Fig. 8 Prototype performance for different power operating point S IN Stage 1 D D A S A S AA Stage 2 D D A S A S AA Output stage D OUT Fig. 9 EMTDC Simulation results of prototype modelling in PSCAD/ 7.2 Semiconductor power ratings Using the same approach as in Section 5, the power rating of each semiconductor is evaluated using the prototype model developed previously. The average current and the maximum voltage the component has to withstand are listed in Table 7. Components are identified using the same labelling as in Fig. 1. Power ratings of the semiconductor are roughly constant between stages as the withstand voltage increases but the average current decreases. The input switch S IN and diode of stage 1, D 1, have lower power rating because the withstand voltage is smaller. The prototype is stable and it amplifies the dc voltage as expected. The laboratory experiment is successful with respect to demonstration of the concept and the operation of the converter. In addition, the simulation model confirms the validity of the simulation tool and the model developed for this work. the output capacitor. The inductor peak currents are 147, 74 and 36 A for L 1, L 2 and L OUT, respectively. The converter gain and efficiency for different load have been tested and the results are shown in Fig. 8. The converter gain decreases almost linearly from 3.8 at 1 kw to 3.6 close to 5 kw. The decrease is in the order of 5%. The efficiency is at 95% at low load and it reaches 91% at rated load. The efficiency is relatively good considering that the converter is a prototype and it has not been optimised to minimise losses. 7.1 Prototype modelling The prototype has been modelled in PSCAD/EMTDC software package to compare the operation of the converter. Parameters listed in Table 5 are used and additional parameters used in the simulation are also listed in the same table. The inductor current waveforms are shown in Fig. 9 and it shows good agreement with the waveforms shown in Fig. 7a. The resonance period at the inductor L 1 has a longer dead-time period than the one observed in the experiment. It can be concluded that the inductance from that portion of the circuit is higher than what has been modelled. It explains the reason for the peak current in inductor L 1 to be higher that what have been observed experimentally. The voltage levels are very similar between the experiment and simulation results. 8 Variable gain The Marx dc dc converter by itself does not have the regulator property; it only amplifies its input voltage by the designed gain. As a result, it is necessary to add an additional stage at the input that will provide the control variable to regulate the output voltage. A variable step-up converter can be inserted at the input stage to fulfill this task. The step-up converter of variable gain combined with the fixed structure of the Marx dc dc converter provides a variable range of amplification. Moreover, the Marx dc dc converter can be designed with different dc gain for each stage to precisely tailor the dc gain to a specific value. In this case, the total converter gain would be M TOTAL = M N...M k...m 2 M 1 MB (35) where M B is the variable gain from the step-up converter and M k for k =1to N is the fixed gain at each stage of the Marx dc dc converter. Another alternative can be the use hard-switching of the IGBTs to vary the conduction period and, subsequently, vary the voltage charged. However, this option has not been studied in this work since the structure of the converter is based on soft-switching event of the IGBT paired with adequate resonance design. 1740

9 9 Conclusions This paper has presented the Marx dc dc converter topology for high-power high-voltage application. It is based on the principle of charging capacitors in parallel followed by reconnection in series to create higher voltage. The topology and the design have been described for single stage converter. The operation has been confirmed through simulation using PSCAD/EMTDC software package. The topology is compared with the conventional boost converter and the Marx dc dc converter is shown to be competitive and even advantageous for higher dc gain. Then, the cascaded configuration is presented to take advantage of the higher amplification factor. A 5 kw prototype has been constructed to demonstrate experimentally the operation of the converter. The experimental results show the operation of the converter as expected. The converter gain and efficiency is observed for the different operating points. Finally, variable amplification can be obtained by inserting a step-up converter at the input to have a continuous range of dc gain. 10 References 1 Marx, E.: Versuche über die Prüfung von Isolatoren mit Spannungsstöβen, Elektrotech. Z. ETZ, 1924, 45, pp ABB Power T&D Company Inc.: Electrical transmission and distribution reference book (ABB Inc., 1997, 5th edn.) 3 Clayton, C.G.: The generation of recurring high-voltage X-ray impulses, Proc. IEE I, Gen., 1952, 119, pp Cadilhon, B., Pecastaing, L., Reess, T., Gibert, A.: Low-stray inductance structure to improve the rise-time of a Marx generator, IET Electr. Power Appl., 2008, 2, (4), pp Kemp, M.A., Benwell, A., Burkhart, C., Larsen, R., MacNair, D., Nguyen, M., Olsen, J.: Final design of the SLAC P2 Marx Klystron modulator. Proc IEEE Pulsed Power Conf., 2011, pp Jovcic, D.: Step-up DC DC converter for megawatt size applications, IET Power Electron., 2009, 2, (6), pp Baek, J.-W., Yoo, D.-W., Rim, G.-H., Lai, J.-S.: Solid state Marx generator using series-connected IGBTs, IEEE Trans. Plasma Sci., 2005, 33, (4), pp Redondo, L.M., Silva, J.F.: Repetitive high-voltage solid-state Marx modulator design for various load conditions, IEEE Trans. Plasma Sci., 2009, 37, (8), pp Jiao, Y., Luo, F.L.: N-switched-capacitor buck converter: topologies and analysis, IET Power Electron., 2011, 4, (3), pp Zhu, G., Ioinovici, A.: Switched-capacitor power supplies: DC voltage ratio, efficiency, ripple, regulation. IEEE Int. Symp. on Circuits and Systems, 1996, pp Ioinovici, A.: Switched-capacitor power electronics circuits, IEEE Circuits Syst. Mag., 2001, 1, (3), pp Gu, D., Czarkowski, D., Ioinovici, A.: A large DC-gain highly efficient hybrid switched-capacitor-boost converter for renewable energy systems. IEEE Energy Conversion Congress and Exposition, 2011, pp Seeman, M.D., Sanders, S.R.: Analysis and optimization of switched-capacitor DC DC converters, IEEE Trans. Power Electron., 2008, 23, (2), pp Cao, D., Peng, F.Z.: Zero-current-switching multilevel modular switched-capacitor DC DC converter, IEEE Trans. Ind. Appl., 2012, 46, (6), pp Peng, F.Z., Qian, W., Cao, D.: Recent advances in multilevel converter/ inverter topologies and applications. Int. Power Electronics Conf., 2010, pp Cao, D., Peng, F.Z.: A family of zero current switching switched-capacitor dc-dc converters. IEEE Applied Power Electronics Conf. and Expo., 2010, pp Ortiz-Lopez, M.G., Leyva-Ramos, J., Carbajal-Gutierrez, E.E., Morales-Saldana, J.A.: Modelling and analysis of switch-mode cascade converters with a single active switch, IET Power Electron., 2008, 1, (4), pp Chaudhuri, N.R., Yazdani, A.: An aggregation scheme for offshore wind farms with VSC-based HVDC collection system. IEEE Power and Energy Society General Meeting,