Voltage Source Inverter (VSI)

Transcription

1 Voltage Source Inverter (VSI) Prof. Dr. Ing. Hans Georg Herzog Prof. Dr. Ing. Ralph Kennel Technische Universität München Arcisstraße München Germany 1

2 Voltage Source Inverter (VSI) Bridge Topology 2

3 Voltage Source Inverter (VSI) (Pulse Inverter) U 0 motor 3

4 Voltage Source Inverter (VSI) (Pulse Inverter) 4

5 Control Methods Voltage Source Inverter (VSI) a) amplitude control b) angle shifting control (block width control) c) pulse control (pulse width modulation PWM) 5

6 Voltage Graphs under Block Width Control u R0 u M0 u RS u R u S u T in case of multiphase windings the phasetophase voltage is active at the motor terminals within the motor the resulting phase voltage comes closer to the sinusoidal form than the phase voltage at the inverter 6!!!

7 Current Measurement in Suboscillation PWM Control 7

8 Symmetrical and Asymmetrical Suboscillation PWM Control symmetrical asymmetrical 8

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13 Space Vector/Phasor Modulation 13

14 Space Vector/Phasor Modulation free choice of zero vector 14

15 Space Vector/Phasor Modulation free choice of zero vector 15

16 Space Vector/Phasor Modulation T INV 16

17 PWM Hardware ASIC or FPGA 17

18 Voltage Graphs under Pulse Width Modulation (PWM) Pulse Patterns Vary with the Operation Point as well as the Frequency Ratio 18

19 Voltage Graphs under Pulse Width Modulation (PWM) Harmonics in Supply Voltages (Square Form) 19

20 Comparison : PWM Bangbang Control advantage: very dynamic disadvantage : variable switching frequency 20

21 PWM Schemes 21

22 PWM Schemes similar, but different pulse patterns Unterschwingungsverfahren suboscillation method 22

23 Space Vector/Phasor Modulation 23

24 PWM Schemes Suboscillation Method Space Vector/Phasor Modulation Addition of the 3rd harmonic PWM acc. to Schörner 1/6 of fundamental amplitude 1/4 of fundamental amplitude 24

25 Extension of Output Voltage Range by adding a 3rd harmonic is also possible when using the suboscillation method addition of the 3rd harmonic 1/6 of the fundamental amplitude space vector/phasor modulation 25

26 Discontinuous PWM Schemes 26

27 DC Link Capacitor Design Prof. Dr. Ing. Ralph Kennel Technische Universität München Arcisstraße München

28 DC Link Capacitance Design U 0 Motor Attention!!!! reactive power for the load is not relevant!!! 28

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34 Reactive Power Motor (e. g. induction machine) U 0 where does reactive power come from??? induction machines need reactive power for magnetization as the sum of reactive power in all 3 phases is zero ( 0 )! it is no problem for the inverter to provide it 34

35 Reactive Power Motor (e. g. induction machine) U 0 with regard to reactive power the inverter is like a marshalling yard (switching station) for trains! as the sum of reactive power in all 3 phases is zero ( 0 )! it is no problem for the inverter to provide it 35

36 Reactive Power Motor (e. g. induction machine) U 0 with regard to reactive power the inverter is like a marshalling yard (switching station) for trains! therefore inverters can be used easily for compensating reactive power in grids! especially in regenerative energy applications like wind power farms or solar power 36arrays!

37 DC Link Capacitance Design criteria : energy : E C = ½ * C * U C 2 energy fluctuation : E C = ½ * C * [(U C + U) 2 U C2 ] capacitance : C = 2 * E C / [ U * (2*U C + U)] 37

38 DC Link Capacitance Design line voltage V line voltage variation U = 10 1 V example : single phase power supply U 0 half line period 10 ms E capacitance : C = 100 Ws C = 2 * E C / [ U * (2*U C + U)] 10 kw Motor C = µf 38

39 DC Link Capacitance Design line voltage V line voltage variation U = 10 1 V example : single phase power supply U 0 half line period 10 ms E capacitance : C = 100 Ws C = 2 * E C / [ U * (2*U C + U)] 10 kw Motor C = µf 39

40 DC Link Capacitance Design criteria switching frequency : C = I * t t / U line voltage variations : C = I * t netz / 2 * U (2 pulsbrücke) C = I * t netz / 6 * U (6 pulsbrücke) inductive load 40

41 e. g. 420 µf DC Link + Capacitance + Design e. g. 100 A e. g. 200 µh U 0 E L = ½ L I 2 = ½ * Ws = 10 6 * 10 6 Ws = 1 Ws 41

42 e. g. 420 µf DC Link + Capacitance + Design e. g. 100 A e. g. 200 µh U 0 E C = ½ C U max 2 ½ C U nenn 2 = ½ C (U 2 max U nenn2 ) C = 2 * E C / (U 2 max U nenn2 ) = 2 * 1 / ( ) F = 35 µf 42

43 DC Link Capacitance Design criteria storage of kinetic energy of the drive is not realistic!!! solutions : fast supervision and switchoff (within µs) (consequence : drive coasting ) ballast switch with resistance in the DC link (consequence : drive decelerating) 43

44 DC Link Capacitance Design be careful with large capacitances (e. g. electrolythic capacitances) large capacitance results in low voltages variations this, however, means a significantly higher AC current (switchinh frequency)!!! many (electrolythic) Capacitances are not designed for a high AC current (see data sheet)!!! the AC current loading is very often decisive for the design!!! for that reason the capacitance of the DC link capacitor might be larger than indicated by calculation!!! 44

45 Voltage Source Inverter (VSI) Topologies Specific for Automotive Applications 45

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48 Power Semiconductor Devices Specific for Automotive Applications inverter topology usually used in industry reduced number of power devices inverter topology usually used in vehicles cost number of power devices compromise in performance! in DC machines there was the same effect with respect to commutators field effect transistors in earlier times (FET) as well!!! today : commutator cost sufficient commutator voltage range size (material input) question high : switching frequency can we expect in future power electronics cost silicon area??? can anything be done to accelerate this process (cost reduction)? bipolar transistors field effect transistors 48

49 Topologies Specific for Automotive Applications inverter topology usually used in industry + + inverter topology usually used in vehicles phase of motor parallel winding reasons low supply voltage (1 device in series only) less devices (but : more complex winding) 49