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8 Student should come with thorough preparation for the experiment to be conducted. Student should take prior permission from the concerned faculty before availing the leave. Student should come with proper dress code and to be present on time in the laboratory. Student will not be permitted to attend the laboratory unless they bring the practical record fully completed in all respects pertaining to the experiment conducted in the previous class. Student will not be permitted to attend the laboratory unless they bring the observation book fully completed in all respects pertaining to the experiment to be conducted in present class. Experiment should be started conducting only after the staff-in-charge has checked the circuit diagram. All the calculations should be made in the observation book. Specimen calculations for one set of readings have to be shown in the practical record. Wherever graphs to be drawn, A-4 size graphs only should be used and the same should be firmly attached in the practical record. Practical record and observation book should be neatly maintained. Student should obtain the signature of the staff-in-charge in the observation book after completing each experiment. Theory related to each experiment should be written in the practical record before procedure in your own words with appropriate references.

9 Question bank 59 Viva questions 60 Appendix

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17 R i) AV = 1+ R Assume R f A f = 10KΩ 10 KΩ = 1+ RA = KΩ R A f = 5KHz H ii) The cutoff frequency f H 1 = 2π R C R C π 1 1 R = = = 318 Ω 3 6 ( Use std 330Ω) 2π f C 2π X 5X10 X 0.1X10 H

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19 Gain (db) 3dB F H -40dB/dec f (Hz)

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21 R i) AV = 1+ R Assume R f A f = 10KΩ 10 KΩ = 1+ RA = KΩ R ii) The cutoff frequency f A L 1 fl = 2π R C R C = 5 KHz π

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23 Gain(dB) +40dB/dec f L 3dB f (Hz)

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25 Design 4 bit R-2R DAC for an output voltage, V 0 = 5V, when the input is (10) d [i.e., (1010) b ]. D 3 D 2 D 1 D 0 ( 10 ) 10 = ( ) 2

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29 Design 4 bit R-2R DAC for an output voltage, V 0 = 5V, when the input is (10) d [i.e., (1010) b ]. D 3 D 2 ( 10 ) 10 = ( 1 0 D 1 D ) 2

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39 V C V o Ton Ton 1 1 D = = = 0.66 T = = = 0.66ms 3 T + T T f 1.5X10 0n T = 0.66 X T = 0.66 X 0.66ms on off = 0.435ms T = T T = = 0.22ms 1 off µ C = 0.01 F R R B A 3 Ton X 10 = = = 62.77K Ω X C 0.693X 0.01X 10 3 Toff 0.22 X 10 = = = 31.7 K Ω X C 0.693X 0.01X 10

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41 Ω T = 1.1R C Td C = 1.1R R C T T d A << T T RT C T << d 10 d ( A = µ F Use0.047µ F standard capacitor )

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59 β βµ µω Ω Ω Ω µµ µµ Ω Ω µ Ω Ω π µ µ

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72 1 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community OFFSET N1 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY 2015 µa741 General-Purpose Operational Amplifiers 1 Features 3 Description 1 Short-Circuit Protection The µa741 device is a general-purpose operational amplifier featuring offset-voltage null capability. Offset-Voltage Null Capability Large Common-Mode and Differential Voltage The high common-mode input voltage range and the Ranges absence of latch-up make the amplifier ideal for voltage-follower applications. The device is short- No Frequency Compensation Required circuit protected and the internal frequency No Latch-Up compensation ensures stability without external components. A low value potentiometer may be 2 Applications connected between the offset null inputs to null out the offset voltage as shown in Figure 11. DVD Recorders and Players Pro Audio Mixers The µa741c device is characterized for operation from 0 C to 70 C. The µa741m device (obsolete) is characterized for operation over the full military temperature range of 55 C to 125 C. 4 Simplified Schematic Device Information (1) PART NUMBER PACKAGE (PIN) BODY SIZE (NOM) SOIC (8) 4.90 mm 3.91 mm µa741x PDIP (8) 9.81 mm 6.35 mm SO (8) 6.20 mm 5.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. IN + IN OFFSET N2 + OUT An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

73 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Table of Contents 1 Features Applications Description Simplified Schematic Revision History Pin Configurations and Functions Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical CharacteristicsA741C,A741M Electrical CharacteristicsA741Y Switching CharacteristicsA741C,A741M Switching CharacteristicsA741Y Typical Characteristics Detailed Description Overview Functional Block Diagram Feature Description Device Functional Modes µa741y Chip Information Application and Implementation Application Information Typical Application Power Supply Recommendations Layout Layout Guidelines Layout Example Device and Documentation Support Trademarks Electrostatic Discharge Caution Glossary Mechanical, Packaging, and Orderable Information Revision History Changes from Revision D (February 2014) to Revision E Page Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging,andOrderableInformation section MovedTypicalCharacteristics intospecifications section Changes from Revision C (January 2014) to Revision D Page FixedTypicalCharacteristics graphs to remove extra lines Changes from Revision B (September 2000) to Revision C Page Updated document to new TI data sheet format - no specification changes DeletedOrderingInformation table Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

74 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Pin Configurations and Functions NC NC OFFSET N1 IN IN+ V CC NC µa741m... J PACKAGE (TOP VIEW) NC NC NC V CC+ OUT OFFSET N2 NC µa741m... JG PACKAGE µ A741C, µ A741I... D, P, OR PW PACKAGE (TOP VIEW) OFFSET N1 IN IN+ V CC NC V CC+ OUT OFFSET N2 µa741m... U PACKAGE (TOP VIEW) µa741m... FK PACKAGE (TOP VIEW) NC OFFSET N1 IN IN+ V CC NC NC V CC+ OUT OFFSET N2 NC IN NC IN+ NC NC OFFSET N1 NC NC NC NC V CC+ NC OUT NC V NC NC CC OFFSET N2 NC NC No internal connection Pin Functions PIN NAME JG, D, P, or TYPE DESCRIPTION J U FK PW IN I Noninverting input IN I Inverting input NC 1, 2, 8, 1,3,4,6,8,9,11,13,1 12, 13, 8 1, 9, 10 4,16,18,19,20 14 Do not connect OFFSET N I External input offset voltage adjustment OFFSET N I External input offset voltage adjustment OUT O Output V CC Positive supply V CC Negative supply Copyright , Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ua741

75 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Specifications 7.1 Absolute Maximum Ratings over virtual junction temperature range (unless otherwise noted) (1) µa741c µa741m MIN MAX MIN MAX V CC Supply voltage (2) C V ID Differential input voltage (3) V V I Input voltage, any input (2)(4) V Voltage between offset null (either OFFSET N1 or OFFSET N2) and V CC V Duration of output short circuit (5) Unlimited Continuous total power dissipation See Table 1 T A Operating free-air temperature range C Case temperature for 60 seconds FK package N/A N/A 260 C Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds J, JG, or U package N/A N/A 300 C D, P, or PS package 260 N/A N/A C T stg Storage temperature range C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, unless otherwise noted, are with respect to the midpoint between V CC+ and V CC. (3) Differential voltages are at IN+ with respect to IN. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) The output may be shorted to ground or either power supply. For the µa741m only, the unlimited duration of the short circuit applies at (or below) 125 C case temperature or 75 C free-air temperature. 7.2 Recommended Operating Conditions UNIT MIN MAX UNIT V CC Supply voltage V CC 5 15 µa741c 0 70 T A Operating free-air temperature C µa741m Table 1. Dissipation Ratings Table T A 25 C TA = 70 C DERATING DERATE T A = 85 C T A = 125 C PACKAGE POWER POWER FACTOR ABOVE T A POWER RATING POWER RATING RATING RATING D 500 mw 5.8 mw/ C 64 C 464 mw 377 mw N/A FK 500 mw 11.0 mw/ C 105 C 500 mw 500 mw 275 mw J 500 mw 11.0 mw/ C 105 C 500 mw 500 mw 275 mw JG 500 mw 8.4 mw/ C 90 C 500 mw 500 mw 210 mw P 500 mw N/A N/A 500 mw 500 mw N/A PS 525 mw 4.2 mw/ C 25 C 336 mw N/A N/A U 500 mw 5.4 mw/ C 57 C 432 mw 351 mw 135 mw V 4 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

76 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Electrical CharacteristicsA741C,A741M at specified virtual junction temperature, V CC± = ±15 V (unless otherwise noted) PARAMETER TEST CONDITIONS T A (1) A741C A741M MIN TYP MAX MIN TYP MAX 25 C V IO Input offset voltage V O = 0 mv Full range 7.5 ±15 6 V IO(adj) Offset voltage adjust range V O = 0 25 C ± mv 25 C I IO Input offset current V O = 0 na Full range C I IB Input bias current V O = 0 na Full range C ±12 ±13 ±12 ±13 V ICR Common-mode input voltage range V Full range ±12 ±12 R L = 10 k 25 C ±12 ±14 ±12 ±14 R L 10 k Full range ±12 ±12 V OM Maximum peak output voltage swing V R L = 2 k 25 C ±10 ±10 ±13 A VD R L 2k Full range ±10 ±10 Large-signal differential voltage R L 2k 25 C amplification V O = ±10 V Full range r i Input resistance 25 C M r o Output resistance V O = 0, See (2) 25 C C i Input capacitance 25 C pf 25 C CMRR Common-mode rejection ratio V IC = V ICRmin db Full range C k SVS Supply voltage sensitivity (V IO /V CC ) V CC = ±9 V to ±15 V µv/v Full range I OS Short-circuit output current 25 C ±25 ±40 ±25 ±40 ma 25 C I CC Supply current V O = 0, No load ma Full range C P D Total power dissipation V O = 0, No load mw Full range (1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for the µa741c is 0 C to 70 C and the µa741m is 55 C to 125 C. (2) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. UNIT V/mV Copyright , Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ua741

77 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Electrical CharacteristicsA741Y at specified virtual junction temperature, V CC± = ±15 V, T A = 25 C (unless otherwise noted) (1) A741Y PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V IO Input offset voltage V O = mv V IO(adj) Offset voltage adjust range V O = 0 ±15 mv I IO Input offset current V O = na I IB Input bias current V O = na V ICR Common-mode input voltage range ±12 ±13 V R L = 10 k ±12 ±14 V OM Maximum peak output voltage swing V R L = 2 k ±10 ±13 A VD Large-signal differential voltage amplification R L 2k V/mV r i Input resistance M r o Output resistance V O = 0, See (1) 75 C i Input capacitance 1.4 pf CMRR Common-mode rejection ratio V IC = V ICRmin db k SVS Supply voltage sensitivity (V IO /V CC ) V CC = ±9 V to ±15 V µv/v I OS Short-circuit output current ±25 ±40 ma I CC Supply current V O = 0, No load ma P D Total power dissipation V O = 0, No load mw (1) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. 7.5 Switching CharacteristicsA741C,A741M over operating free-air temperature range, V CC± = ±15 V, T A = 25 C (unless otherwise noted) µa741c µa741m PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX t r Rise time V I = 20 mv, R L = 2 k, µs Overshoot factor C L = 100 pf, See Figure 1 5% 5% V I = 10 V, R L = 2 k, SR Slew rate at unity gain V/µs C L = 100 pf, See Figure Switching CharacteristicsA741Y over operating free-air temperature range, V CC± = ±15 V, T A = 25 C (unless otherwise noted) µa741y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX t r Rise time V I = 20 mv, R L = 2 k, 0.3 µs Overshoot factor C L = 100 pf, See Figure 1 5% V I = 10 V, R L = 2 k, SR Slew rate at unity gain 0.5 V/µs C L = 100 pf, See Figure 1 6 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

78 V I IB Input Bias Current na Maximum Peak Output Voltage V OM I ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Typical Characteristics Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. VI OUT 0 V IN + INPUT VOLTAGE WAVEFDORM CL = 100 pf RL = 2 kω TEST CIRCUIT Figure 1. Rise Time, Overshoot, and Slew Rate Input Offset Current na IO VCC+ = 15 V VCC = 15 V VCC+ = 15 V VCC = 15 V V ±14 ±13 ±12 ±11 ±10 ±9 ±8 ±7 ±6 ±5 ±4 0.1 TA Free-Air Temperature C Figure 2. Input Offset Current vs Free-Air Temperature VCC+ = 15 V VCC = 15 V TA = 25 C RL Load Resistance kω Figure 4. Maximum Output Voltage vs Load Resistance Maximum Peak Output Voltage V OM ±20 ±18 ±16 ±14 ±12 ±10 ±8 ±6 ±4 ± VCC+ = 15 V VCC = 15 V RL = 10 kω TA = 25 C TA Free-Air Temperature C Figure 3. Input Bias Current vs Free-Air Temperature 1k 10k 100k f Frequency Hz Figure 5. Maximum Peak Output Voltage vs Frequency 1M Copyright , Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ua741

79 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Typical Characteristics (continued) Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. A VD Open-Loop Signal Differential Voltage Amplification V/mV CMRR Common-Mode Rejection Ratio db VO = ±10 V RL = 2 kω TA = 25 C VCC+ = 15 V VCC = 15 V BS = 10 kω TA = 25 C 10k 1M 100M f Frequency Hz Figure 8. Common-Mode Rejection Ratio vs Frequency Input and Output Voltage V 14 VCC± Supply Voltage V Figure 6. Open-Loop Signal Differential Voltage Amplification vs Supply Voltage VO VI A VD Open-Loop Signal Differential Voltage Amplification db Output Voltage mv V O f Frequency Hz Figure 7. Open-Loop Large-Signal Differential Voltage Amplification vs Frequency VCC+ = 15 V VCC = 15 V RL = 2 kω CL = 100 pf TA = 25 C 10% k 10k 100k 0 90% 0.5 tr 1 VCC+ = 15 V VCC = 15 V VO = ±10 V RL = 2 kω TA = 25 C VCC+ = 15 V VCC = 15 V RL = 2 kω CL = 100 pf TA = 25 C M 10M 2.5 t Time - µs Figure 9. Output Voltage vs Elapsed Time t Time ms Figure 10. Voltage-Follower Large-Signal Pulse Response 8 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

80 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Detailed Description 8.1 Overview The µa741 device is a general-purpose operational amplifier featuring offset-voltage null capability. The high common-mode input voltage range and the absence of latch-up make the amplifier ideal for voltagefollower applications. The device is short-circuit protected and the internal frequency compensation ensures stability without external components. A low value potentiometer may be connected between the offset null inputs to null out the offset voltage as shown in Figure 11. The µa741c device is characterized for operation from 0 C to 70 C. The µa741m device (obsolete) is characterized for operation over the full military temperature range of 55 C to 125 C. 8.2 Functional Block Diagram VCC+ IN IN+ OUT OFFSET N1 OFFSET N2 VCC Component Count Transistors 22 Resistors 11 Diode 1 Capacitor 1 Copyright , Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ua741

81 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Feature Description Offset-Voltage Null Capability The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these mismatches by external circuitry. See the Application and Implementation section for more details on design techniques Slew Rate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. The µa741 has a 0.5-V/s slew rate. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics graphs. 8.4 Device Functional Modes The µa741 is powered on when the supply is connected. It can be operated as a single supply operational amplifier or dual supply amplifier depending on the application. 8.5 µa741y Chip Information This chip, when properly assembled, displays characteristics similar to the µa741c. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (8) (7) (6) IN+ IN OFFSET N1 OFFSET N2 (3) (2) (1) (5) + VCC+ (7) (4) VCC (6) OUT 45 (5) (1) (4) CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM (2) (3) TJmax = 150 C. TOLERANCES ARE ±10%. 36 ALL DIMENSIONS ARE IN MILS. 10 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

82 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these mismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a potentiometer between the inputs as shown in Figure 13. A potentiometer can be used to fine tune the circuit during testing or for applications which require precision offset control. More information about designing using the input-offset pins, see the application note Nulling Input Offset Voltage of Operational Amplifiers, SLOA045. IN+ IN OFFSET N1 + OUT OFFSET N2 10 kω To VCC Figure 11. Input Offset Voltage Null Circuit 9.2 Typical Application The voltage follower configuration of the operational amplifier is used for applications where a weak signal is used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current as necessary to the output load. 10 k 12 V + VOUT VIN Figure 12. Voltage Follower Schematic Design Requirements Output range of 2 V to 11.5 V Input range of 2 V to 11.5 V Copyright , Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ua741

83 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Typical Application (continued) Resistive feedback to negative input Detailed Design Procedure Output Voltage Swing The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output voltage requirements Supply and Input Voltage For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to 11.5 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground allows the amplifier to maintain linearity for inputs below 2 V Application Curves for Output Characteristics VOUT (V) VIN (V) C001 IIO (ma) VIN (V) Figure 13. Output Voltage vs Input Voltage Figure 14. Current Drawn Input of Voltage Follower (I IO ) vs Input Voltage C ICC (ma) VIN (V) Figure 15. Current Drawn from Supply (I CC ) vs Input Voltage C Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

84 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Power Supply Recommendations TheA741 is specified for operation from ±5 to ±15 V; many specifications apply from 0 C to 70 C. TheTypical Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than ±18 V can permanently damage the device (see the Absolute Maximum Ratings). Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines. 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. Connect low-esr, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, SLOA089. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Example. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials Layout Example VIN RIN + VOUT RG RF Figure 16. Operational Amplifier Schematic for Noninverting Configuration Copyright , Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: ua741

85 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Layout Example (continued) Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible RF GND RG NC IN1 NC VCC+ VS+ Use low-esr, ceramic bypass capacitor VIN IN1+ OUT RIN Only needed for dual-supply operation GND VCC VS- (or GND for single supply) VOUT NC GND Ground (GND) plane on another layer Figure 17. Operational Amplifier Board Layout for Noninverting Configuration 14 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: ua741

86 ua741 SLOS094E NOVEMBER 1970 REVISED JANUARY Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates Glossary SLYZ022 TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Copyright , Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: ua741

87 PACKAGE OPTION ADDENDUM 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan UA741CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) UA741CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) UA741CDR ACTIVE SOIC D Green (RoHS & no Sb/Br) UA741CDRG4 ACTIVE SOIC D Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C UA741CJG OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70 UA741CJG4 OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70 UA741CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) UA741CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) UA741CPSR ACTIVE SO PS Green (RoHS & no Sb/Br) UA741CPSRE4 ACTIVE SO PS Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UA741CP CU NIPDAU N / A for Pkg Type 0 to 70 UA741CP CU NIPDAU Level-1-260C-UNLIM 0 to 70 U741 CU NIPDAU Level-1-260C-UNLIM 0 to 70 U741 UA741MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125 UA741MJ OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125 UA741MJB OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125 UA741MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125 UA741MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125 (4/5) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples

88 PACKAGE OPTION ADDENDUM 10-Jun-2014 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

89 PACKAGE MATERIALS INFORMATION 17-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant UA741CDR SOIC D Q1 UA741CPSR SO PS Q1 Pack Materials-Page 1

90 PACKAGE MATERIALS INFORMATION 17-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UA741CDR SOIC D UA741CPSR SO PS Pack Materials-Page 2

91 MECHANICAL DATA MCER001A JANUARY 1995 REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE (10,16) (9,00) (7,11) (6,22) (1,65) (1,14) (1,60) (0,38) (0,51) MIN (7,87) (7,37) (5,08) MAX Seating Plane (3,30) MIN (2,54) (0,58) (0,38) (0,36) (0,20) /C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX DALLAS, TEXAS 75265

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99 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as components ) are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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100 1 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LM555 Timer LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Features 3 Description 1 Direct Replacement for SE555/NE555 The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional Timing from Microseconds through Hours terminals are provided for triggering or resetting if Operates in Both Astable and Monostable Modes desired. In the time delay mode of operation, the time Adjustable Duty Cycle is precisely controlled by one external resistor and Output Can Source or Sink 200 ma capacitor. For a stable operation as an oscillator, the free running frequency and duty cycle are accurately Output and Supply TTL Compatible controlled with two external resistors and one Temperature Stability Better than 0.005% per C capacitor. The circuit may be triggered and reset on Normally On and Normally Off Output falling waveforms, and the output circuit can source or sink up to 200 ma or drive TTL circuits. Available in 8-pin VSSOP Package Device Information (1) 2 Applications PART NUMBER PACKAGE BODY SIZE (NOM) Precision Timing SOIC (8) 4.90 mm 3.91 mm Pulse Generation LM555 PDIP (8) 9.81 mm 6.35 mm Sequential Timing VSSOP (8) 3.00 mm 3.00 mm Time Delay Generation (1) For all available packages, see the orderable addendum at Pulse Width Modulation the end of the datasheet. Pulse Position Modulation Linear Ramp Generator Schematic Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

101 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Table of Contents 1 Features Applications Description Revision History Pin Configuration and Functions Specifications Absolute Maximum Ratings ESD Ratings Recommended Operating Conditions Thermal Information Electrical Characteristics Typical Characteristics Detailed Description Overview Functional Block Diagram Feature Description Device Functional Modes Application and Implementation Application Information Typical Application Power Supply Recommendations Layout Layout Guidelines Layout Example Device and Documentation Support Trademarks Electrostatic Discharge Caution Glossary Mechanical, Packaging, and Orderable Information Revision History Changes from Revision C (March 2013) to Revision D Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device anddocumentationsupport section, andmechanical,packaging,andorderableinformation section... 1 Changes from Revision B (March 2013) to Revision C Page Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

102 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Pin Configuration and Functions D, P, and DGK Packages 8-Pin PDIP, SOIC, and VSSOP Top View GND 1 8 +V CC TRIGGER 2 COMPAR- ATOR R 7 DISCHARGE FLIP FLOP R OUTPUT 3 OUTPUT STAGE R COMPAR- ATOR 6 THRESHOLD RESET 4 VREF (INT) 5 CONTROL VOLTAGE NO. PIN NAME I/O Pin Functions DESCRIPTION Control Controls the threshold and trigger levels. It determines the pulse width of the output 5 Voltage I waveform. An external voltage applied to this pin can also be used to modulate the output waveform Discharge 7 I 1 GND O Ground reference voltage 3 Output O Output driven waveform Reset 4 I Threshold 6 I Trigger 2 I 8 V + I Supply voltage with respect to GND Open collector output which discharges a capacitor between intervals (in phase with output). It toggles the output from high to low when voltage reaches 2/3 of the supply voltage Negative pulse applied to this pin to disable or reset the timer. When not used for reset purposes, it should be connected to VCC to avoid false triggering Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop Responsible for transition of the flip-flop from set to reset. The output of the timer depends on the amplitude of the external trigger pulse applied to this pin Copyright , Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM555

103 over operating free-air temperature range (unless otherwise noted) (1)(2) MIN MAX UNIT LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Specifications 6.1 Absolute Maximum Ratings LM555CM, LM555CN (4) 1180 mw Power Dissipation (3) LM555CMM 613 mw Soldering Information PDIP Package Soldering (10 Seconds) 260 C Small Outline Packages (SOIC and Vapor Phase (60 Seconds) 215 C VSSOP) Infrared (15 Seconds) 220 C Storage temperature, T stg C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. (3) For operating at elevated temperatures the device must be derated above 25 C based on a 150 C maximum junction temperature and a thermal resistance of 106 C/W (PDIP), 170 C/W (S0IC-8), and 204 C/W (VSSOP) junction to ambient. (4) Refer to RETS555X drawing of military LM555H and LM555J versions for specifications. 6.2 ESD Ratings VALUE V (ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500 (2) V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) The ESD information listed is for the SOIC package. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) UNIT MIN MAX UNIT Supply Voltage 18 V Temperature, T A 0 70 C Operating junction temperature, T J 70 C 6.4 Thermal Information LM555 THERMAL METRIC (1) PDIP SOIC VSSOP UNIT 8 PINS R JA Junction-to-ambient thermal resistance C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

104 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Electrical Characteristics (T A = 25 C, V CC = 5 V to 15 V, unless otherwise specified) (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Voltage V Supply Current V CC = 5 V, R L = 3 6 Timing Error, Monostable V CC = 15 V, R L = (Low State) (3) Initial Accuracy 1 % Drift with Temperature R A = 1 k to 100 k, 50 ppm/ C C = 0.1F, (4) Accuracy over Temperature 1.5 % Drift with Supply 0.1 % V Timing Error, Astable Initial Accuracy 2.25 Drift with Temperature R A, R B =1 k to 100 k, 150 ppm/ C C = 0.1F, (4) Accuracy over Temperature 3.0% Drift with Supply 0.30 % /V Threshold Voltage x V CC Trigger Voltage V CC = 15 V 5 V V CC = 5 V 1.67 V Trigger Current A Reset Voltage V Reset Current ma Threshold Current (5) A Control Voltage Level V CC = 15 V V CC = 5 V Pin 7 Leakage Output High na Pin 7 Sat (6) Output Low V CC = 15 V, I 7 = 15 ma 180 mv Output Low V CC = 4.5 V, I 7 = 4.5 ma mv Output Voltage Drop (Low) V CC = 15 V I SINK = 10 ma V I SINK = 50 ma V I SINK = 100 ma V I SINK = 200 ma 2.5 V V CC = 5 V I SINK = 8 ma I SINK = 5 ma V (1) All voltages are measured with respect to the ground pin, unless otherwise specified. (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within the Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. (3) Supply current when output high typically 1 ma less at V CC = 5 V. (4) Tested at V CC = 5 V and V CC = 15 V. (5) This will determine the maximum value of R A + R B for 15 V operation. The maximum total (R A + R B ) is 20 M. (6) No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded. ma V V Copyright , Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM555

105 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Electrical Characteristics (continued) (T A = 25 C, V CC = 5 V to 15 V, unless otherwise specified) (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output Voltage Drop (High) I SOURCE = 200 ma, V CC = 15 V 12.5 V I SOURCE = 100 ma, V CC = 15 V V V CC = 5 V V Rise Time of Output 100 ns Fall Time of Output 100 ns 6.6 Typical Characteristics Figure 1. Minimum Pulse Width Required For Triggering Figure 2. Supply Current vs. Supply Voltage Figure 3. High Output Voltage vs. Output Source Current Figure 4. Low Output Voltage vs. Output Sink Current 6 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

106 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY 2015 Typical Characteristics (continued) Figure 5. Low Output Voltage vs. Output Sink Current Figure 6. Low Output Voltage vs. Output Sink Current Figure 7. Output Propagation Delay vs. Voltage Level of Trigger Pulse Figure 8. Output Propagation Delay vs. Voltage Level of Trigger Pulse Figure 9. Discharge Transistor (Pin 7) Voltage vs. Sink Current Figure 10. Discharge Transistor (Pin 7) Voltage vs. Sink Current Copyright , Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM555

107 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Detailed Description 7.1 Overview The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or driver TTL circuits. The LM555 are available in 8-pin PDIP, SOIC, and VSSOP packages and is a direct replacement for SE555/NE Functional Block Diagram THRESHOLD CONTROL VOLTAGE +Vcc RESET COMPARATOR V ref (int) TRIGGER FLIP FLOP COMPARATOR DISCHARGE OUTPUT STAGE OUTPUT 7.3 Feature Description Direct Replacement for SE555/NE555 The LM555 timer is a direct replacement for SE555 and NE555. It is pin-to-pin compatible so that no schematic or layout changes are necessary. The LM555 come in an 8-pin PDIP, SOIC, and VSSOP package Timing From Microseconds Through Hours The LM555 has the ability to have timing parameters from the microseconds range to hours. The time delay of the system can be determined by the time constant of the R and C value used for either the monostable or astable configuration. A nomograph is available for easy determination of R and C values for various time delays Operates in Both Astable and Monostable Mode The LM555 can operate in both astable and monostable mode depending on the application requirements. Monostable mode: The LM555 timer acts as a one-shot pulse generator. The pulse beings when the LM555 timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the 8 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

108 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY 2015 Feature Description (continued) capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting the R and C values. Astable (free-running) mode: The LM555 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values of R A, R B, and C. 7.4 Device Functional Modes Monostable Operation In this mode of operation, the timer functions as a one-shot (Figure 11). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 V CC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. Figure 11. Monostable The voltage across the capacitor then increases exponentially for a period of t = 1.1 R A C, at the end of which time the voltage equals 2/3 V CC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 12 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. V CC = 5 V TIME = 0.1 ms/div. R A = 9.1 k C = 0.01F Top Trace: Input 5V/Div. Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 2V/Div. Figure 12. Monostable Waveforms During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 s before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not in use, TI recommends connecting the Reset pin to V CC to avoid any possibility of false triggering. Copyright , Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM555

109 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Device Functional Modes (continued) Figure 13 is a nomograph for easy determination of R, C values for various time delays Astable Operation Figure 13. Time Delay If the circuit is connected as shown in Figure 14 (pins 2 and 6 connected) it will trigger itself and free run as a multivibrator. The external capacitor charges through R A + R B and discharges through R B. Thus the duty cycle may be precisely set by the ratio of these two resistors. Figure 14. Astable In this mode of operation, the capacitor charges and discharges between 1/3 V CC and 2/3 V CC. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage. Figure 15 shows the waveforms generated in this mode of operation. 10 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

110 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY 2015 Device Functional Modes (continued) V CC = 5 V TIME = 20s/DIV. R A = 3.9 k R B = 3 k C = 0.01F Top Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 1V/Div. Figure 15. Astable Waveforms The charge time (output high) is given by: t 1 = (R A + R B ) C (1) And the discharge time (output low) by: t 2 = (R B ) C (2) Thus the total period is: T = t 1 + t 2 = (R A +2R B ) C (3) The frequency of oscillation is: Figure 16 may be used for quick determination of these RC values. The duty cycle is: (4) (5) Figure 16. Free Running Frequency Copyright , Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM555

111 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM555 timer can be used a various configurations, but the most commonly used configuration is in monostable mode. A typical application for the LM555 timer in monostable mode is to turn on an LED for a specific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low. This simple application can be modified to fit any application requirement. 8.2 Typical Application Figure 17 shows the schematic of the LM555 that flashes an LED in monostable mode Design Requirements Figure 17. Schematic of Monostable Mode to Flash an LED The main design requirement for this application requires calculating the duration of time for which the output stays high. The duration of time is dependent on the R and C values (as shown in Figure 17) and can be calculated by: t = 1.1 R C seconds (6) Detailed Design Procedure To allow the LED to flash on for a noticeable amount of time, a 5 second time delay was chosen for this application. By using Equation 6, RC equals If R is selected as 100 k, C = 45.4 µf. The values of R = 100 k and C = 47 µf was selected based on standard values of resistors and capacitors. A momentary push button switch connected to ground is connected to the trigger input with a 10-K current limiting resistor pullup to the supply voltage. When the push button is pressed, the trigger pin goes to GND. An LED is connected to the output pin with a current limiting resistor in series from the output of the LM555 to GND. The reset pin is not used and was connected to the supply voltage Frequency Divider The monostable circuit of Figure 11 can be used as a frequency divider by adjusting the length of the timing cycle. Figure 18 shows the waveforms generated in a divide by three circuit. 12 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

112 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY 2015 Typical Application (continued) V CC = 5 V TIME = 20s/DIV. R A = 9.1 k C = 0.01F Top Trace: Input 4 V/Div. Middle Trace: Output 2V/Div. Bottom Trace: Capa citor 2V/Div. Figure 18. Frequency Divider Additional Information Lower comparator storage time can be as long as 10s when pin 2 is driven fully to ground for triggering. This limits the monostable pulse width to 10s minimum. Delay time reset to output is 0.47s typical. Minimum reset pulse width must be 0.3s, typical. Pin 7 current switches within 30 ns of the output (pin 3) voltage Application Curves The data shown below was collected with the circuit used in the typical applications section. The LM555 was configured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to: Top Waveform (Yellow) Capacitor voltage Middle Waveform (Green) Trigger Bottom Waveform (Purple) Output As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C value. For this example, the time delay is 5.17 s. Copyright , Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM555

113 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Typical Application (continued) Figure 19. Trigger, Capacitor Voltage, and Output Waveforms in Monostable Mode 14 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

114 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Power Supply Recommendations The LM555 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary to protect associated circuitry. The minimum recommended capacitor value is 0.1 F in parallel with a 1-F electrolytic capacitor. Place the bypass capacitors as close as possible to the LM555 and minimize the trace length. 10 Layout 10.1 Layout Guidelines Standard PCB rules apply to routing the LM555. The 0.1-µF capacitor in parallel with a 1-µF electrolytic capacitor should be as close as possible to the LM555. The capacitor used for the time delay should also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity. Figure 20 is the basic layout for various applications. C1 based on time delay calculations C µF bypass capacitor for control voltage pin C3 0.1-µF bypass ceramic capacitor C4 1-µF electrolytic bypass capacitor R1 based on time delay calculations U1 LMC Layout Example Figure 20. Layout Example Copyright , Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: LM555

115 LM555 SNAS548D FEBRUARY 2000 REVISED JANUARY Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates Glossary SLYZ022 TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 16 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM555

116 PACKAGE OPTION ADDENDUM 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan LM555-MWC ACTIVE WAFERSALE YS 0 1 Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp Call TI Level-1-NA-UNLIM -40 to 85 (3) Op Temp ( C) Device Marking LM555CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM 555CM LM555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM 555CM LM555CMM NRND VSSOP DGK TBD Call TI Call TI 0 to 70 Z55 LM555CMM/NOPB ACTIVE VSSOP DGK Green (RoHS & no Sb/Br) LM555CMMX/NOPB ACTIVE VSSOP DGK Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 Z55 CU SN Level-1-260C-UNLIM 0 to 70 Z55 LM555CMX NRND SOIC D TBD Call TI Call TI 0 to 70 LM 555CM LM555CMX/NOPB ACTIVE SOIC D Green (RoHS & no Sb/Br) LM555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM 555CM CU SN Level-1-NA-UNLIM 0 to 70 LM 555CN MC1455P1 OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 LM 555CN NE555V OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 LM 555CN (4/5) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples

117 PACKAGE OPTION ADDENDUM 27-Jul-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

118 PACKAGE MATERIALS INFORMATION 21-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant LM555CMM VSSOP DGK Q1 LM555CMM/NOPB VSSOP DGK Q1 LM555CMMX/NOPB VSSOP DGK Q1 LM555CMX SOIC D Q1 LM555CMX/NOPB SOIC D Q1 Pack Materials-Page 1

119 PACKAGE MATERIALS INFORMATION 21-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM555CMM VSSOP DGK LM555CMM/NOPB VSSOP DGK LM555CMMX/NOPB VSSOP DGK LM555CMX SOIC D LM555CMX/NOPB SOIC D Pack Materials-Page 2

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124 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as components ) are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS Products Applications Audio Automotive and Transportation Amplifiers amplifier.ti.com Communications and Telecom Data Converters dataconverter.ti.com Computers and Peripherals DLP Products Consumer Electronics DSP dsp.ti.com Energy and Lighting Clocks and Timers Industrial Interface interface.ti.com Medical Logic logic.ti.com Security Power Mgmt power.ti.com Space, Avionics and Defense Microcontrollers microcontroller.ti.com Video and Imaging RFID OMAP Applications Processors TI E2E Community e2e.ti.com Wireless Connectivity Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 2016, Texas Instruments Incorporated

125 1 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 LM565/LM565C Phase Locked Loop Check for Samples: LM565, LM565C 1FEATURES DESCRIPTION ppm/ C Frequency Stability of the VCO The LM565 and LM565C are general purpose phase locked loops containing a stable, highly linear voltage PowerSupplyRangeof±5to±12Voltswith controlled oscillator for low distortion FM 100 ppm/% Typical demodulation, and a double balanced phase detector 0.2% Linearity of Demodulated Output with good carrier suppression. The VCO frequency is LinearTriangleWavewithinPhaseZero set with an external resistor and capacitor, and a Crossings Available tuning range of 10:1 can be obtained with the same capacitor. The characteristics of the closed loop TTL and DTL Compatible Phase Detector Input system bandwidth, response speed, capture and and Square Wave Output pull in range may be adjusted over a wide range AdjustableHoldinRangefrom±1%to>±60% with an external resistor and capacitor. The loop may be broken between the VCO and the phase detector APPLICATIONS for insertion of a digital frequency divider to obtain frequency multiplication. Data and Tape Zynchronization The LM565H is specified for operation over the Modems 55 C to +125 C military temperature range. The FSK Demodulation LM565CN is specified for operation over the 0 C to FM Demodulation +70 C temperature range. Frequency Synthesizer Tone Decoding Frequency Multiplication and Division SCA Demodulators Telemetry Receivers Signal Regeneration Coherent Demodulators Connection Diagram TO-100 Package See Package Number LME Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright , Texas Instruments Incorporated

126 LM565, LM565C OBSOLETE SNOSBU1B MAY 1999 REVISED APRIL Dual-in-Line Package PDIP See Package Number NFF These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM565 LM565C

127 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 AbsoluteMaximumRatings (1)(2) Supply Voltage ±12V PowerDissipation (3) 1400mW Differential Input Voltage ±1V OperatingTemperatureRange LM565H 55 Cto+125 C StorageTemperatureRange LM565CN 0 C to +70 C 65 Cto+150 C Lead Temperature(Soldering, 10 sec.) 260 C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) The maximum junction temperature of the LM565 and LM565C is +150 C. For operation at elevated temperatures, devices in the TO-5 package must be derated based on a thermal resistance of +150 C/W junction to ambient or +45 C/W junction to case. Thermal resistance of the dual-in-line package is +85 C/W. Electrical Characteristics ACTestCircuit,T A =25 C,V CC =±6V LM565 LM565C Parameter Conditions Units Min Typ Max Min Typ Max Power Supply Current ma InputImpedance(Pins2,3) 4V<V 2,V 3 <0V k VCOMaximumOperatingFrequency C o =2.7pF khz VCOFree-RunningFrequency Operating Frequency Temperature Coefficient Frequency Drift with Supply Voltage C o =1.5nF R o =20k % f o =10kHz ppm/ C %/V TriangleWaveOutputVoltage V p-p Triangle Wave Output Linearity % SquareWaveOutputLevel V p-p OutputImpedance(Pin4) 5 5 k Square Wave Duty Cycle % Square Wave Rise Time ns Square Wave Fall Time ns Output Current Sink(Pin 4) ma VCOSensitivity f o =10kHz Hz/V DemodulatedOutputVoltage(Pin7) ±10%FrequencyDeviation mv p-p Total Harmonic Distortion ±10% Frequency Deviation % OutputImpedance(Pin7) k DC Level(Pin 7) V Output Offset Voltage V 7 V mv TemperatureDriftof V 7 V V/ C AM Rejection db PhaseDetectorSensitivityK D V/radian Copyright , Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM565 LM565C

128 LM565, LM565C OBSOLETE SNOSBU1B MAY 1999 REVISED APRIL Typical Performance Characteristics Power Supply Current as a Function of Supply Voltage Lock Range as a Function of Input Voltage Figure 1. Figure 2. VCO Frequency Oscillator Output Waveforms Figure 3. Figure 4. Phase Shift vs Frequency VCO Frequency as a Function of Temperature Figure 5. Figure 6. 4 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM565 LM565C

129 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 Typical Performance Characteristics(continued) Loop Gain vs Load HoldinRangeasa Resistance FunctionofR 6 7 Figure 7. Figure 8. Copyright , Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM565 LM565C

130 LM565, LM565C OBSOLETE SNOSBU1B MAY 1999 REVISED APRIL Schematic Diagram Figure 9. Schematic Diagram 6 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM565 LM565C

131 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 AC Test Circuit Note:S 1 openforoutputoffsetvoltage(v 7 V 6 )measurement. Figure 10. AC Test Circuit Copyright , Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM565 LM565C

132 LM565, LM565C OBSOLETE SNOSBU1B MAY 1999 REVISED APRIL Typical Applications Figure Hz Synchronous AM Demodulator 8 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM565 LM565C

133 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 Figure 12. FSK Demodulator( cps) Figure 13. FSK Demodulator with DC Restoration Copyright , Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM565 LM565C

134 LM565, LM565C OBSOLETE SNOSBU1B MAY 1999 REVISED APRIL Figure 14. Frequency Multiplier( 10) Figure 15. IRIG Channel 13 Demodulator 10 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM565 LM565C

135 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 APPLICATIONS INFORMATION In designing with phase locked loops such as the LM565, the important parameters of interest are: FREE RUNNING FREQUENCY LOOPGAIN:relatestheamountofphasechangebetweentheinputsignalandtheVCOsignalforashiftininput signal frequency(assuming the loop remains in lock). In servo theory, this is called the velocity error coefficient. (1) TheloopgainoftheLM565isdependentonsupplyvoltage,andmaybefoundfrom: (2) f o =VCOfrequencyinHz V c =totalsupplyvoltagetocircuit Loopgainmaybereducedbyconnectingaresistorbetweenpins6and7;thisreducestheloadimpedanceon the output amplifier and hence the loop gain. HOLD IN RANGE: the range of frequencies that the loop will remain in lock after initially being locked. (3) where f o =freerunningfrequencyofvco V c =totalsupplyvoltagetothecircuit (4) THE LOOP FILTER In almost all applications, it will be desirable to filter the signal at the output of the phase detector (pin 7); this filtermaytakeoneoftwoforms: Figure 16. Simple Lead Filter Figure 17. Lag-Lead Filter Copyright , Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LM565 LM565C

136 LM565, LM565C OBSOLETE SNOSBU1B MAY 1999 REVISED APRIL A simple lag filter may be used for wide closed loop bandwidth applications such as modulation following where the frequency deviation of the carrier is fairly high (greater than 10%), or where wideband modulating signals must be followed. The natural bandwidth of the closed loop response may be found from: Associated with this is a damping factor: (5) For narrow band applications where a narrow noise bandwidth is desired, such as applications involving tracking aslowlyvaryingcarrier,aleadlagfiltershouldbeused.ingeneral,if1/r 1 C 1 <K o K D,thedampingfactorforthe loop becomes quite small resulting in large overshoot and possible instability in the transient response of the loop.inthiscase,thenaturalfrequencyoftheloopmaybefoundfrom (6) R 2 isselectedtoproduceadesireddampingfactor,usuallybetween0.5and1.0.thedampingfactorisfound from the approximation: 2 f n (8) These two equations are plotted for convenience. (7) Figure 18. Filter Time Constant vs Natural Frequency Figure 19. Damping Time Constant vs Natural Frequency CapacitorC 2 shouldbemuchsmallerthanc 1 sinceitsfunctionistoprovidefilteringofcarrier.ingeneralc 2 0.1C Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: LM565 LM565C

137 OBSOLETE LM565, LM565C SNOSBU1B MAY 1999 REVISED APRIL 2013 REVISION HISTORY Changes from Revision A(April 2013) to Revision B Page ChangedlayoutofNationalDataSheettoTIformat Copyright , Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM565 LM565C

138 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries(ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products(also referred to herein as components ) are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the thirdparty,oralicensefromtiunderthepatentsorotherintellectualpropertyofti. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components whichhavenotbeensodesignatedissolelyatthebuyer'srisk,andthatbuyerissolelyresponsibleforcompliancewithalllegaland regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS Products Applications Audio Automotive and Transportation Amplifiers amplifier.ti.com Communications and Telecom Data Converters dataconverter.ti.com Computers and Peripherals DLP Products Consumer Electronics DSP dsp.ti.com Energy and Lighting Clocks and Timers Industrial Interface interface.ti.com Medical Logic logic.ti.com Security Power Mgmt power.ti.com Space, Avionics and Defense Microcontrollers microcontroller.ti.com Video and Imaging RFID OMAP Applications Processors TI E2E Community e2e.ti.com Wireless Connectivity Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 2013, Texas Instruments Incorporated

139 MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications. See ON Semiconductor Application Note AN531 for additional design information. Features Excellent Carrier Suppression 65 db 0.5 MHz 50 db 10 MHz Adjustable Gain and Signal Handling Balanced Inputs and Outputs High Common Mode Rejection 85 db Typical This Device Contains 8 Active Transistors PbFree Package is Available* SOIC14 D SUFFIX CASE 751A PDIP14 P SUFFIX CASE 646 PIN CONNECTIONS Signal Input 1 Gain Adjust 2 Gain Adjust 3 Signal Input 4 Bias 5 Output 6 N/C V EE N/C Output N/C Carrier Input N/C Input Carrier ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. Semiconductor Components Industries, LLC, 2006 October, 2006 Rev Publication Order Number: MC1496/D