Advanced. 4 Channel Charge Pump White LED Driver C1P C1N C2P C2N V IN 6 V OUT SP6687 GND. Typical Application Circuit for 4-White LEDs

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1 Advanced Channel Charge Pump White LD Driver FATURS High fficiency > 90% Support up to White LDs with current matching Three Charge Pump Modes: X, X., X2 Soft Start Function Short Circuit Protection Output Overvoltage Protection Thermal Shutdown Programmable LD drive capability PWM Dimming Control MHz Fixed Frequency Oscillator Low µa Shutdown Current Pin Compatible with SC0 Now Available in Lead Free Packaging APPLICATIS Mobile phones White LD Backlighting Camera Flash LD lighting DSCRIPTI The is a compact, highly efficient and highly integrated channel charge pump white LD driver. It can support from to White LDs and is optimized for Li-Ion battery applications. Current matching allows all LDs to maintain consistent brightness. Users can control White LDs by three programming bits. ach channel can support up to 30mA of current. This device is available in a mm x mm, pin QFN package. TYPICAL APPLICATI CIRCUIT LD LD 3 Pin Orientation C2P C2N Pin QFN 2 3 CN 8 CP VOUT IST C µf C2 µf Li-ion Battery C IN µf 2 CP CN C2P C2N V IN V OUT LD C OUT µf 3 I ST 3 LD R ST 2 Typical Application Circuit for -White LDs

2 Input Voltage to V Output Voltage to V Power Dissipation, P T A = 2ºC QFN-L x...2.w Package Thermal Resistance QFN-L x, O JA...0ºC/W ABSOLUT MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. xposure to absolute maximum rating conditions for extended periods of time may affect reliability. Junction Temperature Range...-0ºC to 2ºC Storage Temperature... -ºC to 0 C Operating Temperature C to 8 C SD Susceptibility Human Body Model...2kV Machine Mode...200V LCTRICAL CHARACTRISTICS Unless otherwise specified: V IN = 2.8V to.v, C = C2 =.0µF (SR = 0.03Ω, T A = 2 C) PARAMTR MIN TYP MAX UNITS CDITIS Input Supply Voltage 2.. V Under Voltage Lockout Threshold V Rising Under Voltage Lockout Hysteresis 0 mv ma R ST = 2.0kΩ Current into LDs, 2, 3, and.. ma R ST = 9.0kΩ 2 20 ma 2.V < <.V 2 30 ma 3.V < <.V Quiescent Current 3 ma F OSC = MHz, IOUT = 0mA Quiescent Current in Shutdown 0 µa =.V, n Pin = ZeroV ILDAccuracy (Note ) 2. % 2mA < ILD < 30mA Current Matching (Note 2) % 2mA < ILD < 30mA x mode to.x mode Transition Voltage (V IN Falling).x mode to 2x mode Transition Voltage (V IN Falling) V V VLD = 3.V, IOUT = 80mA ILD = I =I = ILD = 20mA VLD = 3.V, I OUT = 80mA ILD = I = I = ILD = 20mA Oscillator Frequency MHz Input Current Limit ma Output Over Voltage Protection. V Short Circuit applied from VOUT to Open circuit at any LD that is programmed to be in the state 2

3 LCTRICAL CHARACTRISTICS Unless otherwise specified: V IN = 2.8V to.v, C = C2 =.0µF (SR = 0.03Ω, T A = 2 C) PARAMTR MIN TYP MAX UNITS CDITIS Input High Threshold. V Input Low Threshold 0. V Input High Logic threshold (,,, ) Input Low Logic threshold (,,, ) Input High Current µ A V IH = V IN Input Low Current µ A V IL Thermal Shutdown Threshold º C Thermal Shutdown Hysteresis 0 º C = Note : I LD(RR) = I LD(MA) - I LD(ST) I LD(ST) X 00% Note 2: Current Matching refers to the difference in current from one LD to the next. (I LD Current Matching I LD(MAX) - I LD(MIN) I LD(MAX) + I LD(MIN) X 00%) FUNCTIAL DIAGRAM CP CN C2P C2N V IN x/.x/2x Charge Pump MHz MHz Oscillator VOUT Mode Decision I-Setting IST IST LD Bandgap VRF IST LD Decoder 30mV 3

4 PIN DSCRIPTI PIN # PIN NAM DSCRIPTI N Chip nable (Active High) 2 C TRL0 Output Control Bit 0 (See table ) 3 C TRL Output Control Bit (See table ) C TRL2 Output Control Bit 2 (See table ) IST V UT V IN 8 P LD current is set by the value of the resistor RS to ground. Do not short the I pin. Voltage for I ST T connected from the I is typically.v. S T O Output Voltage Source for connection to the LD anodes. Power Input Voltage C Positive Terminal of Bucket Capacitor 9 CN Negative Terminal of Bucket Capacitor 0 C2N Negative Terminal of Bucket Capacitor 2 C2P Positive Terminal of Bucket Capacitor 2 ST pin 2 3 to LD to xposed Pad Ground Current Sink for connected to V LD. (If not in use, pin may be left open, grounded, or ) I N xposed pad should be soldered to PCB board and connected to C2P C2N CN LD 3 8 CP VOUT LD IST 2 3 Pin Orientation TOP VIW

5 The is a high efficiency charge pump white LD driver. It provides channels of low drop-out voltage current source to regulate the current for white LDs. For high efficiency, the implements 3 modes of charge pump: x/x./x2 modes. An external R ST is used to set the current level of the White LDs. has an input current regulation circuit to reduce the input ripple. Soft Start The includes a soft start circuit to limit the inrush current at power on and mode switching. The soft start circuit holds the input current level long enough for output capacitor C OUT to reach a desired voltage level. When the soft start turns off, the will not sink current spiking from V IN. Mode Decision The uses a smart mode decision method to select the working mode for maximum efficiency. The mode decision circuit senses the output and LD voltage for up/down selection. Dimming Control, and are used to control the on/off of correlated White LDs. When an external PWM signal is connected to the control pin, the brightness of the white LDs is adjusted by the duty cycle. LD Current Setting The current flowing through White LDs connected to the can be set by R ST. very current that flows through each respective White LD is 0 times greater than the current of R ST. The white LD current can be estimated by following equation: THORY OF OPRATI where V IST =.V, and R ST is the resistance connected from I ST to. I LD =0x ( V IST R ST ) Thermal Shutdown The provides a high current capability to drive white LDs. A thermal shutdown circuit is needed to protect the chip from thermal damage. When the chip reaches the shutdown temperature of 0ºC, the thermal shutdown circuit turns off the chip to prevent thermal accumulation in the chip. Overvoltage Protection regulates the output voltage by controlling the input current. When the output voltage reaches the designated level, reduces the input current. Subsequently, the output voltage regulation also serves as an overvoltage protection circuit. Short Circuit Protection A current limiting circuit is also included in the for short circuit protection. Whenever the output sources a dangerously high current, the current limiting circuit takes over the output regulation circuit and reduces the output current to an acceptable level. APPLICATI INFORMATI C µf C2 µf Li-ion Battery C IN µf CP CN C2P C2N V IN V OUT LD C OUT µf 3 I ST LD 3 R ST 2 Typical Application Circuit For 3-White LDs

6 V APPLICATI INFORMATI C µf C2 µf Li-ion Battery CP CN C2P C2N V IN OUT C IN µf C OUT 2 LD µf 3 I ST LD 3 R ST 2 Typical Application Circuit for 2-White LDs Control Inputs Output Status LD LD Table. Typical application circuit for PWM dimming using a DC voltage into I ST.

7 APPLICATI INFORMATI Selecting Capacitors To get better performance from the, the selection of appropriate capacitors is very important. These capacitors determine some parameters such as input and output ripple, power efficiency, maximum supply current by the charge pump and start up time. To reduce the input and output ripple effectively, low SR ceramic capacitors are recommended. Generally to reduce output ripple, increasing the output capacitance C OUT is necessary. However, this will increase the startup time of the output voltage. For LD driver applications, the input voltage ripple is more important than output ripple. Input ripple is controlled by the input capacitor C IN -- increasing the value of input capacitance can further reduce the ripple. Practically, the input voltage ripple depends on the impedance of the power supply. If a single input capacitor C IN cannot satisfy the requirement of the application, it is necessary to add a low-pass filter. Figure shows a C- R-C filter used on the. The input ripple can be reduced to less than 30mVp-p when driving 80mA of output current. Figure 2 shows the typical value of R ST versus average LD current and Table 2 shows the values of R ST for a fixed LD current. RST Value (k_) Ω Typical Curve for RST vs. Avg. LD Current LD Current (ma) Figure 2. The typical curve of R ST vs. LDs average current. ILD (ma) R T Nearest Standard ( ks Ω ) Value for RST (kω ) V IN.0Ω V IN µF 2.2µF Figure. C-R-C filter used to reduce input ripple. The flying capacitors C and C 2 determine the supply current capability of the charge pump and influence the overall efficiency of the system. Lower values will improve efficiency, but will limit the current to the LDs at low input voltages. For X 20mA load over the entire input range of 2. to.v, a capacitor of µf is optimal. Setting the LD Current The can be set to a fixed LD current by a resistor R ST connected from I ST to. R ST establishes the reference current and mirrors the current into LD,,, and LD. The current into each LD is about 0 times the current that flows through R ST. The approximate setting formula is given as follows: Table 2. R ST Value Selection If maximum accuracy is required, a precision resistor is needed. The following equation shows how to calculate the error: I LD(RR) = I LD(MAS) - I LD(ST) I LD(ST) X 00% Where I LD(MAS) is practical measured LD current and I LD(ST) is the LD current which is determined by R ST. I LD = 8(V) R ST (Ω)

8 APPLICATI INFORMATI LD Current Setting with NMOS LD current setting control can also be achieved by using an external NMOS transistor to change the equivalent resistor of the I ST pin. Figure 3 illustrates this application circuit which has 3 bit signals and can set 8 different levels of LD current. Table 3 shows the relation between the equivalent resistor of the I ST pin and the respective control signal. IST R R R2 S LD Dimming Control Methods The uses two methods to achieve LD dimming control. These methods are detailed below. PWM Dimming The first dimming method utilizes a PWM control signal into,, and. Table shows the relation between CTRLx and the LD current states. For example, when and are at logic high and receives a PWM signal then LDs will be dimmed simultaneously. The average LD current can be derived by using a known PWM signal value. When the PWM signal logic is low the current can be set at a fixed value with the R ST resistor. The following equation will give the approximate value of the LD current: S2 I LD(AVG) = T X I LD() T PWM Figure 3. Typical application circuit for setting LD current using an NMOS transistor to set R ST R3 S3 Where T PWM is the period of the PWM dimming signal. T is the time of the PWM signal at low. I is LD on LD() state current. S S2 S3 quivalent Resister of I R ( ) S T S T pin R S T R = 0 0 R S T = R 3 / R / 0 0 R S T = R 2 / R / 0 R S T = R 2 // R 3 / PWM LD LD 0 0 R S T = R / R / 0 R S T = R // R 3 / 0 R S T = R // R 2 / R S T = R // R 2 3 / Figure. Typical application circuit for PWM dimming when driving LDs. Table 3. Control signal and equivalent resistor of the I ST pin. PWM LD LD 8 Figure. Typical application circuit for PWM dimming when driving 3 LDs.

9 APPLICATI INFORMATI Dimming using a DC voltage added to I ST PWM LD LD Using an analog input voltage V ADJ via a resistor R ADJ that connects to the I ST pin is another method for dimming control of LDs. Figure shows the application circuit. For this application the LD current can be derived from the following equation: I LD = 0 X [. x (/R ST + /R ADJ ) - V ADJ /R ADJ ] Figure. Typical application circuit for PWM dimming when driving 2 LDs. Due to the 00µs delay time between mode transfers, the duty cycle of the dimming frequency should not exceed the maximum duty cycle on the CTRLx pins. For best performance it is recommended to keep the dimming frequency between 200Hz and khz. When the duty cycle is exceeded, the cannot transfer modes properly. The following equation shows the relation between maximum duty of the CTRLx pins and the PWM dimming frequency: D MAX =(-00 x0 - x F D ) IST VADJ RADJ RST Where D MAX is the Maximum Duty of CTRLX and F D is the PWM Dimming Frequency. Figure. Typical application circuit for PWM dimming using a DC voltage into I ST. Dimming Frequency (Hz) CTRLX Maximum Duty ILD Minimum Duty K VADJ 2.V.V 0.8V 0V Table. Dimming frequency relative to Min/Max duty. ILD 0mA.mA 3mA 20mA Figure 8. dimming control application using a DC voltage into I ST. Figure 8 shows the relation between V ADJ and I LD of a typical application example, with V ADJ from 0 to 2.V, RST = 3k Ohms and R ADJ = kohms. 9

10 PACKAG: PIN QFN D2 D NX L 2 e NX b NX K X غ A SATING PLAN A A2 A3 Pin QFN JDC MO-220 VGGC- Variation SYMBOL MIN NOM MAX A A A A3 D.00 BSC D L K b e 0. BSC Note: Dimensions in (mm) Controlling Dimension 0.20 RF.00 BSC Pin QFN JDC MO-220 VGGC- Variation SYMBOL MIN NOM MAX A A A A3 D RF 0. BSC D L K b e 0.02 BSC Note: Dimensions in (inches) Conversion Factor: Inch = 2.0 mm 0

11 ORDRING INFORMATI Part Number Operating Temperature Range Package Type R-L/TR C to +8 C... Pin mmxmm QFN Available in lead free packaging only. -L = lead free /TR = Tape and Reel Pack quantity is 2,00 for QFN. Corporation ANALOG XCLLC Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 903 TL: (08) FAX: (08) Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.