Diagnostics and Prognostics Method for Analog Electronic Circuits

Transcription

1 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX Diagnostics and Prognostics Method for Analog Electronic Circuits Arvind Sai Sarathi Vasan, Student Member, IEEE, Bing Long, and Michael Pecht, Fellow, IEEE Abstract Analog circuits play a vital role in ensuring the availability of industrial systems. Unexpected circuit failures in such systems during field operation can have severe implications. To address this concern, we developed a method for detecting faulty circuit condition, isolating fault locations and predicting the remaining useful performance of analog circuits. Through successive refinement of circuit s response to a sweep signal, features are extracted for fault diagnosis. The fault diagnostics problem is posed and solved as a pattern recognition problem using kernel methods. From the extracted features, a fault indicator is developed for failure prognosis. Further, an empirical model is developed based on the degradation trend exhibited by the fault indicator. A particle filtering approach is used for model adaptation and remaining useful performance estimation. This method is completely automated and has the merit of implementation simplicity. Case studies on two analog filter circuits demonstrating this method are presented. Index Terms Analog circuits, least squares support vector machines, parametric faults, particle filters. A I. INTRODUCTION NALOG CIRCUITS are used in industrial systems for implementing controllers [1], conditioning signals [2], protecting critical modules [3], [4], and more [5]. The occurrence of circuit failures during field operation can affect system functionality and the cost of failure can be enormous [6], [7]. In most cases, these failures can be related to a fault in a system s analog circuitries, where fault refers to a drift in the value of a circuit component from its nominal value, which leads to a failure of the whole circuit. These faults could either be catastrophic (open and short circuit) or parametric (fractional deviation in circuit components from their nominal values) [8]. For example, the degradation of electrolytic capacitors in LC filters will cause the switching-mode power converters to fail [9]. An increase in the parametric resistance Manuscript received March 5, 2012; revised June 16, 2012; accepted September 3, The authors would like to thank the more than 100 companies that support research activities at the Center for Advanced Life Cycle Engineering, University of Maryland annually. Copyright 2009 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org. S. Arvind and M. Pecht are with the Center for Advanced Life Cycle Engineering, University of Maryland, College Park, MD USA (phone: ; fax: ; arvind88@calce.umd.edu and pecht@calce.umd.edu). M. Pecht is also with the Prognostics and Health Management Center, City University of Hong Kong, Hong Kong. B. Long is with the School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu , China. ( longbing@uestc.edu.cn). offered by the components within filter circuits due to the degradation of solder joints will affect the frequency band being filtered out [10]. Prevention of circuit failures during field operation requires methods for the (1) early detection and isolation of faults and (2) prediction of remaining useful performance (RUP) of the failing circuit [11]. Here, RUP refers to the remaining time that the circuit performance guarantees system operation. In the past, there have been many reports on prognostics and system health management (PHM) techniques for individual components of an analog circuit. For example, Chen et al. [9] proposed an online failure prediction method for electrolytic capacitors in a LC filter of a switching-mode power converter. Alam et al. [12] proposed model-based and data driven prognostics methods for predicting the failure time for embedded planar capacitors. Kwon et al. [13] proposed a probabilistic approach for predicting the failure of interconnects. Though there are PHM strategies for predicting the failure of individual components, it becomes impractical to implement a PHM system for each and every component in a complex system. It is desirable to have a cost-effective expert system for the PHM of electronic circuits at the system-level, so that maintenance decisions can be made on a conditional basis and maintenance personnel can be given ample forewarning before a circuit failure occurs. Most of the related research for analog circuits has aimed at diagnosing faults in circuits during the manufacturing process. These approaches do not address the fault diagnostics problem from a field operation (real-time) perspective. Hence, they suffer from shortcomings (listed in Section II) which limit their implementation in on-board applications. Further, no method has been suggested for predicting the remaining time until circuit failure. System-level prognostic techniques have been successfully implemented for other applications [14] [19]. However, it is not clear how these techniques can be extended to perform RUP estimation for analog circuits. In this paper, a new diagnostics and prognostics method for analog circuits is proposed, aiming at in-circuit real-time fault detection, isolation, and RUP estimation. A kernel-based machine learning (ML) approach is employed for the early detection and isolation of faults, where early fault detection refers to the detection of component variations just outside their tolerance range. For failure prognosis, a fault indicator (FI) reflecting the evolution of a fault in any of the circuit s critical component is developed. Then a model adaptation scheme using particle filters (PFs) is devised for tracking the evolution of the FI and predicting the circuit s RUP.

2 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX This paper is organized as follows. Section II presents a survey of the literature pertaining to fault diagnostics and failure prognostics of analog circuits. Section III briefly describes our multistage PHM framework. Here, we also describe our approach for extracting features and constructing the FI. Section IV provides the theoretical background on a kernel-based fault classifier and the PF approach used in the proposed PHM framework for fault diagnostics and RUP estimation respectively. Section V presents the performance results of the proposed PHM framework on two filter circuits. Concluding remarks and possible directions for future work are presented in Section VI. II. LITERATURE REVIEW Fault diagnostics and failure prognostics in analog circuits are made challenging by the presence of component tolerances, the complex nature of the fault mechanisms, and the effects of the operational and environmental stresses [20]. Traditionally, analog circuit fault diagnosis has been carried out using simulation-after-test (SAT) or simulation-before-test (SBT) strategies [6], [21] [23]. In the SAT approach, fault detection is based on the derived circuit transfer function equations, and fault isolation is realized by estimating the circuit parameters from the circuit s response to a test stimulus [24] [30]. This technique is time-consuming and suffers from drawbacks associated with the parameter estimation procedure when dealing with complex nonlinear circuits. Many SBT diagnostic methods have been proposed in the past. These are either based on derived circuit equations at selected nodes [31] [33] or on the ML approach [34] [45]. Fault diagnosis based on circuit equations is not suitable for nonlinear analog circuits and is limited in application due to the poor accessibility to internal nodes of integrated circuits (ICs) [46]. ML-based SBT approaches typically provide faster results compared to SAT approaches during the diagnostics phase [23]. This makes an ML-based approach appealing for online fault diagnostics. Spina and Upadhyaya [35] used a backward error propagation (BEP) neural network (NN) for analog circuit fault diagnosis. In [35], features extracted from the circuit s response to white noise were used as input to the NN without any data preprocessing. This resulted in an NN with a large architecture. Later, Aminian and Aminian [36] [38] improved the NN approach using data preprocessing techniques such as wavelet decomposition and principal component analysis (PCA). Other efforts in NN-based fault diagnosis include the use of kurtosis and entropy [39], kernel PCA [40], multi-resolution decomposition [42], and L 1 -norm optimization [43] as preprocessors for improving performance. In recent years, researchers have also used support vector machines (SVMs) instead of a NN for fault detection and isolation in analog circuits [44], [45], [47], [48]. Although several fault diagnostic approaches for analog circuits have been reported in the literature, no work has been done on prognostics for analog circuits. Even among the preferred ML-based fault diagnostics methods there are shortcomings that confine their implementation in real-time applications. In these methods, features are extracted from the circuit s response to an impulse signal. Though this allows the extraction of a circuit s frequency response directly from its output, in order to capture the circuit s output, a high sampling rate and expensive data acquisition equipment are required, irrespective of the bandwidth of the circuit [37]. Further, these ML-based SBT approaches are tested and trained using data collected from only one fault value under each fault class or condition. In practice, it is common to encounter fault values that are not seen during training. The diagnosability of these ML-based SBT approaches in such scenarios is still unknown. By diagnosability, we mean the ability to detect faulty conditions and isolate fault locations [27]. To solve these problems, a new diagnostics and prognostics method for analog circuits is proposed. The contributions of this paper are summarized as follows. First, a new feature extraction method is proposed to enable real time testing of analog circuits. Second, a systematic process was established for constructing an FI for circuit prognostics. Finally, a degradation model and model adaptation scheme have been furnished to assess the RUP of analog circuits. Together, these contributions will allow systems to autonomously assess their analog circuitries during field operation. III. PHM FRAMEWORK Developing PHM strategies for analog circuits is a challenging task due to the unavailability of fault models [37]. This makes the application of data-driven techniques appealing, because they do not require knowledge of material properties, structures, or failure mechanisms. Here, we focus on the development of a PHM framework that can be built onboard as an in-circuit testing strategy. An overview of our proposed data-driven PHM method for analog circuits is schematically represented in Fig. 1. The proposed approach involves two phases: training and testing. During the training phase, frequently occurring faults are investigated to identify faults of interest. The circuit under test (CUT) is then replicated for these hypothesized fault conditions and excited by a test stimulus to extract features that are stored in a fault dictionary for use during the online detection of faults. From the extracted features, an FI is built whose trend is identified under different fault conditions. Anomaly and failure thresholds are identified for the FI during the training mode. In the testing mode, the FI is calculated from the most recently extracted features. When the FI crosses the anomaly threshold, the prognostics algorithm is triggered, which estimates the RUP as a probability density function (PDF). Simultaneously, the fault detection and isolation algorithm is triggered, where the features extracted and normalized are compared with those stored in the fault dictionary. This comparison is performed using a kernel-based classifier that has been previously trained. The output of the classifier indicates whether the circuit is faulty or not. If the circuit is faulty, the classifier also identifies the faulty component. Thus, the proposed solution presents a single tool for fault detection, isolation, and prognosis, thereby eliminating the

3 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX Test Signal Generator CUT Feature Extraction of Noisy Signals Feature Normalization Fault Indicator Calculation Anomaly Detection Historical Data Fault Classification Failure Threshold Model Adaptation Anomaly Threshold Fault Detection and Isolation Estimated Fault Type Failure Prediction RUP Prediction Fig. 1. Overview of the proposed diagnostics and prognostics framework for analog electronic circuits. need to develop each separately. The following subsections describe the steps involved in our proposed multistage process. A. Test Signal Generator For analog circuits, the behavioral characteristics are assumed to be embedded in the time and frequency response. Hence, a test signal must be chosen such that this response can be generated and captured. Most of the aforementioned MLbased diagnostic methods use a short pulse (typically 10µs) as a test signal. This is done to obtain the impulse response of the CUT. However, this method can drive a circuit into a nonlinear region of operation. Hence, Spina and Upadhyaya [35] suggested the combination of a pseudorandom number and a digital-to-analog converter as a test signal generator. With this test signal generator, a high sampling rate and expensive data acquisition equipment are required to capture the CUT s response, irrespective of the bandwidth of the CUT. Researchers have also suggested using a series of sinusoids and then extracting features from the frequency domain of the measured CUT response [39]. But performing analysis in the frequency domain is computationally intensive [35]. Fig. 2. Illustration of a sweep (test) signal. In our work, a sweep signal containing a frequency bandwidth larger than that of the CUT is used as the test signal. This ensures that the CUT is excited by all the frequency components to which it is sensitive. Also, this method allows us to acquire data at a sampling rate that depends on the CUT s bandwidth. Simple and cost-effective digital forms of a sweep signal generator have been implemented with TTL logic [49], [50] and thus can be incorporated on-board for testing purposes. A realistic sweep signal waveform is shown in Fig. 2. B. Feature Extraction 1) Wavelet Features: Fourier transformation is commonly used for extracting information embedded in a signal. However, Fourier transformation is suitable only for the analysis of stationary signals. A change in time domain of a non-stationary signal spreads over the entire frequency domain. This change in time domain will not be detected through Fourier transformation [51]. Hence, Fourier transformation alone is not useful for fault diagnosis, as the signals to be analyzed contain time-varying frequencies. In contrast, wavelet analysis can reveal signal aspects such as trends, break points, and discontinuities. Hence, we chose wavelet features for fault diagnosis in analog circuits. In wavelet analysis, the signal s correlation with families of functions that are generated based on the shifted and scaled version of a mother wavelet is calculated and used to map the signal of interest to a set of wavelet coefficients that vary continuously over time [52]. The discrete version of the wavelet transform contains sampled versions of the scaled and shifted parameters, but not the signal or the transform. This makes the time resolution good at high frequencies, and the frequency resolution becomes good at low frequencies. In practice, the measured signal inherently contains noise. If noise is not removed from the signal, then the noise energy will be distributed across the wavelet coefficients. This can lead to misclassification during fault diagnosis. Johnstone and Silverman [53] showed that noise removal can be executed by minimizing the noise in the detail coefficients. This is done through wavelet decomposition followed by level-dependent thresholding over the computed wavelet coefficients. The steps involved in soft level-dependent thresholding are outlined below [54], [55]: 1. Compute the wavelet coefficients using the discrete wavelet transform. 2. Estimate the noise variance at each decomposition level using the following relation:

4 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX ( ). (1) where, denotes the median. 3. Compute the threshold at each decomposition level using the following relation:. (2) 4. The soft level-dependent thresholding is performed with the function { ( ) where, denotes the detail coefficient at the level of decomposition. In our work, through discrete wavelet transformation, we decompose the response of the CUT stimulated by a sweep signal into the approximation and detail signals using multirate filter banks [56]. Then, we remove noise from the detailed coefficients using the classical wavelet denoising procedure outlined above. The information contained in the circuit s response is represented using features extracted by computing the energy contained in the detail coefficients (with noise removed) at various levels of decomposition [47]. This is expressed as follows: (3) (4) where denotes the energy in the detail coefficient at the level of decomposition. 2) Statistical Features: The second set of features extracted includes the kurtosis and entropy of the CUT s response. Kurtosis is a statistical property which is defined as the standardized fourth moment about the mean. It provides a measure of the heaviness of the tails in the PDF of a signal, which is related to the abrupt changes in the signal having high values and appearing in the tails of the distribution [57]. Kurtosis is mathematically described as follows: [ [ ]] [ [ [ ]] ]. (5) On the other hand, entropy provides a measure of the information capacity of a signal, which denotes the uncertainty associated with the selection of an event from a set of possible events whose probabilities of occurrences are known [56], [57]. It is defined for a discrete-time signal as: (6) where, are the possible values of, and are the associated probabilities. C. Feature Scaling The goal of the feature extractor is to characterize a circuit s fault condition such that the feature vector values remains: 1) similar for all of the circuit topology belonging to the same fault condition and 2) different for circuit topologies under different fault conditions. This demands the feature elements to be invariant with respect to scale. Hence, once the features are extracted, we scale the features for the purpose of enhancing the inputs to the fault classifier. Feature scaling helps in avoiding issues due to unexpected changes in the dynamic ranges of the feature elements [36], [60]. In our investigation, scaling the feature vector that was extracted using wavelet decomposition to have a zero mean and unit standard deviation resulted in efficient classification. D. Fault Indicator When implementing prognostics at the component level, usually a fault indicator (FI) parameter is identified to monitor the degradation of the component in real time. This parameter (e.g., the ON state of an IGBT [61] and the RF impedance for interconnects [13]) is chosen based on an understanding of the degradation process [9]. For a complex system, multiple parameters corresponding to all the critical components/sub-systems need to be monitored and processed in real time to perform prognostics. This is not possible in applications such as analog circuits, where there is a constraint on the available resources. In order to address this challenge, we have developed a method to construct an FI to represent circuit degradation. Here, circuit degradation refers to the degradation in any of a circuit s critical components which leads to the deviation of the component s value from its nominal value. The procedure for calculating the FI is based on the well-known Mahalanobis Taguchi (MT) methodology [62], [63]. The FI calculation starts with the collection of the two feature sets (wavelet and statistical features) under a no-fault condition (circuit components are allowed to vary within their standard tolerance range). For both feature sets, two individual Mahalanobis spaces (MSs) are constructed using their normalized feature elements and correlation coefficients. Let { } and { } denote the wavelet and statistical features respectively, where denotes the energy of the detail coefficients at the decomposition level, is the number of decomposition levels, and and are the kurtosis and entropy of the CUT s response. A data set formed using the feature set [ ] with n observations made during the no-fault condition is used as training data. The mean and standard deviation of each feature element is calculated using the training data, from which the training feature sets in the no-fault condition are normalized: where and, ; (7), ( ( ) ), and ( ( ) ). (8)

5 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX After normalizing the feature sets, the Mahalanobis distances (MDs) are calculated during the no-fault condition using the following mathematical expressions: and (9) where and represent the correlation matrices for the wavelet and statistical features, respectively, and are calculated from the normalized feature sets as: and (10) where denotes the total number of classes, i.e., the fault conditions and the no-fault condition. In order to validate the MS, observations that fall outside the normal (or) no-fault group are identified, and the corresponding MD values are calculated. The characteristics of the abnormal group are normalized using the mean and standard deviation of the corresponding characteristics in the no-fault group. The correlation matrix corresponding to the no-fault group is used to compute the MDs of the faulty conditions. If the MS is constructed properly, then the MDs under the faulty conditions should have higher values than the normal group. Thus, if we plot the MD values obtained from the two feature sets on a two-dimensional plane, the fault conditions should be separable from the no-fault condition, as shown in Fig. 3. The figure also illustrates a typical trajectory in the two-dimensional space representing circuit degradation. Fig. 3. Illustration of fault propagation on the Mahalanobis Space. From Fig. 3 we can identify the degradation level of a circuit by observing the trajectory on the MS. However, monitoring the trajectory in the 2-D MS alone for prognostics has two drawbacks: 1) it is difficult to define a failure threshold, and 2) there can be abrupt changes in any of the MD values which are not easy to track. These drawbacks occur because of the difference in dynamic ranges for the MD values obtained from feature sets and (for example, for the sample circuit shown later, the range for MD 1 is found to be around , and for MD 2 it is found to be around 0 500). This happens because of the difference in the number of feature elements present in each of the feature sets. To address this issue, we have built an FI that gives equal weight to the MD values obtained from different feature sets. Once the MD values are calculated for the two feature sets, the FI is computed using the following transformation: (11) where and represent the number of feature elements in feature sets and respectively. The advantage of the FI defined above is that it is invariant to abrupt changes in MD values. This is realized by scaling it using the number of elements present in each feature set. Our study indicates that the FI has an increasing trend with respect to the amount of deviation in the faulty component from its nominal value. In the future, new feature sets might be suggested for fault diagnosis. Even if new feature sets are proposed, the above suggested FI calculation method can still be made compatible by extending Eq. (11) as follows: (12) where denotes the total number of feature sets extracted, and and denote the total number of feature elements and the MD values corresponding to the feature set, respectively. E. Anomaly Detection Threshold A threshold for anomaly detection using the MT method is traditionally defined as MD 1. Here, in the calculation of the FI, an MD of 1 for both feature sets would result in an FI value of 0.5. According to the MT method, the circuit is supposed to be displaying abnormal behavior when the FI value reaches 0.5. Through our experimental study we found the FI values to be greater than 0.5, whenever a drifted outside its tolerance range. Thus, we chose the FI value of 0.5 as the threshold for anomaly detection. F. Fault Detection and Isolation In this work, the fault detection and isolation problem is dealt with using an ML-based fault dictionary approach. During the training phase, the most likely fault conditions are first anticipated. Then, features are extracted from the circuit s response to the test signal under each of the fault conditions, which are emulated by seeding faults into the circuit. These features, along with the corresponding fault conditions, form the fault dictionary. Here, the no fault condition is treated as a special form of fault condition and thus forms a separate class in the fault dictionary. We employ a one-against-one multiclass least squaressupport vector machine (LS-SVM) to learn from the extracted features (inputs) and the corresponding fault conditions (labels). The classifier s model parameters are identified during the training phase. During the diagnosis phase, the extracted features are compared with the features stored in the fault dictionary using the trained classifier. Since the no-fault condition is treated as a separate class, the output of the classifier will indicate whether the extracted features belong to a faulty or no-fault condition. The output of the classifier also denotes the faulty component. The theoretical background pertaining to the classifier used is provided in the next section.

6 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX G. Failure Prognostics The remaining useful life (RUL) of a system/component is defined as the duration from the current time to the end of useful life. In the case of analog circuits, a circuit is considered to have failed when one or more critical components in the circuit have deviated in their value beyond a permissible level, as defined by the circuit designer. But this definition of failure does not literally refer to a functional failure of the critical component. The critical component that is claimed to have failed may still function, but not within the permissible operation range. Hence, it is appropriate to refer to the time to circuit failure as the remaining useful performance (RUP) instead of RUL, as it indicates the time that the circuit performance will ensure system operation. In this study, RUP is estimated from the FI s evolution, as at any time instant its value reflects the amount of deviation in any of the critical components. The RUP estimation is assisted by employing an appropriate prognostics method. A variety of on-line prognostics methods have been proposed in the past. However, in applications where fault models are not available, statistical data-driven prognostic approaches are employed, because they exhibit mathematical properties that are effective in managing uncertainties. Statistical data-driven prognostic approaches rely on available past and present observed data, and statistical models to estimate the RUP in a probabilistic way. One such approach is particle filters (PFs), which has become a popular choice in the PHM community due to its 1) ability to model nonlinear non-gaussian systems, 2) ease of implementation, and 3) support for uncertainty management. A PF approach (also known as the Bayesian Monte Carlo approach) is employed in this work for estimating the RUP of a circuit. The second part of Section IV covers the theory behind PF and the concept of RUP estimation using PF. A. Fault Classifier IV. THEORETICAL BACKGROUND The support vector machine (SVM) classifier theory developed by Vapnik [64] uses a kernel function to map the input samples to a higher dimension feature space. The input samples become linearly separable in higher dimension feature space (see Fig. 4). However, this classifier is obtained by solving a complex quadratic programming (QP) problem. In contrast, the least squares-support vector machine (LS-SVM) classifier introduced by Suykens and Vandewalle [65], [66] reduces the complexity and computations involved in SVM. Fig. 4. Illustration of binary fault classification using a SVM. Given a set of input and output training pairs { }, with and { } being the input vectors and output labels, respectively, the LS-SVM approach aims to construct a binary classifier of the form [ ] (13) where is a weight vector and is a bias term that are estimated by solving the following cost function: (14) subjected to the equality constraint. However, the weight vector can be infinite dimensional. Hence, the optimization problem in Eq. (14) is solved in the dual space using the Lagrangian function: { [ ] } (15) where are the Lagrange multipliers. With this definition of Lagrangian function and optimality conditions, the LS-SVM classifier in the dual space takes the following representation: [ ] (16) where and are the model parameters, and is the kernel function. In the LS-SVM settings, the model parameters are obtained by solving the following system of linear equations: [ ] [ ] [ ] (17) where [ ] [ ] [ ] [ ] and [ ]. 1) Multiclass Classification: In a multiclass setting, the input data and class labels are defined as { }, where { }, and refers to the total number of classifiable classes. The commonly used multiclass LS-SVM classification techniques are the one-against-one (OAO), oneagainst-rest (OAR) [67], and directed acyclic graph (DAG) [68] LS-SVM. The OAO LS-SVM classifier provides the best balance between the sample numbers of both classes under consideration. An OAO technique for class classification constitutes classifiers, where each classifier is trained by the data from two classes alone according to the LS-SVM algorithm. Voting is used during testing phase, after all the classifiers are constructed, which is based on the following decision function [69], [70]: [ ] (18) where and are the weight vector and bias term of the and classes respectively. The weight vector is found only from the data samples belonging to the and classes alone. During the testing phase, the test data are classified into their corresponding classes based on the following relation: where. (19) If the Eq. (19) is satisfied for one, then is classified into class ; otherwise, if the equation is satisfied for plural s, then is categorized under the class with the least label.

7 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX B. Failure Prognostics Failure prognosis is often performed by generating longterm predictions of the FI signal until a predetermined failure threshold is reached [71] [73]. Since uncertainty is inherent in such prediction processes, the evolution of the FI is generally modeled as a stochastic process and estimates of the RUP are made in the form of PDFs [15], [74]. Stochastic nonlinear filters have received attention in the research community. The procedure for estimating RUP using stochastic filters involves estimating the current health state of the system and then performing p-step predictions on the future health state. These two steps are discussed in the following subsections. 1) Nonlinear Filtering: To define the problem of current health state estimation, consider the evolution of the FI, { }, to be based on the following dynamical model: (20) where and are known nonlinear functions, and { } and { } are the process and measurement noise, respectively. The objective is to recursively estimate the health state from the measurements up to time (i.e., the posterior PDF ). In principle, the nonlinear filter computes the posterior PDF using the system model and prior PDF at time via the Chapman-Kolmogorov equation [75]:. (21) When a new measurement is available, then the estimate on is updated via Bayes rule as follows: (22) where the denominator acts as a normalizing constant that depends on the likelihood function defined by the measurement model and noise as follows: (23) The relations in Eqs. (21) and (23) form the basis for computing the Bayesian estimate of the FI from the measurements. However, it is not feasible to determine the above relations in the analytical sense due to the infinite dimensionality of the posterior PDFs. Hence, approximate forms of nonlinear filters are used to obtain estimates of the posterior PDF. 2) Particle Filter: One of the most commonly used forms of approximate nonlinear filters in the PHM field is the particle filter (PF). Many variations of the PF are available. However, we shall focus on the sampling and importance resampling (SIR) form of the PF. The idea is to represent the posterior PDF using a set of random samples with associated weights { }. The Bayesian estimates are computed based on these samples (or particles) and their weights: ( ) (24) where is the Dirac delta function. In practice, is usually not known. Hence, the samples are chosen from the importance density and their associated (normalized, such that ) weights are chosen using the principle of importance sampling, which is expressed as [73]: ( ) ( ) ( ) (25) If the importance density function is chosen to be ( ) ( ) then the weights can be updated using the following relation: ( ) (26) Resampling is used to address issues introduced by the degeneracy of particles, where, after a few iterations, all but one of the particles has negligible weights. During resampling, particles with small weights are eliminated, allowing us to concentrate on the particles with larger weights. 3) RUP Estimation: When the threshold for anomaly has been reached, the p-step prediction is generated using the system model in (20) and the current health state. During the prediction process, the weights of the samples are kept constant and are not updated as there are no measurements. At each prediction step, the predicted health state is checked with the failure threshold. The prediction time at which the FI crosses the failure threshold denotes the time at which the system is predicted to fail. A RUP estimate is obtained by computing the distance between the predicted time of failure and the current time instant. The PDF for RUP is obtained by finding the RUP for all N paths traversed by the N-particles, and then associating them with their weights. We can approximate a prediction distribution (p-steps forward) as follows: ( ) (27) V. IMPLEMENTATION RESULTS AND DISCUSSION We demonstrated our PHM framework on two analog circuits. Since a single-fault situation has a higher probability of occurrence than a multiple-fault situation, the proposed method can be generalized for multiple-fault situations if it works for single-fault cases [22]. Hence, in this demonstration we focused on detection, isolation, and prognosis of singlefault cases in the presence of component tolerances. A 50% deviation from the nominal value of a circuit element has been considered as a fault in most of the previously reported diagnostic techniques, ([22], [35] [45]), irrespective of the tolerance range of their circuit elements. These works do not explicitly state the diagnosability achieved using their fault diagnostic technique when the circuit element value deviates within the intervals [ to ] and [ to ], where is the tolerance range, and is the nominal value of the circuit element. Catelani and Fort [23] did consider the above shown deviation ranges in their definition of circuit fault, and performed a simulation study. In that study, the authors extracted features for faulty circuit

8 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX conditions by assuming a uniform distribution (defined in the intervals [ to ] and [ to ]) for the deviation in their circuit element s value, and demonstrated a 94% diagnosability. However, the authors did not mention the performance of their fault diagnostics method in situations where the deviation in circuit elements value was just beyond their tolerance range. Furthermore, their method along with the aforementioned fault diagnostic methods has been validated using simulation data. Aminian and Aminian [37] showed that the performance of a fault diagnostic method over experimental data will be lesser than that using simulation data (from the SPICE model) due to the inherent differences between a real circuit and its SPICE model. Hence, the performances of the aforementioned fault diagnostic methods during implementation become uncertain. We considered a circuit to be faulty when its critical elements deviates beyond their tolerance range, i.e., and, where is the value of a circuit element. We demonstrated the diagnosability of the proposed technique using experiments performed on actual circuits. Based on this definition for circuit faults, we defined the minimum detectable fault size (MDFS) to be. MDFS refers to the minimum fractional deviation in the circuit parameter from its nominal value for the fault to be detectable with all other circuit parameters held within their tolerance range. (a) Fig. 5. Experimental setup for demonstrating the developed approach. The experimental setup for demonstrating our approach is shown in Fig. 5. The circuit was excited with a sweep signal (1 V p-p ) ranging from 1 to 100 khz for 100 msec using an Agilent Arbitrary Waveform Generator 33250A. The circuit response was captured at the output using a NI USB-6212 data acquisition board with a sampling rate of 200 ks/sec. The data were recorded using LabView. Agilent Digital Oscilloscope 54853A was used to monitor the signal s consistency. A Sallen-Key band-pass filter centered at 25 khz and a Biquad low-pass filter with 10 khz upper cut-off frequency are the sample circuits was used for testing our approach (Fig. 6). The circuit elements had a tolerance range of 10%. Hence, the MDFS was considered to be 20%. Features extracted when all the components varied within their tolerance range belonged to the no-fault (NF) class. Faulty responses were obtained when any of the critical components varied beyond the MDFS range. Tables I and II show the fault classes and the corresponding fault values used in this analysis. (b) Fig. 6. Sample circuits used with their component s nominal value (a) 25 khz Sallen-Key band-pass filter, and (b) biquad low-pass filter with an upper cut-off frequency of 10 khz. In previous studies [35] [45] (except for [21]), the resistors and capacitors were assumed to have tolerances of 5% and 10% respectively. Alippi et al. [21] assumed the circuit components to have a tolerance of 1%. Large tolerance ranges (~10%) would increase the possibility of the CUT s transfer functions to overlap under different fault classes. This would pose a challenge for fault classification. We wanted to demonstrate reliable fault classification even under a worstcase scenario. Hence, circuit elements with 10% tolerance were chosen in this study. TABLE I FAULT CLASSES FOR SALLEN-KEY BAND-PASS FILTER. Fault Class Fault Code Nominal Value Faulty Value NF F0 - - R3 F1 2kΩ 2.31, 2.53, 3.66 kω R3 F2 2kΩ 0.883, 1.5, 1.79 kω C F3 5nF 6,7, 8 nf C F4 5nF 1.5, 2.5, 3.5nF R F5 1kΩ 1.24, 1.61, 2.21 kω R F6 1kΩ 372.3, 669, 836 Ω C F7 5nF 6, 7, 8nF C F8 5nF 1.5, 2.5, 3.5nF A. Fault Diagnosis For validation, we intentionally introduced faulty components (see Tables I and II for the fault values introduced) in both circuits to generate fault-free and faulty responses. This was done using variable resistors and

9 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX capacitors, and manually controlling their value (which was verified using a digital multimeter) to represent different fault classes. For each fault value under each fault class, 50 and 10 responses were generated for the band-pass and low-pass filter circuit respectively. This corresponds to 150 and 50 feature vectors for each fault class under the band-pass (3 fault values 50 responses for each fault value) and low-pass (5 fault values 10 responses for each fault value) filter circuits, respectively. For the low-pass filter circuit, only 10 responses were generated, in contrast to 50 responses for the band-pass circuit. This was done in order to test the proposed fault diagnostics method s diagnosability under a situation with fewer training data. TABLE II FAULT CLASSES FOR BIQUAD LOW-PASS FILTER. Fault Fault Nominal Value Faulty Value Class Code NF F0 - - C F1 5nF 6, 7, 8, 9, 10 nf C F2 5nF 4, 3.5, 3, 2.5, 2 nf C F3 5nF 6, 7, 8, 9,10 nf C F4 5nF 4, 3.5, 3, 2.5, 2 nf R F5 6.2kΩ 7.4, 8.6, 10, 11.2, 12 kω R F6 6.2kΩ 5, 4.35, 3.72, 3, 2.5 kω R F7 6.2kΩ 7.4, 8.6, 10, 11.2, 12 kω R F8 6.2kΩ 5, 4.35, 3.72, 3, 2.5 kω R3 F9 6.2kΩ 7.4, 8.6, 10, 11.2, 12 kω R3 F10 6.2kΩ 5, 4.35, 3.72, 3, 2.5 kω R4 F11 1.6kΩ 1.9, 2.25, 2.6, 2.9, 3.2 kω R4 F12 1.6kΩ 1.3, 1.1, 0.95, 0.8, 0.65 kω The terminologies used for evaluating the performance of the proposed fault diagnostics method are defined as follows: False negative: Number of cases in which there was a fault, but the classifier distinguished it as a no fault case. False positive: Number of cases in which there was no fault, but the classifier indicated a fault in the circuit. Precision: Of all the cases that actually were detected to be faulty, the fraction of cases that were actually faulty. Fault diagnosability: Of all the fault cases, the fraction of cases which were correctly detected to have a fault. Accuracy: Ratio of correctly classified test cases to all the test cases. Two types of analyses were carried out to evaluate the proposed fault diagnosis approach. In the first analysis, the fault classifier s ability to classify faulty conditions when components vary within their tolerance range was tested. For this purpose, data collected under each fault value were divided into two equal halves for training and testing. Thus, for the band-pass circuit there were 75 no-fault and 600 faulty cases, and for the low-pass circuit there were 25 no-fault and 325 faulty cases for training and testing. The training and testing features were extracted from the different circuit responses that were obtained under the same fault classes and fault values. However, the data sets were extracted when all other components were randomly varying within their tolerance range. The results of this analysis are shown in Table III and IV respectively. TABLE III FAULT DETECTION AND ISOLATION PERFORMANCE IN BAND-PASS FILTER CIRCUIT. F0 F1 F2 F3 F4 F5 F6 F7 F8 F F F F F F F F F The second type of analysis was carried out to verify the robustness of our approach in detecting fault values that were not seen during the training phase. In practice it is not possible to generate training data for all fault values in all fault classes. Only a representative set of fault values can be chosen for training. However, this should not affect the diagnosability of the fault classifier for unseen fault values. Hence, in this analysis, the fault classifier was trained with fault values that deviated by 40% and 60% from the nominal value, and we tested the responses obtained under the fault value of 20%. The results for both analyses are shown in Table V. Similar results were obtained when validation was performed with 20 and 40% deviations for training and a 60% deviation for testing. TABLE IV FAULT DETECTION AND ISOLATION PERFORMANCE IN BIQUAD LOW-PASS FILTER CIRCUIT. F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F F F F F F F F F F F F F

10 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX From Tables III and IV, it can be seen that the proposed approach accurately (100%) detected faulty conditions in both the Sallen-Key band-pass and the Biquad low-pass filter circuit. For fault isolation, the proposed approach was able to isolate faulty components with an accuracy of 99.7% and 95.7% in the Sallen-Key band-pass and the Biquad low-pass filter circuit, respectively (for accuracy values, see Table V). Some of the previously proposed diagnostic approaches [19], [36] [39] have shown higher classification accuracy than the proposed approach for the Biquad low-pass filter. However, in [36] [39], validation has been performed with a 50% fault deviation, and the diagnosability when critical components vary just beyond MDFS range has not been explored. Alippi et al. [19] considered variation around MDFS during their validation; they considered only 7 fault classes for validation, in contrast to the 13 fault classes in this study. Furthermore, the results shown in the diagnostic approaches [19], [36] [39] are based on SPICE simulation studies instead of using response data from real circuits. In addition, in the analysis of a low-pass filter, the number of training vectors selected was smaller than the training vectors considered in [19], [36] [39]. Even with smaller training samples the developed fault diagnostics method can detect faulty circuit conditions and isolate faulty components with an accuracy of 100% and 96%, respectively. This proves that our fault diagnostics method can generalize well and is capable of performing reliably using a small training set. TABLE V PERFORMANCE EVALUATION OF THE DEVELOPED PHM METHOD FOR FAULT DETECTION AND ISOLATION Performance Metrics Analysis I Band-pass filter Analysis I Low-pass filter Analysis II Band-pass filter False positives False negatives Accuracy 99.7% 95.7% 99.6% Precision 100% 100% 100% Fault diagnosability 100% 100% 99.6% Further, we investigated the misclassified fault types. From Tables III and IV, it can be seen that there are 2 and 14 misclassifications for band-pass and low-pass filters, respectively. Misclassification in the low-pass filter always occurred between fault classes F3 and F11. These classes correspond to the faults in components C2 and R4. Our study indicated that the transfer function of the low-pass circuit under fault classes F3 and F11 overlap, thereby leading to misclassification. If we combine the fault classes depicting faults in C2 and R4 into one ambiguity group, then we can realize 100% accuracy in fault classification. Irrespective of the circuit type, our approach performed well in distinguishing faulty from fault-free conditions. In the cases investigated, our approach did not fail to detect faults in the band-pass and low-pass filter circuits (see Table V). The proposed approach accurately (100%) identified the faulty component even if the component value was closer to the MDFS. From the results shown in Table V, we can also infer that our approach is robust with respect to both component fluctuations within a tolerance range and to fault values that are not seen during the training phase. B. Failure Prognostics Component degradation is accompanied by a gradual change in component value. This change can have a negative impact on circuit performance. In Section III, the FI was developed to denote the degradation in analog circuits. Fig. 7 shows that the trend exhibited by the FI as the components C2 and R3 in the Sallen-Key band-pass filter and C1 and R4 in the Biquad-low pass filter deviated from their nominal values. We assumed that the fault level increased gradually with respect to time, where, with each time index, the fault level increased by 0.4%. In this context, the time index is one cycle wherein a 100 msec test signal stimulated the CUT and the response was measured. Through curve fitting on the FI data (obtained from features extracted during different simulated fault conditions simulation performed using PSPICE), it was found that a model of the following form can describe the FI trend of different components in different analog circuits well: [ ( ) ] [ ( where is the FI, is the time index; and and are the model parameters. C2 R3 ) ] (28), Fig. 7. Trend exhibited by FI during the degradation of circuit components. In order to perform prognosis, the above regression model was exploited. However, to deal with the uncertainties caused by component tolerances and usage conditions, the model was assumed to be stochastic. Hence, the parameters of the model were subjected to Gaussian distribution. This stochastic model was fed into the online prognostics routine. Features extracted from the circuit s response were used to calculate the current FI value. The calculated FI value was used to estimate the model parameters. Once the diagnostic routine detected an anomaly, it triggered the prognostics module. The model parameters were incorporated as the elements of a state vector. Random walk was employed to estimate the model parameters: C1 R4

11 RUP estimates RUP estimates Fault Indicator RUP estimates Fault Indicator RUP estimates IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX (a) Failure threshold Estimate Mean RUP estimate Actual Failure = 106 time index Predicted Failure = 104 time index Real data 31 time index RUP PDF Time Index (a) EOL prediction is 40 Prognostics algorithm 26 time index Mean RUP estimate Max RUP estimate Min RUP estimate Failure 41 time index Time index Failure threshold Actual Failure = 106 time index Predicted Failure = 105 time index EOL prediction is 102 EOL prediction is 96 Mean RUP estimate Max RUP estimate Min RUP estimate (b) time index RUP PDF Time Index (b) Prognostics algorithm 26 time index Failure 94 time index Time index Mean RUP estimate Max RUP estimate Min RUP estimate Mean RUP estimate Max RUP estimate Min RUP estimate EOL prediction is 112 EOL prediction is 109 (c) Time index Fig. 8. Prognostics results using particle filters for the Sallen-Key band-pass filter for fault progression in component C2: (a) prediction result at time index 31; (b) prediction result at time index 70; and (c) RUL estimation at every time index. [ ( Prognostics algorithm triggered ) ] [ ( Failure reached (29) ) ] where is the measured value of the FI variable at time index, and is a Gaussian distribution with mean zero (c) Prognostics algorithm 30 time index Failure 107 time index Time index Fig. 9. Prognostic results using particle filters for (a) Sallen-Key band-pass filter for fault progression in component R3, (b) biquad low pass filter for fault progression in component C1, and (c) biquad low pass filter for fault progression in component R4. and standard deviation. Using the PF, the future values of FI are calculated. The RUP was calculated based on the time index at which the predicted FI value crosses the failure threshold. In this demonstration, we found that by the time the FI value reaches a value of 2, the fault level for most of the components has crossed 40%. Hence, in this work we chose a value of 2 for the FI as the failure threshold. A threshold value of 2 for the FI is a qualitative threshold. In the future, a method to establish a failure threshold needs to be developed. Also, the initial values of the model parameters (obtained from curve fitting) and their standard deviations were assumed to be known for the sake of simplicity. In practice, an efficient method needs to be devised to choose these values for the model parameters.

12 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. XX, XXXX The results for fault progression in component C2 of the Sallen-Key band-pass filter circuit are shown in Fig. 8. Fig. 8(a) shows the RUP estimation at the time instant an anomaly was detected (i.e., ). This occurred at time index 31. Thus, the data from the first 31 time indices alone are used to update the model. The estimated RUP is 73, and thus the predicted end-of-life (EOL) is 104, and the actual failure occurs at the 106 th time index. In Fig. 8(b), the prognostics results performed at time index 70 are shown. The predicted EOL is the 105 th time index. Thus, the error in prediction is only 1. Also, the prediction PDF becomes narrower as we get closer to the failure time, indicating the improvement in prediction confidence. Fig. 8(c) shows the RUP estimates at different time indices with 95% confidence bounds. In order to show the applicability of the proposed approach for different components and circuits, the RUP estimation at different time indices for the component R3 in the Sallen-Key band-pass filter circuit and the components C1 and R4 in the biquad low-pass filter circuit are shown in Fig. 9. C. Computation Time The computation time involved for the developed PHM method was investigated so as to analyze its applicability to circuits in field operation. Table VI shows the computation time involved in the individual steps of the proposed PHM framework. The computation time were computed on a MATLAB 2010 environment which was run on an Intel Core 2 Duo E GHz processor with 2 Gb RAM. TABLE VI COMPUTATION TIME OF THE PROPOSED PHM FRAMEWORK Step Computation Time Feature extraction (includes noise, removal, < 2.6 msec extraction and normalization of features) Fault indicator (FI) computation < 0.1 msec Fault detection and isolation < 1.35 msec Updating Model Parameter for RUP Estimation < 10 msec In the case study, it was found that the computation time involved in 1) feature extraction, 2) FI calculation, and 3) model parameter estimation (for RUP estimation) was the same for both the band-pass and low-pass filter circuits. However, the computation time for the fault detection and isolation step in the band-pass and low-pass filter circuits was found to be around 1.35 msec and 1 msec respectively. This was because the computation time for fault detection and isolation depends on the number of training data used (due to the use of LS-SVM). Here, the number of training samples used in the band-pass filter was more than of the number of the training samples used in the low-pass filter circuit. From Table VI it can be seen that fault diagnostics and isolation step can be performed in less than 4 msec. This proves that the proposed approach is suitable for detecting and isolating faults in an analog circuit during field operation. Moreover, a computation time of 10 msec for PF parameters updating at each cycle denotes that the proposed prognostics approach is capable of generating RUP predictions in a reasonable timeframe. VI. CONCLUSIONS Test methods for analog circuits have traditionally been developed to diagnose faults in the electronic circuits of complex systems during the product development process. These test methods are not intended for the testing of analog circuits in field operation, nor are they intended for predicting system failures due to circuit faults. But, the nature of the functions performed by mission or safety critical electronic systems demands methods that would enable the prevention of system failures due to faulty circuits. To address this concern, a method for the real time diagnostics and prognostics of analog circuits with an emphasis on early fault detection and failure prevention, has been presented in this paper. Here, by early detection we refer to the identification of components deviating just outside the standard tolerance range. The fault diagnostics method established in this work follows an ML-based approach that uses only the measurements made at the circuit output to generate patterns for the early fault detection and isolation. In contrast to diagnostic methods based on circuit nodal equations, the proposed approach is not limited by the inaccessibility to the internal nodes of analog circuits as in modern integrated circuits, because the approach monitors only the response of the circuit at the output node. The developed method demonstrated 99% diagnosability even under situations involving 1) component fluctuation within a tolerance range and 2) fault values that are not seen during the training phase. These results indicate that the developed diagnostic module is robust and is capable of delivering reliable information during field operation. A fault indicator (FI) and model adaptation scheme to track the evolution of FI has been developed for estimating the RUP of an analog circuit. The unique feature of this FI is its ability to summarize the degradation level in each of the circuit s critical components using the features extracted from circuit response. Thus, RUP estimation can be performed without monitoring the individual components of the circuit. The circuit FI is also compatible with future changes in the extracted features. Thus, even if new features (for circuit fault diagnosis) are introduced in the future, RUP estimates can still be obtained using the circuit FI developed in this work. The challenges in estimating the RUP of an analog circuit are the presence of uncertainties that are introduced by component tolerances and the time-varying nature of the environment. To address this challenge we have developed a model adaptive statistical approach for providing real time predictions of the circuit s RUP. RUP estimates are given in the form of probability distributions, indicating the confidence levels in the prediction. Preventive maintenance actions can be performed using the estimated RUP information for avoiding unexpected system failures due to faults in circuits. REFERENCES [1] G. Escobar, P. R. Matinez, and J. Leyva-Ramos, Analog circuits to implement repetitive controllers with feedforward for harmonic compensation, IEEE Trans. Ind. Electron., vol. 54, no. 1, pp , 2007.

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Inst. Meas. Control, vol. 31, no., pp , [75] M. Arulampalam, S. Maskell, N. Gordon, and T. Clapp, A tutorial on particle filters for online/non-gaussian Bayesian tracking, IEEE Trans. Signal Process., vol. 50, no. 2, pp , Arvind Sai Sarathi Vasan (M 12) received the B.E. degree in electronics and communication engineering from SSN Institutions, Chennai, India. He is currently working towards his Ph.D. degree in mechanical engineering at the Center for Advanced Life Cycle Engineering (CALCE), University of Maryland, College Park. From October 2011 to September 2012 he served as the student chair for the Prognostics and Health Management (PHM) society. In 2011, he was one among the ten graduate students to have been selected for the PHM society doctoral consortium. He was a part of the team that won the 2012 IEEE PHM data challenge contest. He is currently involved in the development of IEEE standard P1856 for the PHM of electronic systems. His main areas of interest include prognostics of electronics, diagnostics, and machine learning. Bing Long was born in Chengdu, China, in July He received the Doctoral degree in aerospace science from the Harbin Institute of Technology, Harbin, China, in He is currently an Associate Professor with the School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu. His research interests include testability analysis and fault diagnosis of electronic device system. Michael Pecht (M 83 SM 90 F 92) received the M.S. and Ph.D. degrees in engineering mechanics from the University of Wisconsin, Madison. He is the Founder of Center for Advanced Life Cycle Engineering, University of Maryland, College Park, which is funded by over 150 of the world s leading electronics companies at more than U.S.$6 million/year. He is also a Chair Professor in mechanical engineering and a Professor in applied mathematics with the University of Maryland. He is the Chief Editor for Microelectronics Reliability. He has written more than twenty books on electronic product development, use, and supply chain management and over 500 technical articles. He consults for 22 major international electronics companies, providing expertise in strategic planning, design, test, prognostics, IP, and risk assessment of electronic products and systems. Dr. Pecht is a Professional Engineer, an ASME fellow, a SAE fellow, and an IMAPS fellow. Prior to 2008, he was the recipient of European Micro and Nano-Reliability Award for outstanding contributions to reliability research, 3M Research Award for electronics packaging, and the IMAPS William D. Ashman Memorial Achievement Award for his contributions in electronics reliability analysis. In 2008, he was the recipient of the highest reliability honor, the IEEE Reliability Society s Lifetime Achievement Award. In 2010, he was the recipient of the IEEE Exceptional Technical Achievement Award. He served as a Chief Editor of the IEEE TRANSACTIONS ON RELIABILITY for 8 years and on the Advisory Board of IEEE Spectrum. He is an Associate Editor for the IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGY.