Application of Feed-forward Artificial Neural Networks to the Identification of Defective Analog Integrated Circuits

Transcription

1 eural Comput & Applic (2002)11:71 79 Ownership and Copyright 2002 Springer-Verlag London Limited Application of Feed-forward Artificial eural etworks to the Identification of Defective Analog Integrated Circuits D. Mic us ík 1, V. Stopjaková 1 and L. Ben us ková 2 1 Department of Microelectronics; 2 Department of Computer Sciences and Engineering, Slovak University of Technology Bratislava, Slovakia This paper presents a new approach for detecting defects in analog integrated circuits using a feedforward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting faults in a simple analog CMOS circuit by representing the differences observed in power supply current of fault-free and faulty circuits. The identification of defects was performed in time and frequency domains, followed by a comparison of results achieved in both domains. We show that resilient backpropagation neural networks can be a very efficient and versatile approach for identifying defective analog circuits. Moreover, this approach is not limited to the supply current analysis, because it also offers monitoring of other circuit parameters. The type of defects detected by the resilient backpropagation neural networks, as well as other possible applications of this approach, are discussed. Keywords: Circuits response investigation; Fault modelling and simulation; Resilient-backpropagation neural networks; Signal filtering; Supply current analysis 1. Introduction Artificial eural etworks (As) are computing systems based on an analogy with the work of the nervous system of the brain, in which connections organise neurons into networks. One of the main Correspondence and offprint requests to: V. Stopjaková, Department of Microelectronics, Slovak University of Technology, Ilkovicova 3, Bratislava 81219, Slovak Republic. advantages of As is that they are massively parallel and distributed structures which can improve their performance through examples by a dynamic adaptation process. The use of As allows modelling of complex systems without requiring the explicit formulation of the relationships that may exist between variables. This allows the application of the As for solving difficult tasks such as pattern recognition, pattern classification, prediction, etc. [1 3]. The goal of an A designed for a pattern classification task is to adapt itself to classify input vectors, representing physical objects or events, into several categories. In a non-parametric approach to this problem, the requirement is to estimate arbitrary decision boundaries in the input signal space using a set of examples. The adaptation process of an A is performed only on a finite subset of all possible instances, also called the training set. The finite set of instances consists of input/target vector pairs. Each category is represented by one target vector, with which a lot of representative input vectors can be associated. After the adaptation process, when the network is taught on the training set, we can present vectors the network has never seen before, and the network is able to classify unknown vectors into correct categories [1,3,4]. One of the most important tasks in the design of recent Integrated Circuits (ICs) is their testing. Thus, a lot of effort has been put into the development of effective test approaches. A few years ago [5,6], power supply current (I DD ) monitoring was originally introduced as one of the most efficient test techniques for digital CMOS circuits. This method is based on the fact that defective circuits produce an abnormally high value of quiescent power supply

2 72 D. Mic us ík et al. current (I DDQ ) in faulty circuits. However, there have been some limitations in the straightforward use of this method for analog ICs, where the fault-free supply current consumption is unique for each circuit. Therefore, distinguishing between faulty and fault-free analog circuits is usually a very difficult and crucial task. Currently available test methods are usually either inapplicable to analog testing or they require sophisticated and complex apparatus. Taking into account the classification ability of As, the feed-forward A adapted in a proper way can be used very effectively to identify defects in analog ICs. We used two categories for power supply current (I DD ) behaviour: GOOD and BAD, corresponding to fault-free and faulty circuits, respectively. This means that every vector applied to the network input is to be classified into these two categories. Our paper shows simulation results in applying this approach for the detection of different defects injected into a simple HSPICE model of a CMOS operational amplifier. Significant results summarising other application possibilities of the proposed approach are also discussed. 2. etwork Architecture and Learning Algorithm 2.1. Mathematical Model of a euron As are composed of simple units (neurons) operating in parallel. These units are abstractions of biological neurons. As in nature, the network function is determined by the connections between neurons. Three basic elements of the neuron model can be identified: a set of synaptic weights, integration and activation function. The mathematical model of the neuron k is described by the following equations: p u k w kj x j b k (1) j 1 y k (u k ) (2) where x j is the output of neuron j, w kj is the weight from the jth to kth neuron, b k is the bias of the kth neuron, u k is the excitation of the kth neuron, (.) is the activation function, and y k is the output (activation) of the kth neuron. There are several types of activation functions used in the A, but the sigmoid function, given by Eq. (3), is usually used in the feed-forward type of A: (u) 1 1 exp( u) (3) The sigmoid function generates a continuous valued output between 0 and 1 as the neuron s net input goes from negative to positive infinity. It is defined as a strictly increasing function that exhibits smoothness and asymptotic properties. The sigmoid function is differentiable, which is an important feature of neural network theory, as will be described later Description of the A used A feed-forward A is a network of neurons organised in layers. There are three types of layer: an input layer of source nodes; one or more hidden layers of neurons; and an output layer of neurons. For most applications of feed-forward As, one hidden layer is enough. The number of hidden neurons is not exactly defined, and the only way to obtain it is by model selection, in which the training process is done for various numbers of hidden units. The layer of hidden units allows the network to extract important features from the signal. Simulations for 2, 6, 10, 14, 18 and 22 hidden units have been done. The Fast Fourier Transform (FFT) of power-supply-current waveforms has been done for representing signals in the frequency domain. The input layer was made up of 50 units, each clamped to an amplitude value of the signal to be classified. Before being applied to the network, each vector was normalised according to Eqs (4) (6): x i x i x (4) s (x i x) 2 s i 1 x x i i 1 (5) (6) where x i is the normalised input vector element x i, and is the number of input vector elements. The number of output units was arbitrarily set to two. The states of the output units determined the class of the signal: (1,0) represented waveforms of a fault-free IC, and (0,1) represented waveforms of a faulty IC. The neural network used in this case is fully connected, in the sense that every node in each layer of the network is connected to every other node in the adjacent forward layer. Figure 1 shows a diagram of the A used. For clarity, the

3 Identification of Defective Analog ICs 73 Fig. 1. Schematic diagram of the neural network structure used. bias connections to each neuron in the hidden and output layers are not shown. The source nodes in the input layer of the network supply elements of the input signals to the neurons (computational nodes) in the second layer (i.e. the first hidden layer). The output signals of the second layer are used as an input to the third layer, and so on for the rest of the network Learning Algorithm There are many learning algorithms used in feedforward As. They have been investigated, and the best results were found to have been obtained using resilient propagation developed by Riedmiller [7]. More information on learning algorithms may be found in [8,9]. Only a brief definition of the principal terms will be given here. Feed-forward As are adjusted or trained, so that finally a particular input leads to a desired target output. The network is being adjusted based on a comparison between the actual and target (desired) output, until the actual network output matches the target otput. Typically, many such input/target pairs are used in this supervised learning to train a network. The original backpropagation learning algorithm updates the network weights and biases in the direction in which the performance function (the global error) decreases most rapidly the negative of the gradient with respect to each weight and bias in the network. It incrementally adjusts the weights and biases to minimise the network performance function, usually the sum of squared errors, E. The error signal e j (n) at the output of neuron j at iteration n, and the sum of squared errors E(n) at iteration n, are defined by e j (n) d j (n) y j (n) (7) E(n) 1 e 2 j C 2 j (n) (8) where the set C includes all the neurons in the output layer of the network, d j (n) is the desired response (target) for neuron j at iteration n, and y j (n) is the actual output of the neuron j at iteration n. There are two different ways in which this gradient descent algorithm can be implemented: the incremental mode or the batch mode. In incremental mode, the gradient is computed and the weights are updated after each input is presented to the network. In batch mode, all of the training inputs are presented to the network before the weights are updated. We have chosen the batch mode, because it is faster and insensitive to the order of training vectors. Thus, it is necessary to define the mean squared error (mse) E av for the batch mode, such that E av 1 E(n) 1 n 1 2 n 1 j C e 2 j (n) (9) where is the training set size. Finally, the steepest descent (negative-gradient) rule is used to adjust the connection weights: E av (10)

4 74 D. Mic us ík et al. where is the change of the weight between the neuron i and neuron j, and (learning rate) determines the magnitude of the modification of the weight. Thus: w ji (t 1) w ji (t) (t) (11) where t is the time step. The sigmoid function is characterised by the fact that its partial derivative approaches zero as the input gets large. This causes a problem when using the steepest descent to train a multilayer A with sigmoid functions, since the gradients can have very small values, and lead to small changes in the weights and biases, even though the weights and biases are far from their optimal values. The purpose of the resilient backpropagation learning algorithm is to eliminate these harmful effects of the magnitudes of the partial derivatives. The individual update value ji is introduced for each weight. This adaptive update value is modified during the learning process. Only the sign of the partial derivative of E av is used to determine the direction of the weight update according to the learning rule: if E av(t 1) * E av(t) 0 then ji (t) * ji (t 1) if E av (t 1) * E av (t) 0 (12) then ji (t) * ji (t 1) if E av(t 1) * E av(t) then ji (t) ji (t 1) 0 where 0 1. Once the update value for each weight is adapted, the weight update itself follows a simple rule: (13) where (t) ji (t) *sign E av(t) 1 if x 0 sign(x) 1 if x 0 0 if x 0 (14) Then, Eq. (11) is applied for the weight update. One of the main problems in training is the initialisation of weight and bias coefficients. There are several approaches, but in practical applications of As, the most often used method is random initialisation from the uniform distribution of small numbers. This fact is important for understanding the training results of a given network. There is a requirement to do averages of more simulations and use these averages to decide which are the optimal network parameters. We have performed 10 parallel simulations for every setting, and results were taken as average values. The networks were simulated in MATLAB and its eural etwork Toolbox Tested Analog Circuit A simple two-stage CMOS operational amplifier has been used as a device under test. The selected circuit was described and simulated in a HSPICE circuit simulator. All simulations have been done with LEVEL3 transistor models, with both TYPI- CAL and FAST parameters for standard n-well CMOS 0.7 m technology. A circuit scheme of a tested operational amplifier is shown in Fig. 2. The circuit has been connected as an inverting conveyor to 2.5 V level applied to the non-inverting input. A pulse waveform has been used as the input test stimulus. Several different defects that can occur in the CMOS process have been injected into the circuit to obtain representative faulty current responses of the circuit. A selected input test pattern applied to the operational amplifier is shown in Fig. 3(a), and corresponding power supply current waveforms of fault-free circuit for FAST and TYPI- CAL transistors parameters are depicted in Fig. 3(b). 4. Fault Models Description To obtain faulty supply current responses of the circuit under test, several defects typically occurring in the CMOS analog process were modelled, embedded into the circuit and simulated [9]. Six types of basic MOS transistor faults DOP, SOP (drain/source opens); GDS, GSS, DSS (gate-drain, gate-source, drain-source shorts) and GOS (gate oxide short) have been injected into the operational amplifier. Open faults are disconnection caused by missing sections of conductive paths. They can be modelled by the insertion of a resistor of high value, Fig. 2. Tested operational amplifier scheme.

5 Identification of Defective Analog ICs 75 Fig. 3. Input test pattern (a), power supply current consumption for the fault-free circuit (b). Fig. 4. Drain (a) and source (b) open fault models, and gate oxide short model (c). together with a capacitor connected in parallel with the resistor. A simplified GOS fault model consists of a diode and a resistor representing the gate oxide short defect (Fig. 4). The short faults are caused by additional conduction paths that connect two or more nodes of the circuit together. They are modelled by the simple insertion of a resistor between two nodes (Fig. 5). The parameters of the resistors in open fault models were in the range 1 K 10 M in GOS faults in the range K and in short faults in the range K. Thus, 460 faulty states of the operational amplifier have been simulated altogether, where in each faulty state only one fault was injected. The locations of faults were chosen at random. The effects of the faults on power supply current signal for various values of fault control parameters are shown in Figs Fault Detection Results with A The size of the test set was 660 power supply current (I DD ) waveforms 200 fault-free and 460 faulty patterns. The fault-free I DD waveforms were obtained by varying the temperature and model parameters of transistors in the selected circuit. The faulty I DD waveforms were obtained by varying the type of MOS transistor faults (SOP, DOP, GOS, DSS, GDS and GSS) and the control parameters of faults (e.g. open resistance or short resistance) in randomly selected transistors. The adaptation process of As has been done for various sizes of training set (200, 100, 76, 50 and 26) to determine its ability to generalise. The number of hidden units required for accurate classification of the waveforms was determined empirically as 2, 6, 10, 14, 18 and 22. Fig. 5. MOS transistor short fault models: DSS (a), GDS (b) and GSS (c).

6 76 D. Mic us ík et al. Fig. 6. Effect of a DSS fault on I DD current in the (a) time and (b) frequency domains. Fig. 7. Effect of a SOP fault on I DD signal in the (a) time and (b) frequency domains. Each training set experiment with the given network topology was repeated 10 times with different initial weight values to average over variations in performance due to initial conditions. To avoid network over-training, we used a validation set of 132 randomly selected I DD waveforms from the test set. The network s performance on both the training and test sets was specified as the Percent Correct Classification (PCC). Figure 9 shows the PCC for the time as well as frequency domains. Each curve represents an average of 10 A adaptations with the specified number of hidden units. For clarity, only curves for 2, 6 and 22 hidden units in the time domain and curves for 2 and 22 hidden units in the frequency domain are shown. The decision boundaries for the network output were set to 0.1 for zero and 0.9 for 1. This means that outputs equal to or greater than 0.9 are rounded towards one, and outputs equal to or smaller than 0.1 are rounded towards zero. If at least one element of the network output vector is in the range (0.1 o i 0.9, where i 1,2), the input vector is not classified. Simulations in the time and frequency domains show that in the frequency domain, satisfactory results for all numbers of hidden units have been reached. Only two hidden units for 76 training vectors achieved a 97% correct classification. On the other hand, a strong dependence on the number of hidden units in the time domain has been observed. Average results obtained for the time and frequency domains are shown in Tables 1 and 2, respectively. The tables are divided into four sections: Percent Correct Classification (PCC), GOOD classification, BAD classification and on classified. Each section is divided into five columns, where

7 Identification of Defective Analog ICs 77 Fig. 8. Effect of different GOS faults on I DD signal in the (a)(c) time and (b) (d) frequency domains. Fig. 9. Percent Correct Classification (PCC) for the (a) time and (b) frequency domains.

8 78 D. Mic us ík et al. Table 1. Average results achieved for the time domain (660 test vectors). HU PCC (%) GOOD classification BAD classification non classified Table 2. Average results achieved for the frequency domain (660 test vectors). HU PCC (%) GOOD classification BAD classification non classified each column represents the size of training set (200, 100, 76, 50 and 26). Each row describes the results for a given number of Hidden Units (HU). The GOOD classification section represents a group of correctly classified waveforms from the test set of 660 total patterns. Similarly, the BAD classification section represents a group of incorrectly classified waveforms from the test set. The on classified section represents a group of waveforms from the test set, for which network outputs are not within the decision boundaries for the GOOD or BAD categories. 6. Hardware Implementation of the A If we considered a real test environment, there might be a requirement for a hardware implementation of the proposed neural network. The hardware solution of the neural network approach would offer a much higher computational speed than software simulation on conventional computers. There are several ways of possible hardware implementation. A first possibility could be the software algorithm applied to a Digital Signal Processor (DSP) specially designed processors for the efficient performance of mathematical calculations. Another possibility is to put the proposed neural network architecture on a chip that would offer the most effective solution in terms of computational speed. Two main on-chip implementations have been considered: a Field Programmable Gate Array (FPGA) for a digital type of network architecture, or an Application Specific Integrated Circuit (ASIC) if the network requires mixed digital-analog realisation. A final solution can be selected with respect to all significant aspects that the hardware implementation should offer (e.g. speed, time to develop, complexity, chip area, etc.). Hardware representation of the neural network approach for identifying defective integrated circuits is currently under development. 7. Conclusion A new efficient resilient back-propagation A approach to the detection of a wide range of defects in analog CMOS ICs is proposed. It was shown that an A is able to identify defective integrated circuits. Our results indicate the possibility of using this approach as an effective and flexible test method, especially for analog designs where parametric testing is not an easy task and usually requires complex test equipment. This is exactly the area in which the neural network approach seems to be a good alternative that is easily adaptable for an arbitrary circuit parameter (e.g. output voltage,

9 Identification of Defective Analog ICs output current, frequency response, etc.). Moreover, the A approach also gives very good classification answers for inputs that the network has never seen before. This justifies the approach being a versatile and smart test method that can detect unknown types of defects or defects that are difficult to detect which remain hidden using conventional test techniques. References 1. Gorman RP, Sejnowski TJ (1998) Analysis of hidden units in a layered network trained to classify sonar targets. eural etworks 1: Sbirrazzuoli, Brunel D (1997) Computational neural networks for mapping calorimetric data: application of feedforward neural networks to kinetic parameters determination and signals filtering. eural Comput & Applic 5: Beasley JS, Righter AW, Apodaca CJ, Pour-Mazafari S, Huggett D (1997) I DD pulse response testing applied to complex CMOS ICs. Proc Int Test Conf Haykin S (1994) eural etworks A Comprehensive Foundations. Macmillan College Publishing 5. Acken JM (1983) Testing for bridging faults (shorts) in CMOS devices. Proc Dig Autom Conf, San Francisco, CA Hawkins CF, Soden JM (1985) Electrical characteristics and testing considerations for gate oxide shorts in CMOS IC s. Proc Int Test Conf, Philadelphia, P Riedmiller M, Braun H (1993) A direct adaptive method for faster backpropagation learning: the RPROP algorithm. Proc IEEE Int eural etworks, San Francisco, CA 1: Zornetzer SF, Davis JL, Lau C, McKenna T (1995) An Introduction to eural and Electronic etworks, 2nd ed. Academic Press 9. Sidiropulos M, Stopjakova V, Manhaeve H, Musil V (1999) An analog self-test based on differential I DD monitoring supported by differential I out checking. Analog Integrated Circuits & Signal Process 21: Star-Hspice Manual, Release 1998 (1998) 2, Avant! Corporation, July 11. Demuth H, Beale M (1998) eural etwork Toolbox User s Guide. The Mathworks Inc