Design of a high-frequency series capacitor buck converter

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SEM2200 TI Literature Number: SLUP337 2016, 2017 Texas Instruments Incorporated

1 Power Supply Design Seminar Design of a high-frequency series capacitor buck converter Reproduced from 2016 Texas Instruments Power Supply Design Seminar SEM2200 TI Literature Number: SLUP , 2017 Texas Instruments Incorporated Power Seminar topics and online power training modules are available at:ti.com/psds

2 Design of a high-frequency series capacitor buck converter Pradeep Shenoy

3 Agenda High-frequency buck converter limitations Series capacitor buck converter Sample experimental results Design of a high-frequency series cap buck converter Series cap buck converter prototype TPS54A20 Series capacitor Inductors 1-2

4 Power delivery system Point-of-load Voltage Regulators Intermediate bus architecture 1-3

5 Why increase switching frequency? Inductors usually are the largest component. 1) Smaller size Converter volume: 1,270 mm 3 Converter volume: 157 mm 3 Inductor volume: 232 mm 3 Inductor volume: 19.2 mm 3 2) Faster response 3) Lower BOM cost 1-4

6 Inductor size reduction: 10-A output 2-5 MHz 500 khz High-frequency operation! 15 times smaller inductors! 1-5

7 High-frequency (HF) buck converter limitations Buck converter High switching loss Ploss f sw Switch timing diagram High-side switch on-time is very short at HF o o 5 MHz! 200 ns period 10-to-1 voltage ratio! 20 ns highside on-time HF converters on today s market have low-conversion ratios (<5-to-1) and low current (<1A) 1-6

8 Series capacitor buck topology Series capacitor Two-phase, series cap buck converter Benefits o Single conversion stage o Switching at reduced V DS o Series cap soft charge/discharge o Automatic current balancing o Duty ratio doubled Drawbacks o 50% duty cycle limitation " Theoretical: V IN,MIN = 4 V OUT " Practical: V IN,MIN = 5 V OUT o No phase-shedding P.S. Shenoy, M. Amaro, D. Freeman, and J. Morroni, Comparison of a 12V, 10A, 3MHz buck converter and a series capacitor buck converter, in Proc. IEEE Applied Power Electron. Conf., pp , Mar

9 Steady-state operation: Interval 1 1-8

10 Steady-state operation: Interval 2 1-9

11 Steady-state operation: Interval

12 Steady-state operation: Interval

13 Reduction in inductor current ripple Up to 33% reduction in inductor current ripple o Same L, V IN, V OUT, f SW, etc. Benefit: reduces inductor core loss P core k f B k Δi sw pk 0 sw L f Δi Current ripple ratio: Δi L, SCBuck L, Buck 1 2( V = 1 ( V O O / V / V IN IN ) ) Alternative: reduction in required inductance o Same Δi L, V IN, V OUT, f SW, etc. 1-13

14 TI high-frequency controller Adaptive constant on-time control o Fast transient response o Internal compensation Frequency synchronization by adapting on-time o Fixed-frequency in steady state o External clock or internal oscillator 1-15

15 Current density comparison Current Density (A/cm3) (as of Jan 2016) TPS54A20 Research Industry Series cap buck: 1.2 mm high TPS54A20 IC Inductors Conventional buck: 4.8 mm high Rated Output Current (A) A 3x to 7x improvement in total solution current density 1-16

Series capacitor selection Cap is (dis)charged by the inductors Select the cap value to keep voltage ripple <8% at full load o Ex: 10 A load, 2 MHz, 12 V IN, 1.2 V O C = i DT 0.08 V out in 2 1.

16 Series capacitor selection Cap is (dis)charged by the inductors Select the cap value to keep voltage ripple <8% at full load o Ex: 10 A load, 2 MHz, 12 V IN, 1.2 V O C = i DT 0.08 V out in 2 1.2V 2 12V = V ( 10A ) 2MHz 2 ( ) = 1.04µF PGOOD V O Tradeoff: startup delay to precharge the series cap o 10 ma precharge current into 1 µf cap! 625 µs to precharge to 6 V Precharge EN SCAP 1-21

17 Feedback network selection # Simple - No phase boost # Phase boost - Less flexibility # Flexible phase boost - More components # Noise immunity - Most components Example: V IN = 12 V, V OUT = 1.2 V F SW = 2 MHz, I OUT = 4.8 A C OUT = 191 µf, L = 250 nh Configuration Crossover Frequency Phase Margin khz khz

18 HotRod package HotRod QFN package Flip-chip design reduces parasitic elements Thermal vias placed in PGND strip for heat removal " PCB ground planes act as a heat sink " Aids ground return currents Bottom-up view of TPS54A20 3.5x4 mm Pin assignments (top-down view) 1-24

19 Board layout tips Place input cap and series cap right next to the IC Place gate drive and bootstrap caps close to the IC Example layout diagram Insert thermal vias on the PGND stripe o Connects to internal power ground planes o Improves thermal dissipation o Provides good ground return path 1-25

20 Where s the Heat? Test condition: 12 V IN, 1.2 V OUT, 10 A, 2 MHz/phase, temp measured in C Series capacitor Inductors Integrated converter Inductors have relatively low loss and not a thermal bottleneck 1-27

21 Total solution size Inductor on 10-A buck EVM 10.2 x 10.2 x 4.7 mm = 489 mm 3 10-A series cap buck prototype 16 x 10 x 1.85 mm = 296 mm 3 The total solution size is 65% smaller in volume than just the inductor on a competitor s 10-A evaluation module! 1-28

22 Summary High-frequency (HF) operation of switching converters enables size reduction and performance improvements Buck converters have fundamental limitations that limit HF operation The series capacitor buck converter has unique properties that support HF operation Design guidelines for an HF series cap buck converter demonstrate the ease of implementation 1-29

23 Reduced switching loss Reduced switch voltage/ current overlap loss Loss due to switch output capacitance reduced by 67% Enables higher frequency operation Energy loss per switching cycle 1-12

Robust to variations in L, DCR Output Current (A) I LA (1A/div) I LB (1A/div) P.S. Shenoy, et al.

24 Auto current sharing Current Sharing: La 100 nh, Lb 200 nh Series cap forms average current feedback mechanism o Inductors charge/discharge cap o Charge balance maintained Inductor Current (A) ILa ILb Robust to variations in L, DCR Output Current (A) I LA (1A/div) I LB (1A/div) P.S. Shenoy, et al., Automatic current sharing mechanism in the series capacitor buck converter, in Proc. IEEE Energy Conversion Conf. Expo., Sept

25 Measured efficiency comparison Efficiency (%) MHz, TPS54A20 530kHz, TPS Output Current (A) Conditions: o 12 V IN, 1.2 V OUT o Room temp, no air flow Higher efficiency over the load range Inductors selected for equivalent DCR Higher peak efficiency at ~4 times the switching frequency 1-17

26 Transient response Load step-up V OUT (20 mv/div) 2 µs/div Load step-down V OUT (20 mv/div) I LA, I LB (2 A/div) I OUT (5 A/div) 2 µs/div I LA, I LB (2 A/div) I OUT (5 A/div) 12 V IN, 1.0 V OUT ; 500 A/µs full-load steps; 2 MHz per phase Deviation in V OUT <25 mv; recovery time <4 µs; F SW changes during transient Excellent dynamic current sharing 1-18

27 Choosing the switching frequency Increasing frequency can reduce inductance requirement o Helps reduce converter size VIN (max) 2V L I K O 2 O V IN (max) VO f o K = inductor current ripple percentage Tradeoff: efficiency decreases with increased switching frequency SW Efficiency (%) 12 V IN, 1.2 V O Efficiency Comparison MHz 3.5MHz 65 5MHz Output Current (A) 1-19

28 Inductor impact on efficiency Higher inductance tends to increase peak efficiency o Lower core loss o Lower RMS currents Lower inductance has higher full load efficiency o Lower winding resistance o Assumes same inductor size Comparison using 3.2x2.5x1.2 mm inductors, same vendor Efficiency (%) V IN, 1.2 V O, 2 MHz/phase 250nH 330nH 470nH Output Current (A) 1-20

29 Input and output capacitor selection The output caps impact o Steady-state voltage ripple o Closed-loop bandwidth o Load transient performance C Ex: ΔI O,MAX = 10A, L = 220 nh, Vo = 1.2 V, ΔV O,MAX = 36 mv 2 2 ( Io,max ) L (10A) 220nH 4V V 4(1.2V)(0.036V) o, min o o,max Input cap selected based on allowed voltage ripple o Steady-state ripple o Deviation during a load transient 127μF Magnitude (db) Phase (degrees) Bode plot: 12 V IN, 1.2 V OUT Co=91uF Co=138uF 219 khz 319 khz ,000 Frequency (khz) Co=91uF Co=138uF ,000 Frequency (khz) 1-22

Board layout example Switching Loop A Switching Loop B Compact layout o Lower switching & conduction loss o Small switch nodes lower EMI Reduces parasitic inductance by

30 Board layout example Switching Loop A Switching Loop B Compact layout o Lower switching & conduction loss o Small switch nodes lower EMI Reduces parasitic inductance by minimizing switching loop area o Reduces switching loss and voltage stress o Power stage and bootstrap caps Example converter layout Ensures good ground return path o Ground planes 1-26

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