Modelling of Low Inductive Busbars for Medium Voltage Three-level NPC Inverter

Transcription

1 Modelling of ow Inductive Busbars for Medium Voltage Three-level NPC Inverter. Popova, T. Musikka, R. Juntunen, Student Member, IEEE, M. ohtander, P. Silventoinen, O. Pyrhönen, J. Pyrhönen, Member, IEEE Φ Abstract--Design of low inductive busbars for medium voltage Neutral Point Clamped (NPC) inverter is studied. In a hard-switched inverter the stray inductance causes various problems, such as over voltages, current unbalance, and possible resonance with DC-link capacitors. These problems lead to improper operation of the inverter and an increased level of electromagnetic interference (EMI). The laminated busbars are known to be a good solution for minimizing the stray inductance. It is important to estimate and minimize the stray inductance of the busbars in an early design stage. FUX3D is used to compare three physical layouts and analyze the influence of the placement of the main circuit components on the inductance value. Index Terms--Converters, electromagnetic interference, electromagnetic modelling, finite element methods, inductance. D I. INTRODUCTION EVEOPMENT of wind turbines with power ratings more than 3 MW has brought new challenges to the designers of power converters. In such high power wind turbines with 690 V generator voltages, the current level reaches very high levels. High current requires large cables and brings more cost and decreases the reliability of the system. This causes the overall system to be more expensive and complex. From this point of view medium voltage converters, in which the voltage is increased up to 3-10 kv [1], have become more and more attractive. Multilevel topologies are particularly suitable for high power medium voltage converters due to the advantages of relatively lower line-to-line voltage steps and lower harmonic content in the output voltage. As a result the switching stress and the Electromagnetic Interference (EMI) are low [2], [3]. Results of implementation of three-level NPC inverters in wind generation systems are reported e.g. in [4]-[6]. Medium voltage NPC-converters have traditionally been built using different thyristors as main circuit components. Their turnoff times are so long that no special problems related to the This work was supported by the European Regional Development Fund (ERDF) and European Social Fund (ESF) in Finland. The Managing Authority of ERDF and ESF in Finland is the Ministry of Employment and the Economy.. Popova, T. Musikka, R. Juntunen, P. Silventoinen, O. Pyrhönen, J. Pyrhönen are with the Department of Electrical Engineering, appeenranta University of Technology, appeenranta 53851, Finland ( iudmila.popova@lut.fi; Tatu.Musikka@lut.fi; Raimo.Juntunen@lut.fi; Pertti.Silventoinen@lut.fi; Olli.Pyrhonen@lut.fi; Juha.Pyrhonen@lut.fi). M. ohtander is with the Department of Metal Technology, appeenranta University of Technology, appeenranta 53851, Finland ( mika.ohtander@lut.fi). DC-link topology have been present. Medium voltage IGBTs, however, are much faster than thyristors and therefore new effort has to be put on the converter geometry. In this particular research the laminated busbars for a multi-megawatt medium voltage three-level NPC inverter are studied both from the manufacturing and electromagnetic points of view. II. NPC INVERTER Nowadays NPC inverters are applied in various applications from low-power low-voltage to high-power and medium-voltage. The main idea in all neutral-point-clamped topologies is that the phase output is clamped to the DC-link neutral point through semiconductor switches. Fig. 1 illustrates one phase leg of an NPC inverter. As it can be seen from the figure, there are several current paths from the DC-link to the phase output and this makes the execution of low inductive busbar design more complicated than in an NPC inverter s traditional two-level counterpart. The NPC topology itself is well known and widely covered in the literature. Its general operation principles are presented e.g. in [7] and [8]. A. Topology and Operation Principles In the NPC topology, a phase output can be connected to +U DC /2, 0, or U DC /2 potentials by controlling the semiconductors S x1 4 in a desired way. By a proper modulation method, almost sinusoidal electrical machine currents can be achieved. Connection to +U DC /2 potential with a positive phase current current from DC-link to phase output takes place through switches S x1 and S x2. Whereas the same connection is realized through D x1 and D x2 with opposite current direction. Similar procedure takes place with U DC /2 potential but naturally through the lower switches of the phase arm. Thus S x3 and S x4 are used with negative current direction and D x3 and D x4 with positive current direction. Further, connection to zero or Neutral Point (NP) is realized through D x5 and S x2 or D x6 and S x3 depending on current direction. In many practical applications straight commutation from +U DC /2 to U DC /2 is denied or at least it is infrequent so commutations from +U DC /2 or U DC /2 to NP, or vice versa, will be treated in this article. Moreover, it can be assumed that the upper and the lower half of the phase arm commutate symmetrically, therefore discussion of one of /12/$ IEEE

2 those is enough. When the potential of the phase output is changed from +U DC /2 to NP with positive output current direction current commutates from S x1 to D x5 and commutation loop A in Fig. 1 is formed. ater this loop is called the short commutation loop. If current direction is reversed the commutation happens between D x1 and S x3, and thus commutation loop B is formed. This loop can be called the long commutation loop [9]. model for the busbar conductor is needed if the one quarter of the wave length of the highest critical frequency f c is around the same as the dimensions of the busbar. In other words the lumped parameter transmission line model is needed when a standing wave occurs in the conductor. R B UDC/2 C1 +UDC/2 0 C2 B A NT Dx5 P Sx1 AD1 Sx2 Dx1 Dx2 Ph c ESR C R B D c ESR C UDC/2 C3 -UDC/2 C4 Fig. 1. One leg of a three-level NPC inverter with example of commutating routes. P positive busbar N negative busbar NT-neutral busbar Ph phase out busbar AD1 additional busbar of upper phase arm AD2 additional busbar of lower phase arm Dx6 B. Commutation oop Inductances Non-idealities in the conductors and components along a commutation path create a case specific commutation inductance. Cutting off an inductive current causes voltage spikes over the component which performs the cut-off. The most common problem caused by these spikes is a switching component overvoltage break down. The overvoltage spike is estimated by U = di dt AD2 N Sx3 Sx4 Dx3 Dx4 spike (1) where U spike is the voltage spike during turn-off, is the stray inductance of commutation loop, and i is the current through the commutation loop. The case specific commutation inductances for both A and B commutation loops consist of the inductance of the busbars in the loop B, the equivalent series inductance of the DC-capacitor C, inductance of the IGBTs IGBT and inductance of the diode D. Fig. 2 presents simplified equivalent circuits for both commutation loops. According to [10] a lumped parameter transmission line A B D Fig. 2. Simplified equivalent circuits for commutation loop inductances for both the short (A) and long loop (B). The critical frequency is defined by the switching device fall time t f. For instance if medium voltage IGBT s fall time t f = 480 ns the corresponding wave length for a standing wave is around = 226 m, which means that the transmission line model is not needed for the inductance modelling. III. BUSBARS DESIGN The aim of the designer is to keep the inductance of every commutation loop within allowed limits, so that the safety limits of the devices are not exceeded during operation. It is important to reduce all inductances, which contribute to the total stray inductance of the commutation loop. The inductance of the power components are provided by manufactures and devices with low inductance are preferred. The designers of the converter can minimize the inductance of the busbars, which connect the components. The structure consisting of two and more parallel conducting plates and thin insulation layers between (Fig.3) is known to be optimal solution for this purpose [11], [12]. Fig. 3. 3D view of the busbar structure. During the design of the converter it is important to find

3 the means to estimate the stray inductance in an early design stage. It allows making appropriate adjustments for decreasing the stray inductance. So the layout with minimum stray inductance can be chosen for the manufacturing. A. Analytical Analysis The different aspects of the busbar design are discussed in details in several papers [13]-[15]. Mathematical analysis was performed to realize the factors, which have an influence on inductance value [16], [17]. Based on the conducted research, the inductance can be minimized by decreasing the separation between the conducting plates and the length of current loop, increasing the width of conducting plates, placing the connections in line with the main current flow. However, the compliance with these basic rules does not guarantee the minimum inductance. Thorough analysis of each particular design is required in order to take into account the influence of the arrangement of the components, skin effect, and proximity effect. In this case exact analytical calculations become very complicated and bulky. Various numerical modelling tools are extensively used for the inductance estimation. B. FEM Modelling Among various numerical methods the inductance calculation dedicated tools utilizing Partial Element Equivalent Circuit (PEEC) method has shown great ability to determine the inductance of complex geometries [18], [19]. Also three-dimensional finite element models (FEM) are known to be effective tool for electromagnetic modelling [15]. The FUX3D software by Cedrat is a package for three dimensional analysis of electric and magnetic fields based on the finite element method [20]. 3D FEM modelling using steady state AC magnetic application is performed in this paper. This application allows modeling the skin and proximity effects in solid conductors. The proximity effect is related to the phenomena that are produced when, in a system consisting of several current carrying conductors, the magnetic field generated by a conductor perturbs the current distribution in other conductors [21]. Both of these effects take place in inverter and must be considered during the inductance estimation [22]. In order to have an accurate evaluation of the physical quantities in the skin region at the surface of the conductor: you must to have at least two layers of mesh elements in the thickness of this region [21]. To compute the inductance of the busbars forming the commutation loop, the magnetic energy in the entire space W m and the RMS value of the current I flowing in the loop have to be known. 2 W I = (2) m 2 The magnetic energy is obtained by integration of the magnetic energy density over the finite element domain, while the current is specified in the external circuit. The power components are excluded of the modelling, since the inductances of these components are provided by the manufacturer. Three layouts (Fig. 5, Fig. 6, and Fig. 7) are modelled using FUX3D in this paper in order to analyze the influence of the location of the DC-link capacitors and the power components on the stray inductance of the commutation loops. C. aminated Structure One lamination scheme (Fig.4) is used in three layouts considering in the paper to ensure that the placement of the components is the only factor which affects the inductance value. It means that the order of the busbars in the structure is identical. The positive and negative busbars are located in the same plane on the neutral busbar. This arrangement is chosen taking into account that currents during the transition times flow in the positive and neutral busbars in the upper phase arm and in the negative and neutral busbars in the lower phase arm. So the distance between these busbars is minimized and equal to the thickness of the insulation layer. There is no need to laminate the positive and negative busbars, since they are not included in the same commutation loops. The additional busbars of the upper and lower phase arms are the top busbars. And the phase out busbar is at the bottom. The thickness of copper (3 mm) and the thickness of insulation layer (1 mm) are also the same in three layouts. Fig. 4. Principal cross sectional view of the laminated busbar structure. This staircase structure is also preferred from the heat transfer point of view. A better heat dissipation is achieved due to contact of the inner layers with the ambient. In the converter with high power, a considerable amount of heat is generated during operation. If the heat is not removed efficiently, the temperature limits of the insulation can be exceeded. This leads to various undesired phenomena in the insulation material, which cause the loss of dielectric property. In the layered structure the main thermal problem is in a low thermal conductivity of the insulation material. Therefore, the solution is to use the insulation material with a higher thermal conductivity. Hence, the thermal resistance of the structure is small.

4 D. ocation of the Components The physical locations of the components in the inverter should be optimized in such a way that the stray inductance can be minimized. Three mechanical layouts with different locations of the main circuit components relative to each other are taken into consideration. In ayout 1 (Fig. 5) the DC-link capacitors are located in the centre [12]. The power components of the upper phase arms of three phases are placed from one side of DC-link and the power components of the lower phase arms of three phases are from the other side of DC-link. T x1 x4 are the IGBT modules, which consist of IGBTs S x1 x4 and freewheeling diodes D x1 x4. This arrangement provides equal commutation current loops in the upper and lower phase arms of the phase leg and between the phase legs. So, the voltage stresses of the components in three phase legs are almost equal. The short and long commutation loops of the upper phase arm are shown in Fig. 3. The lower phase arm has symmetrical commutation loops. The dimensions of the ayout 1 are mm 3 (l w h). In ayout 2 (Fig. 6) two upper capacitors of the DC-link - C1 and C2 are located between the clamping diodes and the IGBT modules of the upper phase arms and two lower capacitors - C3 and C4 are placed between the clamping diodes and the IGBT modules of the lower phase arms. In ayout 2 the length of the long commutation loop is shorter than in ayout 1 and, consequently, the stray inductance is expected to be lower. The dimensions of ayout 2 are mm 3 (l w h). For the further minimization of the length of the long commutation loop, the distance between the switching components of the upper and lower phase arm should be minimized. Therefore, ayout 3 is introduced. Fig. 6. (a) Top view of ayout 2 (b) cross section view of busbar structure of ayout 2 with the short (green) and long (red) commutation loops. Fig. 5. (a) Top view of ayout 1 (b) cross section view of busbar structure of ayout 1 with the short (green) and long (red) commutation loops. In ayout 3 (Fig. 7) all switching components are located in the centre, the DC-link capacitors - C1 and C2 are on one side and the DC-link capacitors - C3 and C4 are on the other side. The dimensions of ayout 3 are mm 3 (l w h). All three layouts have symmetrical short and long commutation loops in the upper and lower phase arms. It should be noted that during the modelling of the busbar structure the holes, made to connect the terminals of power

5 devices to the busbar and to support the structure are treated differently. The holes made in the middle of the busbar have minor effect on the stray inductance and can be excluded from the model. While the influence of the holes near the edges on the stray inductance can be significant and exclusion of these holes leads to erroneous estimation of the stray inductance [14]. During the simplification of the model it is important to consider the effect of the excluded part on the inductance value. ayout 1 has the lowest stray inductance of the busbars of the short commutation loop. Since the performance is limited by the worst possible case, the inductance of the long commutation loop has to be minimized for optimization. Therefore, ayout 3 is preferred (Fig. 9 and Fig. 10). Fig. 8. Normalized stray inductances of three layouts with the long commutation loop stray inductance of ayout 3 value of 100 %. Also the inductances of the long and the short commutation loops for each phase leg are estimated. Small variations of the inductance in each phase leg are ensured due to symmetrical positioning of the DC-link capacitors. Therefore, the stresses on the devices in each phase leg are almost equal. Fig. 7. (a) Top view of ayout 3 (b) cross section view of busbar structure of ayout 3 with the short (green) and long (red) commutation loops. E. Results of Modelling Three-dimensional finite element software FUX3D has been used to estimate the inductances of the busbars of the short and long commutation loops in each layout. The inductances estimated using FEM models are normalized to the long commutation loop inductance of ayout 3 and presented in Fig. 8. As shown in the results, ayout 3 has the lowest stray inductance of the busbars of the long commutation loop and Fig. 9. 3D view of laminated busbar structure of ayout 3.

6 V. REFERENCES Fig D view of ayout 3. The stray inductance of the busbars of the short and long commutation loops of ayout 3 are: B S =21.25 nh, B =54.89 nh. The total inductances of the short and long commutation loops are: Short = D + + B σs + C = nH σ (3) ong = D Bσ + C = nH σ (4) D is the inductance of the diode module, IGBT is the inductance of the IGBT module, and C is the inductance of the capacitors (Fig. 2). These values are taken from the datasheets of the components. The inductance associated with screw connections to the power components also contributes to the total loop inductance and should be taken into account. IV. CONCUSIONS In this paper the development of low inductive busbars for medium voltage three-level NPC inverter is considered. The electromagnetic modelling is applied as design support tool. It helps a designer to explore possible variations of the geometry of the inverter to achieve the minimum stray inductance of the busbars. The results of the modelling showed that the stray inductance value varies considerably between the different layouts. The layout with minimum stray inductance significantly improves the electromagnetic compatibility (EMC) performance of the inverter and decreases the stresses on the switching components. [1] iang Zhang, Xu Cai, "A Novel Multi-level Medium Voltage Converter Designed for Medium Voltage Wind Power Generation System," Power and Energy Engineering Conference (APPEEC), 2010 Asia-Pacific, vol., no., pp.1-4, March [2] Wu B.: High-Power Converters and AC Drives, Piscataway, NJ, IEEE Press, [3] Rodriguez J., Bernet S., Wu B., Pontt J. O., Kouro S., "Multilevel voltage-source-converter topologies for industrial medium-voltage drives, " IEEE Transactions on Ind. Appl. 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7 level universal inverter module with specifically designed busbar," Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE, vol., no., pp , Feb VI. BIOGRAPHIES iudmila Popova received the M.Sc. degree in electrical engineering from appeenranta University of technology (UT), appeenranta, Finland and SPbETU "ETI", Saint-Petersburg, Russia in She is PhD student in the Department of Electrical Engineering at appeenranta University of Technology. Her main research interest is in the field of combined simulation of electrical drives. Tatu Musikka received the M.Sc. degree in electrical engineering from appeenranta University of Technology (UT), appeenranta, Finland in Also in 2010 he started his PhD studies concerning semiconductor losses and thermal modeling of multilevel inverters. His current interests are research and modeling of parasitic effects in electric drives. Raimo Juntunen (S 10, GS 12) received the M.Sc. (Tech.) degree in electrical engineering from appeenranta University of Technology (UT), appeenranta, Finland in In 2011 he started his PhD studies concerning control and filtering in multi-level voltage source inverters. Mika ohtander received the M.Sc. degree in mechanical engineering, the icentiate of Science (technology) degree, and D.Sc. (technology) degree from appeenranta University of Technology (UT), appeenranta, Finland, in 1999, 2007, and 2010, respectively. He is currently a researcher in the department of Metal Technology. His special areas of interest cover sheet metal design and manufacturing and he is specialized to boundary area of design and manufacturing. Main activities are to find common factors from both (design and manufacturing) entities and make descriptions that utilization of design/manufacturing architecture will realize commercial software s. Pertti Silventoinen was born in Simpele, Finland, in He received the D.Sc. degree from appeenranta University of Technology (UT), appeenranta, Finland, in He became a Professor of Applied Electronics in He is currently the Head of the Degree Program in Electrical Engineering at the Institute of UT Energy. His current interests include power electronic systems in various applications. Olli Pyrhönen received the M.Sc. and D.Sc. degrees in Electrical Engineering in 1990 and 1998 from appeenranta University of Technology (UT), Finland. He has been Professor in Applied Control Engineering since 2000 at UT. In 2010 he received further teaching and research responsibility in the wind power technology at UT. He has gained industrial experience as a R&D Engineer at ABB Helsinki in and as a CTO of The Switch in He has published about 80 papers in the control of electrical drives, power electronics and other industrial applications. Juha Pyrhönen (M 06) received the M.Sc. degree in electrical engineering, the icentiate of Science (technology) degree, and D.Sc. (technology) degree from appeenranta University of Technology (UT), appeenranta, Finland, in 1982, 1989, and 1991, respectively. He was an Associate Professor in electric engineering with UT in 1993 and has been a Professor in electrical machines and drives since in From 1998 to 2006, he was the Head of the Department of Electrical Engineering. He is active in the research on and development of electric motors and electric drives.