Design and Modeling of Low-Inductive Busbars for a Three-Level ANPC Inverter

Transcription

1 Design and Modeling of Low-Inductive Busbars for a Three-Level ANPC Inverter L. Popova 1, T. Musikka 1, R. Juntunen 1, M. Polikarpova 1, M. Lohtander 2, J. Pyrhönen 1 Abstract Laminated busbars are extensively used to connect components in hard-switched power inverters due to their low stray inductance. The objective of this paper is to demonstrate the design procedure and modeling of laminated busbars of a three-level three-phase Active Neutral Point Clamped (ANPC) inverter, with special emphasis placed on ensuring low stray inductance at an early design stage. In the paper, the partial inductances of the busbars are estimated using an ANSYS Q3D software tool. The stray inductance of the commutation loops is determined analytically and by cosimulation with ANSYS Simplorer and Q3D. Cosimulation allows analysis of the influence of the stray inductance on the performance of the inverter. The modeling results show that the laminated busbars proposed in this paper have low stray inductance. The stray inductances of the commutation loops were measured before the inverter is assembled to verify the modeling results. The approach used reduces the need for late-stage modifications based on prototype testing. Keywords: Busbars, converters, impedance measurement, inductance Nomenclature Symbols C f i L p L M u Capacitance Frequency Current Self partial inductance Stray inductance Mutual partial inductance Voltage Subscripts c capacitor cr critical h half r resonance tot total w wire Acronyms 3D Three dimensional AC Alternating current ANPC Active neutral point clamped CAD Computer-aided design DC Direct current FEM Finite element method IGBT Insulated gate bipolar transistor MOM Method of moments PEEC Partial element equivalent circuit I. Introduction In hard-switched power inverters, parasitic inductances distributed within the inverter can cause problems during operation of a switching module [1]. A voltage spike u spike from discharging the stray inductance occurs across the semiconductor switch during fast switch-off u spike di dt where L is a commutation loop stray inductance and i is a current in the commutation loop [2]. The current slope is determined by the fall time of the device. As manufacturers produce faster devices with lower switching losses [3], the voltage spike increases proportionally, which may lead to the voltage rating of the device being exceeded and consequential damage to the power semiconductor switch. The applied switching current thus has to be limited to prevent such damage, which decreases the converter power capability [4]. Designers of power inverters consequently face the challenge of designing inverters in which the stray inductances of the commutation loops are minimized. This objective can be achieved by using components with low stray inductance and low inductive connections. Laminated busbars are extensively used in power electronics to connect the main circuit components because of their inherently low stray inductance [5], [6], [7]. (1)

2 While the design of the busbars for a traditional twolevel inverter which has only one commutation loop is quite straight forward, the designs of laminated busbars for multilevel topologies, which nowadays are of great interest [8], [9], easily become complicated when the number of levels, power components, and commutation loops increases. As a result, busbar design and analysis becomes complex and demanding [10]. In this paper, the design procedure of the busbars for a three-level, three-phase ANPC inverter is presented. Relevant aspects such as the selection of the number of the busbar layers and the arrangement of the inverter s components to minimize the difference between the stray inductance values of the commutation loops are discussed. NPC is currently one of the most commonly used multilevel topology in the industry. There is a modified version of the NPC topology called ANPC in which the neutral clamping diodes are replaced by clamping switches. ANPC has received attention due to its ability to control the distribution of losses among the devices. A practical design of the busbars for the ANPC is associated with some difficulties caused by the presence of several commutation loops. When several commutation loops exist in the inverter, the difference between their stray inductance values may be rather significant. Consequently, the voltage spikes experienced by certain switching devices are considerably higher than experienced by the others. Since the allowed switching current of the devices is selected in such a way that the highest voltage spike is within the permitted limits, the switching devices with lower voltage spikes are thus de-rated. This creates one more requirement of the busbars which, in addition to the low inductance value, is that the difference between the busbars stray inductance of different commutation loops should be minimized. Numerical modeling widely used in the design of inverters [11], [12] is applied. Suitable tools would permit the inductance of complicated busbar structures to be accurately estimated and would allow modifications to reduce the stray inductance to a safe value to be made at an early design stage rather than when the inverter prototype has already been built. This paper is organized as follows. Section II discusses the operation principles of the ANPC topology and the current loops formed during commutations. In Section III, the physical locations of the main circuit components in the inverter are assessed. The execution of the laminated busbar design is described in detail in this section. Section IV is dedicated to numerical modeling of the laminated busbars and cosimulation with Simplorer and Q3D. Finally, the measurements performed to verify the modeling results are presented in Section V. II. ANPC inverter An Active Neutral Point Clamped (ANPC) inverter has been introduced in [13], [14] as a modified version of the Neutral Point Clamped (NPC) inverter that was presented in [12]. The main drawback of the NPC topology is uneven loss distribution between the switching devices. In the ANPC topology, the additional active switches, S x5 and S x6 are connected antiparallel (Fig. 1) to the diodes, D x5 and D x6, respectively, to enable new switch states and provide more even loss distribution. II.1. Inverter commutation loops In the ANPC inverter, direct commutation between the Positive (P) and Negative (N) states is avoided. Therefore, all commutations are made through the Neutral Point (NP) state [15]. The commutations between the P and NP states, and the N and NP states are described in detail in [13]. It is assumed that the lower and upper phase arms commutate symmetrically, hence only the upper phase arm is considered further. Despite the considerable number of different commutations that can be used to distribute the switching losses among the switching devices, two basic commutation loops can be determined. When a commutation takes place between P and NPU1 or NPU2, commutation loop A is formed (Fig. 1). If the commutation occurs between P and NPL1 or NPL2, commutation loop B is formed (Fig. 1). Fig. 1. One phase leg of the ANPC inverter with the commutation loop A and B. P positive busbar N negative busbar NT neutral busbar Ph phase out busbar A1 additional busbar of the upper phase arm A2 additional busbar of the upper part of DC link A3 additional busbar of the lower phase arm A4 additional busbar of the lower part of DC link II.2. Stray inductance of commutation loops Each component of the inverter has a parasitic inductance that contributes to the inductance of the commutation loop. The total inductances of the commutation loops A and B can be calculated as

3 L L (2) loopa DC _ link_h 2 IGBT busbarsa (3) loopb DC _ link_h 4 IGBT busbarsb The values of the stray inductances of the IGBT modules and the capacitors are taken from the datasheets of the components. The stray inductance of the IGBT module (T x) L IGBT containing one IGBT (S x) and one diode (D x) is 16 nh. Each DC link capacitor has a parasitic inductance L c of 20 nh. The DC link consists of 16 capacitors that are connected as shown in Fig. 1. The total stray inductance of the DC link capacitors L DC_link is 20 nh and the stray inductance of half of the DC link L DC_link_h is 10 nh. The stray inductance of the busbars L busbars is not known and should be estimated using analytical or numerical methods to determine the total stray inductance of the commutation loops. In order to reduce the inductance of the commutation loops, components with low stray inductance have to be selected. Manufacturers try to minimize the stray inductance of the capacitors and switching components [16], [17]. However, to benefit from the low inductance of the switches and capacitors, the inductances of the busbars also have to be minimized. Laminated busbars are widely used to connect components because of the inherent low stray inductance of such a construction. The laminated busbar structure consists of several planar busbars with thin insulation layers between them, providing only a limited surface area for build-up of the stray flux. From a thermal point of view, the advantage of this structure is better heat dissipation because of the larger contact area with the ambient air. III. Design of low inductive busbars Commutation loop A consists of four busbars, and commutation loop B contains six busbars. According to the theory of partial inductance [18], each busbar of the commutation loop can be characterized by self partial inductances and mutual partial inductances. A comprehensive description of the theory of partial inductance is presented in [18]. Loop inductance can be calculated when the self partial inductances of each busbar of the loop and the mutual partial inductances between the busbars are known. Analytical formulas for calculation of the partial inductance for different conductors are presented in [19], [20]. The difference between the concepts of loop and partial inductances is explained in detail in [20]. Low inductance of laminated busbars is achieved by decreasing the self partial inductance of each busbar and increasing the mutual partial inductance between busbars in which the current flows in opposite directions. The self partial inductance L p is decreased by increasing the width of the busbar and decreasing the length [21]. The mutual partial inductance between the busbars, M is increased by placing the busbars close to each other. If the current flows in opposite directions in the busbars, the mutual partial inductance is subtracted from the loop inductance. The mutual partial inductance approaches the value of the self partial inductance when the distance between the busbars is minimized. This high negative mutual partial inductance allows considerable decrease in the loop inductance and this effect is used in the laminated busbars of the ANPC inverter to decrease the inductance of the commutation loops. III.1. Laminated structure Fig. 2 presents a cross-sectional view of the laminated busbar structure used to connect the components in the ANPC inverter. The order of the busbars is chosen such that the inductances of the commutation loops are minimized. Fig. 2. Cross-sectional view of the laminated busbars. Busbars included in the same commutation loops are laminated to minimize the distance between busbars in which the current flows in opposite directions. This helps to reduce the loop inductance by increasing the subtractive mutual partial inductance between the busbars. The positive busbar is placed above the neutral and A2 busbars because the current in the commutation loops A and B flows in the positive busbar in one direction and in the A2 and NT busbars in the opposite direction. This placement minimizes the distance between these busbars to the thickness of the insulation. For the same reason, the negative busbar is located above the A4 and NT busbars. There is no need to laminate busbars that are not included in the same commutation loops. Consequently, the P and N busbars are located in the same plane similarly as the additional busbars A2 and A4. III.2. Location of the components The physical location of the components in the inverter is selected to minimize the length of the commutation loops. In the layout presented in Fig. 3, all the switching components are located in the center, the upper part of the DC link (C1-C8) is on one side and the lower part of the DC link (C9-C16) is on the other side. This configuration is chosen because the upper part of the DC link is included only in the commutation loops of the upper phase arms and the lower part of the DC link is included in the commutation loops of the lower phase

4 arms. The IGBT modules T x1 and T x2 are located close to the upper part of the DC link (C1-C8) and T x3 and T x4 are placed close to the lower part of the DC link (C9- C16). This arrangement allows the length of commutation loop B to be decreased. This is done by increasing the distance between the IGBT module T x5 and the upper part of the DC link and, consequently, by increasing the length of commutation loop A. The distance between the IGBT module T x6 and the lower part of the DC link is also increased. But since commutation loop B contains more switching components, it has a higher total stray inductance than the inductance of commutation loop A. Fig. 4 shows a 3D view of the ANPC inverter. This arrangement provides equal commutation loops in the upper and lower phase arms and between the phase legs. Fig. 4. 3D view of the ANPC inverter. Fig. 3. Top view of the inverter layout with the commutation loops of the upper and lower phase arms of phase B. IV. Inductance estimation The laminated busbar structure considered in this paper has a complicated geometry with multiterminal connections. For the analytical estimation of the inductance, it has to be subdivided into a number of smaller elements having a simple geometry. This procedure increases the number of calculations considerably. Further, it is necessary to estimate the inductance at the highest critical frequency f cr (1.2 MHz) associated with the IGBT fall time (130 ns) when the voltage spike occurs [21]. At this frequency, the skin effect is significant. The proximity effect is also pronounced for planar conductors located very close to each other as in the presented structure. These two effects influence the current distribution in the busbars and thereby the inductance value [21]. In light of the importance of consideration of the skin and proximity effects, the analytical calculations become complicated and laborious. With the increasing computational capabilities of modern computers, numerical modeling tools that allow consideration of the skin and proximity effects are increasingly being used. Numerical tools based on the Partial Element Equivalent Circuit (PEEC) method have shown good performance in calculating the inductance of complex geometries [22], [23], [24], [25]. Similarly, tools that use Finite Element Method (FEM) to solve Maxwell s field equations have been effectively used for inductance estimation [26], [27]. A FEM-PEEC coupled method is presented in the literature [25]. All these methods allow modeling of the skin and proximity effects. In this paper, ANSYS Q3D software is used for the inductance estimation of the laminated busbars. This 3D

5 numerical modeling tool is used for extraction of the resistance, partial inductance, capacitance and conductance. The Q3D extractor performs the electromagnetic field simulation by using a combination of FEM and the Method of Moments (MoM). The results provided by this tool take proximity and skin effects into account. As an example to explain inductance estimation using ANSYS Q3D, evaluation of commutation loop A of phase A is presented here. The switching components and capacitors are excluded from the modeling because the inductances of these components are provided by the manufacturers. The self partial and mutual partial inductances of the busbars P, A1, A2, and NT are estimated. The geometry of the laminated busbars is imported from the Computer-Aided Design (CAD) tool. An AC analysis is performed to calculate the inductance at different frequencies. Fig. 5 shows the surface current distribution on the neutral busbar at f cr=1.2 MHz. A mesh with triangle elements was created for the AC analysis. The results in Table I show that a high negative mutual partial inductance between the busbars is obtained by placing them close to each other. These subtractive mutual partial inductances help to minimize the loop inductance. The mutual partial inductance between busbars in which the current flows in the same direction is kept low. Fig. 6 shows the equivalent circuit of commutation loop A, where each busbar has a self partial inductance and mutual partial inductances. M P,A2 L pp L pa2 M P,A1 I M A2,A1 M P,NT I M A2,NT L pa1 M A1,NT L pnt Fig. 6. Commutation loop A with four busbars. The equivalent loop inductance of the busbars L busbarsa can be calculated analytically by the following formula using dot convention: L busbarsa P,A2 pp A1,NT pa1 pa2 A1,A2 pnt P,NT P,A A2,NT nh.(4) Fig. 5. Surface current density distribution on the neutral busbar (NT). Table I presents the partial inductance matrix of the busbars forming commutation loop A estimated by ANSYS Q3D at the critical frequency (1.2 MHz). The diagonal elements of the matrix are the self partial inductances of the busbars L p, and the off-diagonal elements are the mutual partial inductances M between the busbars. The sign of a mutual partial inductance depends on the direction of the current. The mutual partial inductance between busbars in which the current flows in opposite directions is negative. If the current flows in two busbars in the same direction, the mutual partial inductance is positive. TABLE I SELF PARTIAL AND MUTUAL PARTIAL INDUCTANCES OF THE BUSBARS INCLUDED IN THE COMMUTATION LOOP A (AT 1.2 MHZ) Inductance [nh] P A1 NT A2 P A NT A In addition, the loop inductances of the busbars of the other commutation loops were calculated, and the results are presented in Table II. TABLE II STRAY INDUCTANCES OF THE LAMINATED BUSBARS OF THE COMMUTATION LOOPS Estimated inductance [nh] Frequency 10 khz Frequency 1.2 MHz Phase A L busbarsa L busbarsb Phase B L busbarsa L busbarsb Phase C L busbarsa L busbarsb The stray inductance of the commutation loops can also be estimated by cosimulation with Simplorer and Q3D. Fig. 7 shows the Simplorer-Q3D cosimulation model. The model of the DC link and the ANPC inverter were created in Simplorer, and the busbars were modeled in Q3D and coupled to Simplorer. The

6 cosimulation makes it possible to focus on the model of the inverter and considers the influence of the parasitic components of the busbars on the performance of the inverter. To determine the stray inductance, the commutation loops are formed by short-circuiting the appropriate IGBT modules in the model. When the impedance versus frequency of the circuit created by the capacitance of half of the DC link C DC_link_h and the stray inductance of the busbars L busbars is known, the resonant frequency f r can be estimated. The stray inductance of the commutation loop is then calculated by 1 L busbars 2 [ H ]. (5) CDC_link_h (2 f r ) Fig. 7. Simplorer-Q3D cosimulation model. V. Experimental results To verify the modeling results, the inductances of the commutation loops were measured before the inverter was completely assembled. A frequency response analyzer, Venable 3120 was used to measure the impedance versus frequency of commutation loops A and B. The commutation loops exclude the IGBT modules and include only the DC link capacitors and the laminated busbars (Fig. 9). To form commutation loop A, the IGBT module T x5 was shorted by a small wire. The impedance was measured across the terminals of the IGBT module T x1 as shown in Fig. 9 and Fig. 10. Commutation loop B was formed by shorting the IGBT modules T x2, T x3, and T x6. The impedance was measured across the terminals of T x1. After the impedance versus frequency has been measured, correction for the test fixture parasitics is required. It is important to take into account the parasitics of the test setup because they can be significant at low and high impedance levels. In order to compensate for the parasitics of the test setup at low impedance levels, the impedance was measured with the commutation loop being short circuited. Then, the short circuit impedance was subtracted from the commutation loop impedance data [28]. As a result, the actual impedance of the commutation loop can be established, shown in Fig. 11. Fig. 8. Results of the impedance simulation of commutation loop A of phase A. Fig. 9. Photograph of the measurement setup. The capacitance of half of the DC link C DC_link_h is 8.2 mf. The impedance of commutation loop A is presented in Fig. 8. The resonant frequency of commutation loop A is Hz and the L busbarsa is 20.8 nh. This value is in agreement with the analytically calculated value (Eq. 4).

7 Fig. 10. Circuit diagram of the measurement setup. Fig. 12. Comparison of the estimated and measured stray inductances of the laminated busbars at 10 khz. The total inductances of commutation loops A and B are: L 62.5 nh (7) loopa DC_link_h 2 IGBT busbarsa L loopb DC_link_h 4L IGBT busbarsb nh, (8) Fig. 11. Results of the impedance measurement and simulation of commutation loop A of phase A. As shown in Fig. 11, the impedance of the commutation loop A reaches its minimum at the resonant frequency f r (8872 Hz) produced by the DC link capacitors and the total stray inductance L tot. The total inductance estimated by Eq. 5 is 39.2 nh. Fig. 11 also presents the results of the cosimulation with Simplorer and Q3D when the stray inductances of the capacitors are included in the model. The stray inductance of half of the DC link L DC_link_h (10 nh) and the stray inductance of the wire L w shorting the IGBT module (the estimated inductance is 6 nh) were subtracted from the total stray inductance to obtain the measured inductance of the laminated busbars L busbarsa_m where L busbarsa (20.8 nh) and L busbarsb (28.9 nh) are the stray inductances of the busbars estimated using ANSYS Q3D at 1.2 MHz (Table II). The expected voltage spike during cutting-off of the inductive current (200 A) of commutation loop A calculated by (1) is 96 V. The voltage spike corresponding to commutation loop B is 158 V. VI. Discussion The total stray inductances of the commutation loops are shown in Fig. 13 where the contribution of each component to the loop inductance is also presented. It is observed that the inductance of commutation loop B is larger than the inductance of loop A by 64% despite the efforts to minimize the difference between the inductances of the busbars of the loop A and B. L 23.2 nh. (6) busbarsa_m tot DC_link_h w Fig. 12 presents a comparison between the measured and estimated inductance values of the laminated busbars of loops A and B for each phase. In the comparison, the inductance is estimated at 10 khz because the resonance frequency is approximately this value. There is a good correlation between the estimated and measured results.

8 further reduced by adding snubber capacitors close to the IGBT modules. The approach presented in this paper is aimed to avoid costly modifications to mitigate the effect of the stray inductance when the inverter is built. Also it allows obtaining the stray inductance values which can be used in the circuit simulation tools to accurately model the performance of the inverter in a presence of the stray inductance. Fig. 13. Total inductance of commutation loop A and B. As shown in Fig.13, the contribution of the IGBT modules to the loop inductances is rather significant, particularly for commutation loop B which contains four IGBT modules. As the IGBT modules are connected in series in the commutation loops, their equivalent inductance is obtained as a sum of the stray inductances of the modules. In order to minimize the equivalent inductance of the IGBT modules, the mutual inductances between the modules should be considered. By utilizing the negative mutual inductances between the switching modules, the equivalent stray inductance can be further reduced. In this case, the modeling of the IGBT modules (which requires the knowledge of the module s internal structure), is needed to estimate the mutual inductances. This data is not typically provided by the manufacturers. VII. Conclusion This paper discussed the design of low-inductive laminated busbars for a three-level three-phase ANPC inverter. The commutation loops of the ANPC inverter were considered as a starting point of the inverter design. The physical location of the components was selected such as to decrease the length of the commutation loops. For that reason, the distance between components participating in the same commutation loops was minimized. The placement of the busbars in the laminated structure was selected to minimize the commutation loop inductances by increasing the subtractive mutual partial inductance between the busbars carrying current in opposite directions. A coupled Simplorer-Q3D model was created to evaluate the influence of the parasitic components of the busbars on the performance of the inverter. The impedances of the commutation loops were measured to verify the results of the cosimulation. The modeling and experimental results showed that the laminated busbars have a low stray inductance. The variation in the stray inductance values between the phases is quite small because of the symmetrical arrangement of the components in the inverter. As a result, the voltage stresses of the components in the three phases are almost equal. The voltage spikes can be References [1] I. Josifovic, J. Popovic-Gerber and J.A. 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Zare and G.F. Ledwich, Reduced layer planar busbar for voltage source inverters, IEEE Transactions on Power Electronics, vol. 17, no. 4, 2002, pp [27] Jih-Sheng Lai, Xudong Huang, E. Pepa, Shaotang Chen and T.W. Nehl, Inverter EMI modeling and simulation methodologies, IEEE Transactions on Industrial Electronics, vol. 53, no. 3, 2006, pp [28] Using the Venable Windows Software 4.0 For MODEL 3120, Venable Instruments, Austin, TX R. Juntunen received the M.Sc. (Tech.) degree in electrical engineering from Lappeenranta University of Technology (LUT), Lappeenranta, Finland in In 2011 he started his PhD studies concerning control and filtering in multi-level voltage source inverters. M. Polikarpova was born in 1985 in Severodvinsk, Russia, received the Specialist Degree in Industrial Heat and Power from Saint-Petersburg Technological University of Plant Polymers, Russia in 2008 and Master of Science (M.Sc.) degree from Lappeenranta University of Technology (LUT), Finland in She is currently a doctoral student in the Department of Electrical Engineering in LUT, where she studies heat transfer processes and cooling systems of electric motors and electric drives. M. Lohtander is a Researcher in the department of Metal Technology. Lohtander has developed in his doctoral thesis the manufacturability analysis method for small lot series production in sheet metal industry. Analysis method proposes manufacturing parameters based on part, tools, machines, materials and energy efficiency. His special areas of interest cover sheet metal design and manufacturing and he is specialized to boundary area of design and manufacturing. Main activities are to find common factors from both (design and manufacturing) entities and make descriptions that utilization of design/manufacturing architecture will realize commercial software s. J. Pyrhönen received the D.Sc. degree from Lappeenranta University of Technology (LUT), Finland in He became an Associate Professor of Electrical Engineering at LUT in 1993 and a Professor of Electrical Machines and Drives in He is currently the Head of the Department of Electrical Engineering, LUT, Finland, where he is engaged in research and development of electric motors and electric drives. His current interests include different synchronous machines and drives, induction motors and drives and solid rotor high-speed induction machines and drives. Authors information 1 Electrical Engineering Department, Lappeenranta University of Technology, P.O. Box 20, Lappeenranta 53851, Finland 2 Mechanical Engineering Department, Lappeenranta University of Technology, P.O. Box 20, Lappeenranta 53851, Finland L. Popova received the M.Sc. degree in electrical engineering from Lappeenranta University of technology (LUT), Lappeenranta, Finland and SPbETU "LETI", Saint-Petersburg, Russia in She is a doctoral student in the Department of Electrical Engineering at Lappeenranta University of Technology. Her main research interest is in the field of power electronics. T. Musikka received the M.Sc. degree in electrical engineering from Lappeenranta University of Technology (LUT), Lappeenranta, Finland in Also in 2010 he started his PhD studies concerning semiconductor losses and thermal modeling of multilevel inverters. His current interests are research and modeling of parasitic effects in electric drives.