Reference Design RD-408

Transcription

1 Reference Design RD Fairchild Motion SPM 45 LV Series This reference design supports design of Motion SPM 45 LV series. It should be used in conjunction with the Motion SPM 45 LV datasheets as well as Fairchild s application note (AN-9111). For more information, please visit Fairchild s website at Target Application Fairchild Device MOSFET Rating Motor Rating (1) Isolation Voltage Topology Small-Power Inverter, Power Tool FSB44104A 40 A / 40 V 0.8 kw FSB43004A 60 A / 40 V 1.2 kw V ISO = 800 V RMS (Sine 60 Hz, 1 min. Between all shorted pins and heat sink) 3-phase MOSFET inverter Notes: 1. This motor rating is a typical value and may change depending on the operating conditions. Key Features L Certified No.E (L1557). 40 V, R DS (ON) = 4.1 mω(max.) 3-Phase MOSFET Inverter Module with Gate Drivers and Protection. Low Thermal Resistance sing Ceramic Substrate. Three Separate Open-Emitter Pins from Low-Side MOSFETs for Three-Leg Current Sensing. Single-Grounded Power Supply for Built-in HVIC. Isolation Rating: 800 Vrms / min Fairchild Semiconductor Corporation 1 RD-408 Rev. 1.1

2 1. Block Diagram Reference Design For Motion SPM 45LV Series VDD VCC Master Board VIN(H) VDD BLDC Controller / MC VIN(L) Fault VSP GND CP05 5V 15V R LPF CP15 CP15 DP15 Motion SPM 45L Series Test Board D C CCDZD VB VCC(H) VIN(H) HVIC VS VIN(L) 5V RPF VCC(L) VFO CFOD CFOD LVIC COM CSC CSC C N NV P V W NW HNT N CDCS V W Motor VDC V Hall IC Signal Figure 1. Block Diagram of Application 2014 Fairchild Semiconductor Corporation 2 RD-408 Rev. 1.1

3 2. Schematic +15V R D C CF (22) V B(W) VB(W) P (1) M C Gating WH Gating VH Gating H R R D D C CF C CF (21) V S(W) (20) V B(V) (19) V S(V) (18) V B() (17) V S() (16) IN (WH) (15) IN (VH) (14) IN (H) VS(W) VB(V) VS(V) VB() VS() IN(WH) IN(VH) IN(H) VCC COM HVIC OT(WH) VS(W) OT(VH) VS(V) OT(H) VS() W (2) V (3) (4) Motor CDCS VDC CSP15F (13) V CC (12) COM VCC COM OT(WL) N W (5) Gating WL Gating VL Gating L +5V (11) IN (WL) (10) IN (VL) (9) IN (L) IN(WL) IN(VL) IN(L) LVIC OT(VL) N V (6) H Fault RPF (8) V FO VFO OT(L) N (7) CPF CSP15 Current Sensing Figure 2. Schematic of Reference Design for 3-Phase Inverter Part (Direct Coupling) 2014 Fairchild Semiconductor Corporation 3 RD-408 Rev. 1.1

4 3. Key Parameter Design 3.1. Selection of Bootstrap Capacitance (C ) The bootstrap capacitor value can be calculated by: C I Leak V t (1) Δt ΔV I Leak = maximum ON-pulse width of high-side MOSFET; = the allowable discharge voltage of the C (voltage ripple); = maximum discharge current of the C consisting of: Gate charge for turning the high-side MOSFET on Quiescent current to the high-side circuit in the IC Level-shift charge required by level-shifters in IC Leakage current in the bootstrap diode C capacitor leakage current (can be ignored for non-electrolytic capacitors) Bootstrap diode reverse recovery charge Practically, 2 ma of I Leak is recommended for FSB44104A (I P, operating V supply current at 20 khz, is max. 2 ma in the datasheet). Calculation examples of C : I Leak ΔV Δt (2) C = 10 ma = 2.0 V (recommended value) = 2 ms (depends on user system) I t 10mA 2ms Leak 6 _ min 0 V 2.0V More than 2~ 3times 20~ 30 μf standard nominal capacitance 22 ~ 35 μf Notes: 2. In case of trapezoidal control for BLDC motor or 2-phase modulation, long ON time periods of the high-side MOSFET may exist. Attention should be paid to the bootstrap supply voltage drop. 3. The above result is only a calculation example. It is recommended that actual PWM patterns and lifetime of components should be considered in the design Fairchild Semiconductor Corporation 4 RD-408 Rev. 1.1

5 3.2. Selection of Bootstrap Resistor (R ) A resistor must be added in series with the bootstrap diode to slow down the dv /dt and determine the time to charge the bootstrap capacitor. If the minimum ON pulse width of low-side MOSFET or the minimum OFF pulse width of high-side MOSFET is t O ; the bootstrap capacitor must be charged to increase the voltage by ΔV during this period. Therefore, the value of bootstrap resistance can be calculated by Equation (2): R ( V C CC V ) t o ΔV (2) V CC V t O C = Supply voltage; = Minimum bootstrap voltage; = Minimum ON pulse width; = Bootstrap capacitor value; and ΔV = Ripple voltage of V. Calculation Examples of R : V CC t O C ΔV R = 15 V, V = 13 V (minimum voltage) = 200 µs (if carrier frequency is 5 khz, 1-cycle is 200 µs) = 20 µf (obtained bootstrap capacitor value) = 1 V (recommended value) ( VCC V ) to V 200s 20 C ΔV 20F 1V If the rising dv /dt is slowed significantly, it could cause missing pulses during the startup phase due to insufficient V voltage Selection of Shunt Resistor (One Shunt) The value of shunt resistor is calculated by the following equations. Maximum short-circuit (SC) current trip level (depend on user selection): I SC(max) = 1.5 I C(max) SC trip reference voltage (depends on user selection): V SC = min V, typ V, max V (Tolerance 10%, depends on system) Shunt resistance: I SC(max) = V SC(max) / R SHNT(min) R SHNT(min) = V SC(max) / I SC(max) If the deviation of the shunt resistor is limited below ± 1%: R SHNT(typ) = R SHNT(min) / 0.99, R SHNT(max) = R SHNT(typ) Fairchild Semiconductor Corporation 5 RD-408 Rev. 1.1

6 Actual SC trip current level becomes: I SC(typ) = V SC(typ) / R SHNT(typ), I SC(min) = V SC(min) / R SHNT(max) Inverter output power: P OT = MI = Modulation Index; V O,LL = Inverter output line to line voltage; I RMS = Maximum load current of inverter; and PF = Power Factor Average DC current I DC_AVG = V DC_Link / (P out Eff) Eff = Inverter efficiency The power rating of shunt resistor is calculated by the following equation: P SHNT = (I 2 DC_AVG R SHNT Margin) / Derating Ratio R SHNT = Shunt resistor typical value at T C = 25 C Derating Ratio = Derating ratio of shunt resistor at T SHNT = 100 C (From datasheet of shunt resistor); and Margin = Safety margin (determined by user) Shunt Resistor Calculation Examples Calculation Conditions: DT: FSB44104A Tolerance of shunt resistor: ±1% SC Trip Reference Voltage(V SC ) : V SC(min) = V, V SC(typ) = 0.03 V, V SC(max) = V V SC = Reference voltage of external comparator (refer to the Fig. 3) Maximum Load Current of Inverter (I RMS ): 28.3 A rms Maximum Peak Load Current of Inverter (I C(max) ): 60 A Modulation Index(MI) : 0.9 DC Link Voltage(V DC_Link ): 20 V Power Factor(PF): 0.8 Inverter Efficiency(Eff): 0.95 Shunt Resistor Value at T C = 25 C (R SHNT ): 0.5 mω 2014 Fairchild Semiconductor Corporation 6 RD-408 Rev. 1.1

7 Derating Ration of Shunt Resistor at T SHNT = 100 C: 70% Safety Margin: 20% Calculation Results: I SC(max) : 1.5 I C(max) = 1.5 x 40 A = 60 A R SHNT(typ) : V SC(typ) / I SC(max) = 0.03 V / 60 A = 0.5 mω R SHNT(max) : R SHNT(typ) x 1.01 = 0.5 mω x 1.01 = mω R SHNT(min) : R SHNT(typ) x 0.99 = 0.5 mω x 0.99 = mω I SC(min) : V SC(min) / R SHNT(max) = V / mω = 58.8 A I SC(typ) : V SC(typ) / R SHNT(typ) = 0.03 V / 0.5 mω = 60 A V O,LL = P OT = = = W I DC_AVG = (P OT /Eff) / V DC_Link = 22.7 A P SHNT = (I 2 DC_AVG R SHNT Margin) / Derating Ratio = ( ) / 0.7 = 0.31 W (Therefore, the proper power rating of shunt resistor is over 1.0 W) 3.4. Design of Short-Circuit Current Protection (SCP) Circuit Figure 3 is typical application circuits for SCP function using MC, needs external amplifier circuit and comparator circuits. In this reference design, SC trip level (V SC ) is 0.3 V (I SC(max) =60 A) and V REF level is 2.5 V. MC Internal port 5V line R 21 10k 1% R % C R 19 1M 5V line Comparator R 18 20K 1% R k 1% 5V line R 16 10k 1% 5V line V REF R K 1% V SC C Amplifier R K 1% C R m 3W N, N V, N W SPM R K 1% Figure 3. Short-Circuit Protection (SCP) Circuit sing MC 2014 Fairchild Semiconductor Corporation 7 RD-408 Rev. 1.1

8 4. Print Circuit Board (PCB) Layout Guidance It is recommended to connect control GND and Power GND as short as possible + - Amplifier Comparator AND gate GND F. FSB44104A XXX EXX 33uF 35V 33uF 35V 20R BR3 D3 33uF 35V Connect CSC filter s capacitor to control GND(not to power GND) CSC wiring should be as short as possible N Place sunbber capacitor between P and N, and closely to terminals P +15V V W + 5V VFO VIN(WL) VIN(VL) VIN(L) VIN(WH) VIN(VH) 20R BR1 VIN(H) D1 20R BR2 D SPM 45 LV design for PCB layout V The VIN RC filter should be placed to SPM as close as possible Isolation distance between high voltage block and low voltage block should be kept Capacitor should be locate closely to terminals of SPM Wiring between N, NV, NW and shunt resistor should be as short as possible 2014 Fairchild Semiconductor Corporation 8 RD-408 Rev. 1.1

9 5. Related Resources FSB44104A Motion SPM 45 LV Series Product Folder FSB43004A Motion SPM 45 Series Product Folder. Reference Design Disclaimer Fairchild Semiconductor Corporation ( Fairchild ) provides these reference design services as a benefit to our customers. Fairchild has made a good faith attempt to build for the specifications provided or needed by the customer. Fairchild provides this product as is and without recourse and MAKES NO WARRANTY, EXPRESSED, IMPLIED OR OTHERWISE, INCLDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR A PARTICLAR PRPOSE. Customer agrees to do its own testing of any Fairchild reference designs in order to ensure design meets the customer needs. Neither Fairchild nor Customer shall be liable for incidental or consequential damages, including but not limited to, the cost of labor, requalifications, rework charges, delay, lost profits, or loss of goodwill arising out of the sale, installation or use of any Fairchild product. Subject to the limitations herein, Fairchild will defend any suit or proceeding brought against Customer if it is based on a claim that any product furnished hereunder constitutes an infringement of any intellectual property rights. Fairchild must be notified promptly in writing and given full and complete authority, information and assistance (at Fairchild s expense) for defense of the suit. Fairchild will pay damages and costs therein awarded against Customer but shall not be responsible for any compromise made without its consent. In no event shall Fairchild s liability for all damages and costs (including the costs of the defense by Fairchild) exceed the contractual value of the products or services that are the subject of the lawsuit. In providing such defense, or in the event that such product is held to constitute infringement and the use of the product is enjoined, Fairchild, in its discretion, shall procure the right to continue using such product, or modify it so that it becomes noninfringing, or remove it and grant Customer a credit for the depreciated value thereof. Fairchild s indemnity does not extend to claims of infringement arising from Fairchild s compliance with Customer s design, specifications and/or instructions, or the use of any product in combination with other products or in connection with a manufacturing or other process. The foregoing remedy is exclusive and constitutes Fairchild s sole obligation for any claim of intellectual property infringement and Fairchild makes no warranty that products sold hereunder will not infringe any intellectual property rights. All solutions, designs, schematics, drawings, boards or other information provided by Fairchild to Customer are confidential and provided for Customer s own use. Customer may not share any Fairchild materials with other semiconductor suppliers Fairchild Semiconductor Corporation 9 RD-408 Rev. 1.1