Design of 4-Bit Manchester Carry Look-Ahead Adder Using MT-CMOS Domino Logic Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, Banupriya M

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1 Design of 4-Bit Manchester Carry Look-Ahead Adder Using MT-CMOS Domino Logic Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, Banupriya M msenthilsivakumar@gmail.com, dhasjohn85@gmail.com, arputharajsamvel@gmail.com, mvbanupriya@gmail.com Abstract A design of high performance and low power 4-bit Manchester carry look-ahead adder is presented in this paper using multi-threshold domino logic technique. The introduced MT-MOS transistors reduce the power dissipation of adder circuit by limiting sub threshold leakage current. Feed Through Logic (FTL) dynamic logic is a technique which increase the operating speed of logic circuit. It evaluates the computational blocks partially before the input signals are formalized and then the final evaluation is performed as soon as the input signals arrive. The pre-evaluation logic reduces propagation delay into half. The combination of FTL dynamic logic and MT-CMOS domino logic techniques yield high fan-out, high switching frequencies since both lower delay and dynamic low power consumption in the arithmetic circuits. In carry look-ahead adder, a Manchester structure of carry generation is employed to minimize the area of arithmetic circuit by decreasing number of transistors. The simulation results have been verified that the proposed techniques are reduced the total power dissipation up to 40% and propagation delay up to 55% when compared to the standard dynamic domino CMOS technology. Index Terms CLA, CMOS, Domino logic, Dynamic logic, FTL, MT-CMOS. I. INTRODUCTION The invention of Monolithic integrated circuits and MOS transistors are brought a giant revolutionary changes in microelectronics. The increased performance, and reduced power consumption, cost and size of the device are importantly notable in Monolithic integrated circuits. The increasing demands of high performance processors are also developing complicated rise in technological emergent of integrated circuits. This emerging growth is forcing the researchers to develop the new dynamic circuits to improve the performance, area efficiency, functionality and cost reduction of different logical and arithmetic circuits. Normally, in the integrated circuits arithmetic operations are extensively used for basic and enhanced applications. Basically in arithmetic circuits carry look-ahead addition is used for fast operations since it calculates the carry bit before the sum which reduce the propagation delay of the circuit maximally. The parallel calculation of sum and advanced carry bits increase the operating speed of the circuit but that increase the transistor count in the implementation. When the controlling action taken against the device count that reduce the performance of the circuit. Many techniques were developed to improve the performance by limiting the device count of arithmetic circuit designs. So far the use of carry look-ahead principle of high-speed arithmetic unit is precisely one of the challenges in VLSI processor design structured today for multilevel CLA circuits without limiting the functional flexibility. Power reduction is also another important factor in integrated circuit. It is extremely important for battery powered devices like calculators, notebooks, portable devices, cellular telephones, pagers, wireless applications and palmtops etc. In arithmetic circuits to improve the performance and to reduce the power consumption dynamic and domino CMOS logic techniques are popularly used in the design. Dynamic logic technique usually reduces the device count in the circuit design but when one logic circuit is directly cascaded with another circuit the first circuit discharge the output of second circuit permanently which lead the circuit to produce wrong output. In order to cascade the logic circuits without error output, domino logic technique is popularly used in the integrated circuits. Domino logic technique uses a static inverter between two logic circuit in order to avoid the charge/discharge error that appear between the dynamic logic circuit. The use of domino logic in high performance processor offers smaller area and higher performance than conventional CMOS logic design. However the reduction of average power consumption and propagation delay in domino logic is a significant factors in arithmetic circuits. In CMOS circuits the leakage appear due to the parasitic capacitances present in the junction of transistors cause to increase the power dissipation of the device. The flow of leakage current in the integrated circuit affect the output by triggering the transistor when it must be in off. So it should be limited or eliminated in the circuit to get the proper output and to reduce the power dissipation. A multi threshold transistor can be used to control the leakage current since it has the high triggering voltage to change the state of output. A low-power dual threshold voltage-voltage scaling technique for domino logic circuit [1] reduces the total power consumption of an arithmetic circuit. Also the multi threshold voltage transistors prevent the circuit from unwanted switching transients (glitches). In [2], a dual threshold voltage technique for glitch minimization is presented and verified with CMOS logic circuits. The 62

2 high threshold voltage transistors are not sensitive to the leakage current. Also the total power consumption of the circuit can be reduced through high threshold voltage transistors considerably. It is verified in [3] with the name of NBTI-aware dual threshold voltage assignment for leakage power reduction. The dual VT techniques are proposed in [5] and the outputs are verified as low power circuits by comparing with conventional CMOS digital circuits. Feed through logic is another important logic against technology for high performance in particular applications. The evaluation technique employed in the FTL reduce the propagation delay of the circuit considerably to increase the performance. In paper [4], an FTL (Feed through logic) design technique is proposed for high performance dynamic CMOS logic with high noise immunity and low power. An FTL improves the performance of arithmetic circuits with a very long logic depth. Chen and Li [6] have developed an improved 32-bit carry look-ahead adder with Conditional Carry-Selection for high speed and low power arithmetic circuit. It is implemented on silicon to verify the power reduction as well as the preservation of high speed. In [7] Levi, Bass have developed a high speed dual mode logic carry look ahead adder to limit the power dissipation of logic circuits. The output of Multi-threshold CMOS design for low power digital circuit is proposed and verified in [8], [12] and [14]. Sleep switch dual threshold voltage domino logic with reduced sub threshold and gate oxide leakage current is proposed and verified in [9] by Wang, Huang, and Cheng. The reduction of sub threshold leakage and gate oxide leakage current are achieved in [10] and [13] for domino logic circuit. Domino logic technique improves the performance and reduces the device count and silicon area of arithmetic circuit when compared to the standard fully complementary static CMOS logic. However, the major drawback with the domino dynamic logic circuit is that the circuit consumes extra power due to the switching activity and the clock load of the circuit. To eliminate the excessive power dissipation of the dynamic logic, the current design methodologies trade the power for performance in critical delay sections of arithmetic circuit. This technique can be achieved through a combination of dynamic and static circuit styles, and by the use of dual supply voltages and dual-vt transistors. So far domino and dynamic logics are endured by charge sharing and race problems. To solve these demerits, we are proposing the new MT-CMOS dynamic logic circuit using multi threshold MOS transistor for reducing the power dissipation. Also to increase the performance of the dynamic logic circuit, FTL logic technique is employed in the arithmetic circuits. The proposed circuit is giving solution for problems discussed and also minimizing power wastages. In this paper, we are also proposing a low power high performance 4-bit Manchester carry look-ahead logic structure using a new MT-CMOS domino logic blocks to reduce device count. A. MT-CMOS Domino Logic II. PRINCIPLE OF OPERATION Domino logic is employed in the arithmetic circuit reduce the area of the device. The parasitic capacitances are less in the domino logic circuit that increase the operating speed of device. Also it produce the output free of glitches i.e. the transistors in the domino logic make only one transition per clock cycle. Multi threshold technique is applied on the gate terminal of the MOS transistor to limit the leakage appear on the gate terminal. Normally in high threshold transistors the size of gate terminal is very large than low threshold transistors. The large gate of transistor develop the large parasitic capacitances which tends to suppress the switching of transistor from one state to another and hence the speed is increased. It clearly shows that the employment of large threshold voltage transistors increase the speed of the circuit and reduce the leakage current of the transistor. Hence the domino logic and MT-CMOS logic techniques can be used in the arithmetic circuit to increase the speed and to reduce the power dissipation. With the intention of reducing power dissipation and propagation delay in the arithmetic circuit the new MT-CMOS domino logic circuit is introduced in this paper in combination of domino logic technique and multi threshold technique. The proposed MT-CMOS Domino Logic Circuit is shown in Fig 1. In the circuit, multi threshold MOS transistors are printed in dark line on gate to differentiate from low threshold voltage transistors. The employment of MT-CMOS transistors in domino logic circuits reduce the power dissipation by eliminating sub threshold leakage current and gate oxide leakage current with high threshold voltage. Normally multi threshold transistors i.e. MT-PMOS and MT-NMOS transistors are larger than standard transistors. This condition greatly depends on the parasitic capacitors which present in the transistor. When the PMOS and NMOS transistor width is reduced, the parasitic capacitances become larger and that tends to suppress the switching time of logic low and high to improve the speed. In the standby (Sleep) mode, i.e., when logic high clock signal is applied to circuit, the MT-transistors switch to off, that leads the circuit for reduction of static power dissipation and elimination of sub threshold current. It is reducing the total power dissipation of MT-CMOS circuit. In evaluation mode, dynamic logic circuit improves the speed of switching operation through feed through logic. The domino logic circuit shown in Fig 1 consists of multi threshold PMOS transistor P11 and NMOS transistor N11, low threshold NMOS logic block, low threshold discharge transistor N12 and an inverter in the output. The low threshold NMOS logic block is constructed to achieve the arithmetic logic that has to be implemented. It can be evaluated on arrival of input signals on the gate terminal of the transistors with the control of multi threshold transistors P11 and N11. The low VT transistor N12 is used to keep the logic block output as low when the circuit functions in pre-charging mode. The introduced domino logic circuit operates in 63

3 two mode such as pre-charging and evaluation. In pre-charging mod with the help of N12 the output inverter is maintained in logic high. In evaluation mode the circuit evaluates the NMOS logic block as soon as the inputs arrive to the gate of low VT transistors. The pre-charging and evaluation phase of the circuit is functioning dependent on the level of clock as logic low and high. Usually in MOS transistor logic, PMOS transistor gets ON for logic low input while the NMOS transistor gets ON for logic high input. In the circuit inverted clock pulse is applied for NMOS transistor N11. When the CLK is high, the transistors P11 and N11 gets OFF. This is known as pre-charging phase. The transistor N12 gets ON with logic high clock input. In this phase, the leakage current appear at node A due to the sub-threshold leakage of low VT logic block is grounded through N12 and that maintains node A in logic low. The low voltage on node A is applied to the inverter in which transistor P12 saturates and N12 goes to cut-off. The saturation of P12 provides the output as logic high which is named as pre-charging in domino logic circuit. When the CLK is low, the transistors P11 and N11 gets ON. This is known as evaluation phase. During this evaluation phase, the low VT NMOS logic block is evaluated efficiently to switch the node voltage VA almost equal to VCC or ground. The low VT NMOS transistor N12 is OFF with low clock input. Therefore the voltage at node A is developed by the evaluation of logic block as high or low. The low VT logic circuit is evaluated faster since it has reduced logic delay by 55% compared to high-vt logic circuit. Hence this evaluation is performed faster with less propagation delay. The proposed logic circuit provides the flexibility to design the logic circuit, so it can be used to design multistage domino logic with iterative circuits. The two stage MT-CMOS dynamic logic circuit is shown in Fig 2 which is expressing the cascaded connection of proposed domino logic technique to construct pipeline structure. In this two stage implementation, stage 1 and 2 are operating alternatively in pre-charging phase and evaluation phase. The pre-charging of first state produce logic high input to the next state for evaluating the logic blocks effectively. Similarly in the cascade connection the pre-charging of previous state helps to evaluate the next stage uninterruptedly. The logic evaluation of this two stage cascade connection functions as follows dependent on the level of clock input as low or high. If the applied CLK is high, first stage operates in pre-charging phase and second stage operates in evaluation phase. MT-NMOS N22 is used to hold the output of first stage in logic high during the pre-charging phase. This logic high output is applied to evaluate low VT NMOS section of second stage. The second stage evaluates the low VT NMOS logic block by activating MT-transistors P23 and N24. If the applied CLK is low, first stage operates in evaluation phase and second stage operates in pre-charging phase. The first stage evaluates the low VT NMOS logic block by the activation of the MT-Transistors P21 and N21. At the same time the second stage operates in pre-charging phase. The signal applied into MT-NMOS N25 is used to hold the output of second stage in logic high during the pre-charging phase which evaluates the next stage. This alternate switching of pre-charging and evaluation of adjacent stages is also assisting to reduce the power consumption of circuit into one-half. Also this FTL based dynamic domino logic operates faster to develop the output when compare to typical CMOS dynamic logic circuit. Fig. 1. Proposed MT-CMOS domino logic 64

4 Fig. 2. Cascaded two stage MT-CMOS dynamic logic Similar to the two state cascaded connection the domino logic can be implemented for any numbers of stages. The domino logic technique in the cascaded circuit increase the throughput of circuit which helps to increase the fan-out of arithmetic circuit. The combination of domino logic and multi threshold logic in the arithmetic circuit increase the performance of the circuit maximally when compared with conventional circuit. Also it reduce the power dissipation of the arithmetic circuit by limiting the sub threshold leakage current. B. Manchester Carry Look-Ahead Adder Normally in adders the sum and carry of the circuit is calculated separately to find the addition output. In multi bit addition normally the sum output is calculated dependent on the previous carry output which may increase the propagation delay of the adder circuit. This delay effect can be eliminated by the use of Carry look-ahead adder which works with a principle of carry generation and propagation. It generates the carry of multi bit adder parallel to the evaluation of sum block. And then the generated carry outputs are propagated to the sum block as per the requirements. The parallel evaluation of carry block allows the preprocessing addition step of two numbers to find the carry. That helps to reduce the propagation delay of adder. In general the efficiency of domino carry chain is enriched by pre-charging phase of circuit at appropriate points. The adder circuit works in pre-charging phase when the clock input is high. When MT-transistors are turned off, the output goes to logic high through inverter. When the clock input is low, the adder circuit operates in evaluation phase. When MT-transistors are turned on, the logic blocks are evaluated by the inputs applied to low VT logic block. However, the carry look-ahead adder uses many transistors to construct a logic block. If numbers of bits are increased in the adder, the transistors count also increases maximally in an adder circuit. Here, we are introducing a new Manchester carry look-ahead structure to reduce the number of elements employed in the construction of adder circuit. Manchester carry chain is a carry look-ahead generator that uses shared logic technique to reduce the transistor count. The circuit of 4-bit carry look-ahead adder is shown in Fig 3 in which Fig 3(a) and 3(b) are representing the circuit of carry propagate and generate signal provider, Fig 3(C) is representing the circuit of Sum output provider, Fig 3(d) is representing the circuit of conventional structure carry output provider and Fig 3(e) is representing the circuit of Manchester structure carry output provider of the adder. The logic blocks are implemented by new FTL MT-MOS transistors to reduce the propagation delay and power dissipation. The carry propagate circuit is shown in Fig 3(a) which generates the output from the parallel connected NMOS transistors. The transistors P11 and N11 are the control transistors which are functioning by the control of clock pulse. When clock pulse is high the circuit functions in pre-charging phase. The transistor N12 discharges the output Pi to logic low at pre-charging. When clock pulse is low the circuit functions in evaluation phase. The parallel connected NMOS transistor logic block provides the NOR operation as an output at Pi. The logic output expression of carry propagation circuit is given by, P i A B (1) i i Fig.3 (a). Propagate signal 65

5 The carry generate circuit is shown in Fig 3(b) which generates the output from the series connected NMOS transistors. The transistors P11 and N11 are the control transistors which are functioning by the control of clock pulse. When clock pulse is high the circuit functions in pre-charging phase. The transistor N12 discharges the output Gi to logic low at pre-charging. When clock pulse is low the circuit functions in evaluation phase. The series connected NMOS transistor logic block provides the NAND operation as an output at Gi. The logic output expression of carry generation circuit is given by, G A.B (2) i i i Fig.3 (C). Sum output Fig.3 (b). Generate signal Fig 3(c) is a circuit of sum calculator which is also constructed by proposed MT-MOS transistor technique. It develops the sum output as soon as the carry and propagate signals arrive from the carry and propagate signal providers. In the circuit transistors P11 and N11 are the control transistors which are functioning by the control of clock pulse. The NMOS transistor N12 discharges the output when it is saturated. The logic sum output is performed with pre-charging and evaluation phase with the control of clock pulse as logic high and low respectively. When clock pulse is high the circuit functions in pre-charging phase. The transistor N12 discharges the output Si to logic low at pre-charging. When clock pulse is low the circuit functions in evaluation phase. The logic block of sum output generator is evaluated from the input propagate signal Pi and previous carry signal Ci-1. The logic output expression of sum output circuit is given by, S i P. C i i 1 Pi. C i 1 P C (3) i i 1 The sum output of the adder circuit can be obtained by connecting an inverter in the output. The evaluation of sum is almost similar in both conventional and proposed adder logic circuit. The circuit diagram of conventional carry generator is shown in Fig 3(d). It consists of 10 PMOS transistors and 10 NMOS transistors. The low VT transistors employed in the circuit may affect the output due to sub threshold leakage and that cause to increase the power dissipation of the circuit. Also usually in CMOS logic technique the size of PMOS transistor is fixed as double when compared to NMOS transistors. Since the mobility of electrons which drive the NMOS transistor are double than holes which drive the PMOS transistors. The employment of large PMOS transistor increases the area of arithmetic circuit drastically. The demerits of this conventional carry generator can be overcome by the use of proposed Manchester carry generator circuit. The circuit diagram of Manchester carry chain is shown in Fig 3(e). It generates various carry signals for the adder. The circuit consists of only 6 PMOS transistors and 11 NMOS transistors. The use of reduced number of transistors in the Manchester carry chain reduce the area of the circuit maximally compared to conventional structure. In the proposed structure MT-PMOS and MT-NMOS transistors are limiting the sub threshold leakage in the circuit which helps to reduce the power dissipation of the device. Normally the size of multi threshold transistors are larger than the low threshold transistors. It may increase the size of arithmetic circuit literally but in the Manchester structure the reduced transistor count compensates this problem. In the introduced new Manchester carry look-ahead adder circuit the carry generator reduce the number of elements used to construct a logic circuit and the MT transistors reduce the sub threshold leakage in the circuit. The Manchester carry chain is a carry look-ahead generator that uses shared logic technique to reduce the transistor count. The logic output of Manchester structure is evaluated dependent on the level of clock pulse as low or high. The carry propagate signals Pi and carry generation signals Gi are applied to the Manchester carry structure to evaluate the logic output. The logic carry output is 66

6 performed with pre-charging and evaluation phase with the control of clock pulse as logic high and low respectively. When clock pulse is high the circuit functions in pre-charging phase. When clock pulse is low the circuit functions in evaluation phase. in this phase the logic block of Manchester carry chain is evaluated from the applied input propagate signal Pi and generate signal Gi. The carry signal of adder is obtained through an inverter. However no longer we need the intermediate carry signals as the carry bits distributed in the circuit arrangement. A fourth bit of carry propagation of Manchester structure is selected to reduce numbers of series propagate transistors which supports to reduce the consequence of body effect. The logic expressions of proposed carry look-ahead adder defines the logic output of adder circuit. The logic structure of a proposed Manchester carry look-ahead adder is evaluated to determine the logic expressions. The output expression of proposed 4-bit Manchester carry generation circuit is obtained as follows, C1 G1 P1.C0 C 2 G2.C1 G ) 2.(G1 P1.C0 C 3 G3 P3.C2 C G3 P 3. ( G2.C1 ) G3 P 3. ( G2.(G1 P1.C0)) 4 G4 P4.C3 G4 P4.( G3 P3.C2 ) G4 P4.( G3 P 3. ( G2.C1 )) G4 P4.( G3 P 3. ( G2.(G1 P1.C0))) From the above expressions the general logic expression of Manchester carry generator can be written as C G P.C (4) i i i i 1 The proposed 4-bit Manchester type carry look-ahead adder can be connected in cascade to perform the addition with 8-bit, 16-bit addition and so on. The introduced domino logic technique increases the throughput of adder circuit when it connected in cascaded. The introduced MT-CMOS techniques reduces the power dissipation of the circuit. The FTL logic increases the operation speed of the circuit without increasing the area of the arithmetic circuit. The combination of these three logics in the arithmetic circuit increase the performance operating speed even for the addition of two date with large numbers for bits. Fig.3 (d). Carry output of conventional Structure 67

7 Fig.3 (e). Carry output of Manchester Structure Fig. 3. Circuit of Carry Look-ahead adder III. SIMULATION RESULTS The proposed high performance and low power MT-CMOS based 4-bit Manchester carry look-ahead adder technique is increasing the speed and reducing the average power consumption of the circuit. To verify this assertion, the simulations were conducted for the proposed MT-CMOS dynamic logic and typical CMOS dynamic logic circuits. A TSMC 0.18µm CMOS technology was employed in tanner EDA tool to determine the power dissipation and propagation delay of the circuits. The circuits has been drawn in S-edit and that exported on T-edit. The circuit configurations then integrated with the technology file and required input and output specifications. Then the simulation were performed to get the result as shown in Fig 4(a). The output waveform has been obtained for the applied input. By the comparison of input and output waveform the rise time and fall time delay of the circuit has been obtained. From the rise and fall time delay of the output the average propagation delay of the circuit is obtained using the formula given below, Average propagation delay (tpd), ( t t ) pdr pdf t pd 2 (5) Where, tpdr rising propagation delay, From input to rising output crossing VDD/2. tpdf falling propagation delay, From input to falling output crossing VDD/2. The cascaded adder circuit has drawn for 30 stages and that simulated similar to the dynamic logic explained above. The input-output characteristic waveform of the circuit is obtained as shown in Fig 4(b). The cascaded domino logic circuit output is obtained with high throughput, free of glitches and reduced propagation delay. The propagation delay between the first stage and the last stage is also less in parameter. It clearly shown that the cascaded arithmetic logic circuit is operating with high performance. The proposed domino logic circuit is also verified for power reduction that ensures the reduced power dissipation compared to the typical domino logic circuit. Also the proposed Manchester 4-bit carry look-ahead adder method is simulated and verified with tanner tool which results the reduced power dissipation and propagation time delay. The obtained results are shown in Fig 4. (a) Output and Input waveforms 68

8 (b) Output waveform for 30 cascaded stages resulted that the circuit consumes less power and operates with high performance when compared conventional carry look-ahead adder. The power analysis of proposed 4-bit carry look-ahead adder is shown in Fig 4(c). The power dissipation of the circuit is obtained in mw for various input voltages. The power dissipation chart shows that the proposed structure is consuming 1/3 of power when compared with conventional technique. The delay analysis of proposed 4-bit carry look-ahead adder is shown in Fig 4(d). The propagation delay of the circuit is obtained in nsec for various input voltages. The propagation delay chart shows that the proposed structure is operating around 4 times faster than the conventional technique. The power and delay values are also verified using following formulas. (c) Power Analysis Chart Fig. 5(a). Layout of Propagate, Generate and Sum output (d) Delay Analysis Chart Fig. 4. Simulation results The conventional and proposed Manchester carry look-ahead adder structures are simulated separately in the tanner EDA tool. The characteristic waveform of proposed Manchester carry look-ahead adder circuit Fig. 5(b). Layout of 4-bit Manchester Carry Structure Transient power consumption can be calculated using the equation: 69

9 Power(P T ) C V2 F I N (4) pd CC SW Where, PT Transient power consumption; VCC Supply voltage; FI Input signal frequency; NSW Number of bits switching; and Cpd Dynamic power-dissipation capacitance. Figure of merit =delay power area. The input/output waveforms and power and area comparison chart are shown in Fig 4. The layout of proposed 4-bit Manchester carry look-ahead adder is shown in Fig 5. Fig 5(a) shows the layout of carry propagate, generate and sum circuits which are shown in Fig 3(a), (b), and (c), respectively. Fig 5(b) shows the layout of Manchester carry circuit which is shown in Fig 3(e). the layout of the proposed circuits have been drawn in L-Edit and that extracted as net list to T-Edit to verify the results obtained through the circuit simulation. The obtained net lists were simulated to ensure the power and area reduction of proposed Manchester carry look-ahead adder. The simulation results of layout are certified the power and area reduction similar to circuit simulation. IV. CONCLUSION In this paper, we have presented an efficient method with minimized power and increased speed of dynamic logic circuit for arithmetic circuits using FTL and MT-CMOS logic techniques. Charge sharing problems associated with dynamic and domino families are also removed in the proposed structures. By eliminating these power wastages, the total power consumption of adder circuits is reduced with the help of MT-CMOS domino logic technique. The propagation delay of adder is also decreased by pre-evaluation procedure of FTL which helps to increase the operating speed of adder. Experiments have ensured the high speed operation and low power dissipation of Manchester carry look-ahead adder by the proposed model match with SPICE simulation results. For the experimental verification, the proposed Manchester 4-bit carry look-ahead adder method is simulated in tanner EDA tool with TSMC 0.18µm technology file. Hence, the simulated result shows that the reduction of power dissipation up to 40% and propagation time delay up to 55%. The proposed 4-bit Manchester carry look-ahead adder can be cascaded to perform the logic addition with 8-bits, 12-bits, 16-bits and so on. Since the use of feed through domino logic technique, the circuit remain operates with high performance for large number of bits. ACKNOWLEDGMENT The successful completion of any task would be incomplete without the mention of the people who made it possible through their constant guidance and encouragement crowns all the efforts with success. First up all, we wish to express our special thanks to grateful God for giving us peaceful life and given a chance to perform this research. Then we wish to express gratitude to our parents (Mr.K.Mookkaiah and Mrs.M.Valliammal) and sister (Ms.M.Sivagami) for built us to this position with their consistent encouragement, moral support, blessings and hard work. We would like to say thanks to our fellow students who helped us in every possible way to make this project a success. We express our heartfelt thanks to St. Joseph University, St. Eugene University and VIT University and the Management of the Institution for a chance given us to build and complete this research project on time. REFERENCES [1] Arun P, Ramasamy S, A low-power dual threshold voltage-voltage scaling technique for domino logic circuits, Computing Communication & Networking Technologies (ICCCNT), IEEE 2012, pp.1-6. [2] Slimani, Mariem, Matherat, Philippe, Mathieu, Yves, A dual threshold voltage technique for glitch minimization, Electronics, Circuits and Systems (ICECS), th IEEE International Conference, pp [3] Tu Wen-Pin, Wu Shih-Wei, Huang Shih-Hsu H, Chi, Chi Mely Chen, NBTI-aware dual threshold voltage assignment for leakage power reduction, Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp [4] Pattanaik Manisha, Parashar Shashank, Kumar Chaudhry Indra, Chouhan Akanksha, Mahor Vikas, A novel low power noise tolerant high performance dynamic feed through logic design technique, Electronic System Design (ISED), 2011 IEEE International Symposium, pp [5] Nausieda Ivan, Ryu Kyungbum, Akinwande, Bulovic Vladimir, Sodini Charles G, Mixed-signal organic integrated circuits in a fully photolithographic dual threshold voltage technology, Electron Devices, IEEE Transactions on Volume: 58, Issue: 3, 2011, pp [6] Ping-hua Chen, Juan Zhao, Guo-bo Xie, Yi-Jun Li, An improved 32-bit carry-look ahead adder with Conditional Carry-Selection, 4th International Conference on Computer Science & Education-ICCSE '09, IEEE 2009, pp [7] Levi, Bass O, Belenky, High speed dual mode logic carry look ahead adder, International symposium on Circuits and Systems (ISCAS), 2012 IEEE, pp [8] Hemantha S, Dhawan Amit, Kar Haranath, Multi-threshold CMOS design for low power digital circuits TENCON 2008 IEEE region 10 conference, pp.1-5. [9] Chua-Chin Wang, Chi-Chun Huang and Tsai-Wen Cheng, A low power high-speed 8-bit pipelining CLA design using dual-threshold voltage domino logic, IEEE transaction on VLSI systems, vol.16, may 2008, pp [10] Zhiyu Liu, Volkan Kursun, Sleep switch dual threshold voltage domino logic with reduced sub threshold and gate oxide leakage current Microelectronics Journal 01/2006, vol. 37, pp [11] N. Weste, K. Eshraghian, Principles of CMOS VLSI Design, A systems perspective, Addison Wesley. [12] Senthil Sivakumar M, Arockia Jayadhas S, Arputharaj T, and Ramkumar E, Design of MT-CMOS Domino Logic for Ultra Low Power High Performance Ripple Carry Adder, IJETED, Jan 2013, issue 3, vol.1, pp [13] Senthil Sivakumar M, Banupriya M, Low power high performance design consideration of CMOS domino logic for fast adders, Journal of Scientific Theory and Methods, 2012, vol. 12, pp [14] Senthil Sivakumar M, Banupriya M, Design Consideration of Dual Threshold Logic for High 70

10 Performance and Ultralow Power Carry Look-Ahead Adder, IJSER, June 2012, vol. 3, issue 6. Senthil Sivakumar M 1 is working as a faculty in St. Joseph University in Tanzania, Tanzania, East Africa. He has received Bachelor of Engineering in Electronics and Communication engineering from Anna University, Chennai, India in 2005 and Master of Technology in VLSI design from VIT University, Vellore, India. He has been published many research papers in international journals. Also he has participated as an author in international conferences and published the research papers through that. He was awarded for best master level studentship research project by Intel India Ltd and Cadence India Ltd. He is also published the text books for the subjects Linear integrated circuit and Fundamentals of Digital Design. He is also a reviewer in International Journal of Electronics. He has a research interest of Low power VLSI Design, Analog and Digital CMOS VLSI Design. Arockia Jayadhas S 2 is working as a faculty in St. Joseph University in Tanzania, Tanzania, East Africa. He has received Bachelor of Engineering in Electronics and Communication engineering from Anna University, Chennai, India and Master of Engineering from Sathyabama University, Chennai, India. He has been published many research papers in international journals. Also he has participated as an author in international conferences and published the research papers through that. He is also participated as a co-author in a text book Fundamentals of Digital Design. His research interest include ASIC design and Embedded system. Arputharaj T 3 is working as a faculty in St. Joseph University in Tanzania, Tanzania, East Africa. He has received Bachelor of Engineering in Electronics and Communication engineering from Anna University, Chennai, India and Master of Engineering from Sathyabama University, Chennai, India. He has been published many research papers in international journals. Also he has participated as an author in international conferences and published the research papers through that. His research interest include wireless communication and Antenna design. Banupriya M 4 is working as a faculty in St. Joseph University in Tanzania, Tanzania, East Africa. She has received Bachelor of Science in Computer Science Engineering from Manonmaniam Sundaranar University, Tirunelveli, India in 2008 and Master of Computer Application from Anna University, Tirunelveli, India in She has been published many research papers in international journals. Also she has participated as an author in international conferences and published the research papers through that. She is also participated as a co-author in a text book Fundamentals of Digital Design. She has a research interest of Web Designing, and architecture design. 71