Trigger Board for the Auger Surface Detector With 100 MHz Sampling and Discrete Cosine Transform Zbigniew Szadkowski, Member, IEEE

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1 1692 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 Trigger Board for the Auger Surface Detector With 100 MHz Sampling and Discrete Cosine Transform Zbigniew Szadkowski, Member, IEEE Abstract The surface detector array of the Pierre Auger Observatory contains 1600 water Cherenkov detectors spread over an area of 3000 km 2. The Cherenkov light is detected by three 9-inch photomultiplier tubes from which the signals of the anode and last dynode are digitized by 10 bit ADCs. The currently used Front-End Boards equipped with the ACEX and Cyclone FPGA are sampled with 40 MHz. New requirements from the Auger North (100 MHz) and AMIGA (80 MHz) specification as well as the proposal of new spectral triggers based on the 16-point Discrete Cosine Transform (DCT) impose a new Front End Boards with more powerful FPGA chip with a sufficient amount of DSP blocks. The DCT trigger allows recognition of ADC traces with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated by hadrons and starting their development early in the atmosphere. Ten prototype boards equipped with Altera Cyclone III FPGA have been fabricated and successively tested in the lab and in real pampas conditions in six test surface detectors within April 19 July 26, Boards contain only a single FPGA chip, which implements also the slow channel, in previous three generations supported by the external Dual-Port RAM. Tests confirmed full stability and high reliability of the digital part. Both lab and field tests confirm a high efficiency of the recognition of expected patterns of ADC traces. Index Terms DCT, FPGA, Pierre Auger Observatory, trigger. I. INTRODUCTION T HE aim of the Pierre Auger Observatory is the measurement of cosmic rays at the highest energies with unprecedented statistics and resolution. The first Southern part of the Observatory is located in Argentina. It contains 1600 water Cherenkov detector stations distributed over an area of 3000 for measuring the charged particles associated with extensive air showers (EAS) and 24 telescopes with degrees field of view and 12 mirror area each to observe the fluorescence light produced by the charged particles in the EAS during operation in clear moonless nights. The simultaneous observation of EAS by the ground array and the fluorescence light called as hybrid events improves the resolution of the reconstruction considerably and, due to the calorimetric nature of the emitted fluorescence light, provides energy measurements virtually independent from hadronic interaction models [1]. Manuscript received June 09, 2010; revised October 07, 2010; accepted February 07, Date of publication March 28, 2011; date of current version August 17, This work was supported in part by the Polish Committee of Science under KBN Grant N N The author is with the University of Łódź, Department of Physics and Applied Informatics, Łódź, Poland ( zszadkow@kfd2.phys.uni.lodz.pl). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TNS Three 9-inch photo-multiplier tubes (PMTs) detect the Cherenkov light from the liters of purified water contained in each tank. The signals from the anodes (low-gain channel) and dynodes (high-gain channel) are transported on equal-length shielded cables to the Front End Board (FEB), attached as a daughter board to a Unified Board (UB). The UB contains a microcontroller that manages all processes related to the data acquisition in the detector station. The splitting of the signals allows an extension of the dynamic range of the measured energy to 15 bits with 5 bits overlapping. The system digitizes the 6 analog signals of each detector station in the multistage differential pipeline architecture ADC. Signal filtering is performed by anti-aliasing 5-pole Bessel filters. The outputs of the six 10-bit ADCs are processed by an Altera FPGA working as trigger/memory circuitry (TMC). The TMC evaluates the ADC outputs for interesting trigger patterns, stores data in a buffer memory, and sends an interrupt to the UB if a trigger occurs. II. FEB IMPROVEMENTS All 3 generations of the FEB equipped with FPGAs Altera families: APEX [2], ACEX [3] and Cyclone [4] have been working with 40 MHz sampling. The specification for the 2nd part of the Observatory planned in Colorado with 4000 surface detectors spread over foresees a higher sampling frequency 100 MHz. Faster sampling significantly improves the time resolution, crucial for measurements of rising time of signals coming from PMT, especially for horizontal and very inclined old showers with flat, narrow muon front, which gives sharp rising edges in ADC traces [5]. New cost-effective Altera Cyclone III family FPGAs are rich in resources, powerful and fast enough to implement fully the first level trigger (both fast and slow channels) in a single chip. In contrast to FPGA chips used in previous FEB generations, Cyclone III contains also fast DSP blocks. The selected chip EP3C40F324I7 for the new 4th generation FEB allows an implementation of the standard Auger code and additionally 3 engines of the new spectral trigger based on the Discrete Cosine Transform [6]. The DCT trigger was especially designed for a detection of horizontal and very inclined showers, for which the standard triggers are either much less effective or even completely blind. The EP3C40F324I7 allows also a resignation from the external Dual-Port RAM supporting the slow channel in all previous FEB generations. Although the sampling rate has been increased to 100 MHz, the communication with the UB still remains at 40 MHz. This clock is the only one available in the UB. The 100 MHz clock /$ IEEE

2 SZADKOWSKI: TRIGGER BOARD FOR THE AUGER SURFACE DETECTOR WITH 100 MHZ SAMPLING AND DCT 1693 is generated in the FPGA PLL circuit and split to the ADC by the clock distributor CY2308 (see Fig. 10). The ADC traces generated by the EAS are recorded in a shower memory working like a digital scope, in which the signals before and after a trigger point are latched. This memory is double buffered to minimize system dead time and consists from a 256 word long rotating pre-trigger buffer and a 512 word long post-trigger buffer filled when the trigger appears. The FPGA continuously monitors the data being sampled into the circulating shower memory buffer, looking for potentially interesting patterns. In all previous FEB generations this memory has been implemented as dual-port, but single-clock RAM. All pipeline routines were clocked by a single 40 MHz clock. The new FEB has to be compatible with the standard Auger UB, meaning, it should communicate with the UB at 40 MHz. Thus, the shower memory is recording 100 MHz clock data in the left port of the RAM, while the UB reads these data via the right port with only 40 MHz. The memory for the slow channel (replacement of the external Dual-Port RAM) has been implemented as FIFO with 16 k 32-bit structure. However, this size corresponds to only a single bank of the IDT70V3569, but twice more frequent DMA transfer for the slow channel data is practically not perceptible. III. LABORATORY TESTS A. Digital Data Flow The first test is a full verification of digital data flow from the digital inputs (digital data generated in the internal FPGA pattern generator were used instead of the ADC output) through the trigger system, internal memory buffer and the DMA transfer from the FPGA to the UB for both the fast and the slow channel through the trigger system, the logic circuit inserting time stamps, the external memory and finally also the DMA transfer from the Dual-Port RAM to the UB [8]. This test verifies whether any line is shortened or broken as well as any bit is corrupted. Test data were generated in the internal pattern generator and compared with data received in the UB. No channel reported any bit errors. B. Integral Linearity and Differential Non-Linearity The integral linearity of the ADC is crucial to correctly transform an analog signal shape to a digital representation. Differential non-linearity is dangerous especially for small signals, because it can disfigure their shape and significantly affect the Time-over-Threshold (ToT) trigger rate. The integral linearity and the differential non-linearity were tested by ramping up the input signals using a saw-tooth waveform and analyzing the digitized signals as a function of time (sample number). The rising edge of the analog signal was ( ), ( ) and ( ) to overlap the 768 word length of the fast buffer which registers the shower profile for 40, 80, and 100 MHz, respectively. For the integral linearity the correlation coefficients ( ) were calculated for all 768 words. Deviation from the perfect linearity ( ) were typically below, and, for 40, 80, 100 MHz, respectively. The integral non-linearity in the prototype Cyclone III boards is a little bit higher than for all FEB of the 3rd generation. Typical histograms of differences of ADC-counts in consecutive time bins for Cyclone boards showed strong peaks for the value (according to adjusted ramp signal) and negligible distribution. For Cyclone III boards however, histograms are wider (slightly worse transformation of ramping analog signals), nevertheless the differential non-linearity did not introduce significant signal distortions. C. Cut-Off Frequency According to the Nyquist theorem the cut-off frequency should be a half of the sampling frequency. The FEB have been designed for 100 MHz sampling, however they were also tested at 80 MHz clock as used in AMIGA underground electronics. The cut-off frequency in all boards has been set to 50 MHz. Tests with 80 MHz sampling frequency were performed in conditions slightly deviated from the golden rules. For that frequency small (actually negligible) aliasing was recorded in some channels. The cut-off higher than half of the sampling frequency may introduce aliasing and violate the integral linearity of the analog section. Too small values can smooth the edges of the ADC traces, elongate their rising edges and tails, in consequence affect the ToT rate and change the rising time crucial for detection of neutrinos in horizontal and very inclined showers. D. Noise At 40 MHz the noise level is below 1 ADC-count and it is comparable with the noise in the Cyclone boards. For 80 MHz the average noise reaches and for 100 MHz is on the level of 1.6 ADC-counts. The noise level is twice as high as in all Cyclone boards (compare [8, Fig. 8]). E. Resolution Originally, the structure of the ADC trace is as follows: 256 time bins before the trigger and 512 time bins after the trigger. Data from the ADC are continuously written into a circulating buffer (dual-port RAM inside the FPGA) and when the trigger appears this buffer is frozen and data are written into the next buffer with 512 time bins length. In total, 768 time bins for 40 MHz sampling correspond to a 19.2 interval ( ), when the shape is investigated. Higher sampling, with the same interval would require longer buffers and in consequence more data transferred from the surface detector to the Central Data Acquisition System (CDAS). It would seriously complicate the existing structure of the CDAS software. However, the analysis of registered events shows that data in the first 128 time bins and the last 256 time bins appear mainly for the events triggered by ToT, the contribution of which is much smaller than Threshold trigger (T1). Detectors are calibrated for ca. 100 Hz for the T1 and only 2 Hz for the ToT. Data concentrate mainly in a range of time bins It means, if the ADCs are working with 80 MHz sampling full data range (0 767 time bins), this would correspond to 9.6 ( ). Only a small part of data would appear outside this range. In order not to lose data and keep compatibility with standard data, data is written in buffers with double size (

3 1694 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 ). When the event has been completely written, an additional FPGA routine checks a contribution of signals in the first 256 and the last 512 time bins. If the signal looks like noise or a contribution is negligible and irrelevant, only data from a range from time bins are transferred to the CDAS (256 before and 512 after the trigger, which corresponds to the 512th time bin). However, if the significant signal is detected outside this range, two consecutive bins are averaged and to the CDAS still only data from 768 time bins are transferred. Thresholds for the 1st 256 and the last 512 time bins are set in a separate register. F. DCT Spectral Trigger Surface detectors in the Southern Auger Observatory are equipped with 3 PMTs and are working with 3-fold (Threshold) and 2-fold (ToT) coincidences. The design for the Auger North anticipates a single PMT only (due to a limited budget, the PMTs are one of the most expensive components of the detector). The coincidence technique for a noise suppression cannot longer be used. A higher threshold reduces a noise. However, it reduces simultaneously the sensitivity for non-standard events. The analysis of Auger South data shows that all horizontal and very inclined showers crossing almost the entire SD array fire only few detectors. Due to short PMT pulses from the narrow flat muon front the ToT trigger is useless as required at least 13 fired time bins. Even for 100 MHz sampling this corresponds to at least 130 ns. These pulses are on the level of 80 ns. On the other hand the Threshold trigger requires 3-fold coincidences. These are too strong requirements. Often the signal in a single channel is just below the threshold and the 3-fold coincidence fails. The natural enhancement is a pulse shape recognition independently of the amplitudes. The trigger based on the Discrete Cosine Transform allows a registration of events, with expected PMT pulse shapes: i.e., short peaks with fast attenuated tails coming from horizontal and very inclined showers [6]. However, this trigger cannot be implemented in existing front-end boards equipped with ACEX or Cyclone FPGA chips, due to a lack of DSP blocks. The DCT trigger [6] requires a powerful FPGA with a large amount of DSP blocks. The EP3C40F324C7 chip contains enough DSP blocks for an implementation of three DCT engines. The DCT based on only real coefficients in the frequency domain, provides much more sensitive trigger conditions and a simpler interpretation in comparison to a discrete Fourier transform (DFT) which is based on complex coefficients [7]. It also offers a scaling feature. The DCT triggers have been tested in the lab. A single channel was fed with the signal from a pattern generator with a programmed shape: a sharp rising edge and an exponentially attenuated tail (simulating a PMT signal). An event has been recorded if the signal shape matched the acceptance lane in a frequency domain. The preliminary tests were fully satisfactory. IV. TESTS IN THE FIELD Six selected prototype boards have been installed in test surface detectors on the Pampa Amarilla on the Apr 7th, Fig. 1. T1, T2 and ToT rates for surface detectors: Cuixart, Brisa, Matias (80 MHz sampling) and Alexis, Gaita, Anabel (100 MHz sampling). Data from the 3rd generation Cyclone FEB within Mar 1 Apr 7, 2009 have been shown as reference, standard Auger level : Hz for the T1, Hz for the T2. An expected level for the ToT is 102 Hz, however due to many reasons the ToT rate is often higher than expected in many SD tanks. For used test detectors the ToT level is 5Hz, much higher than in good working ones. Three surface detectors : Cuixart, Brisa, Matias have been equipped with FEB configured for 80 MHz sampling (FEB : #3, #6, #10), while Anabel, Alexis, Gaita were configured for 100 MHz sampling (FEB : #4, #8, #9), respectively. Initially all prototype boards have been temporarily installed and activated in the lab test detector in Malargüe. The main goal was to calibrate the high voltage (HV) for the PMT and run a data acquisition. The calibration procedure, utilizing the method of successive approximations, adjusts the HV independently for three PMT in order to achieve T1 trigger rate (threefold coincidences in a single time bin at 1.75 VEM threshold corresponding roughly 90 ADC-counts above pedestal). The estimated current for a Vertical Equivalent Muon (VEM) is the reference unit for the calibration of ADC traces signals [10].

4 SZADKOWSKI: TRIGGER BOARD FOR THE AUGER SURFACE DETECTOR WITH 100 MHZ SAMPLING AND DCT 1695 Fig. 2. Noise in FEB working with 80 MHz (above) and 100 MHz (below) sampling, respectively. Each vertical line corresponds to a range from minimal to maximal noise among six channels of the FEB. For 80 MHz sampling the noise increases on average of only 0.5 ADC-counts, however fluctuations of the noise are lower in comparison to the standard Cyclone FEB. For 100 MHz sampling maximal noise is still on the level 2 ADC-counts, although on average increases by ca. 1 ADC-count. Since May 12, 2009 there are no data for Alexis and Gaita due to communication problems with the CDAS. The minimal noise in these tanks was a little bit smaller in comparison to Anabel tank. Generally, the noise in the standard FEB is lower, however for some channels fluctuations are huge and the noise reaches even more than 3 ADC-counts. The calibration procedure was developed many years ago and it was optimized for the standard Auger sampling rate (40 MHz). There were neither time nor resources to modify it for other sampling rates. The standard Auger procedure has been used also for the calibration of detectors for 80 and 100 MHz sampling rate. The HV was tuned for each FEB for three FPGA codes, running the data acquisition with 40, 80 and 100 MHz sampling. The precise calibration takes several minutes. For 40 MHz sampling, the HV for all PMT has been tuned very precisely. However, for 80 or 100 MHz for some FEB precise calibration failed. For these configurations the HV was tuned in the fast mode. A comparison of the HV level for precise mode versus fast mode showed, that the fast mode can be successfully used for all sampling rates. Finally, the data acquisition has been run in all FEB for all three sampling rates. A. Trigger Rates The successful calibration of the HV in the real detector on the pampas allowed the normal data acquisition via the standard Auger wireless network. The rate of the Threshold trigger (T1 hardware first level trigger) decreased by in comparison to the standard level for regular boards, where the ADCs are driven by the 40 MHz clock. This shift may come from not very well optimized HV, due to the use of the standard calibration procedure. The T2 rate (software trigger in the UB) is very close to the expected standard level. The level of the ToT trigger slightly decreased. Also a lower level of fluctuations is observed. All three trigger rates for all six installed FEB confirm a very good agreement with the expected, standard Auger ranges (see Fig. 1). B. Noise The noise in the FEB under field conditions remains roughly on the same level. Higher noise for 80 and 100 MHz, however, does not disqualify the boards. It reduces only the resolution of the signal conversion from 10 to. This resolution was still satisfactory for preliminary tests (see Fig. 2). C. Diagnostic Mode Data from the surface detectors are collected in root files, which apart from ADC traces contain calibration and GPS data, detector and trigger information as well as several histograms regarding peaks, charge, base, offset etc. The structure of the database and the data transfer is fixed and it is practically impossible to extract additional information in a standard way. The normal data acquisition supports also a monitoring channel, which provides slow control data like the temperatures of the PMTs and the electronic boxes, voltages, currents. However, monitoring files are independent of events and they cannot be used for additional information extraction. The analysis of the ADC traces shows that in all registered events the last 8 words contain only noise. So, the area of ADC

5 1696 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 Fig. 3. Intervals between the consecutive rebooting of the Unified Boards in reference Auger surface detectors in 2008 (above) and for detectors equipped with the 4th generation of the FEB within Apr 7th Jul 21st, 2009 (below). Each point corresponds to a real shower registered in at least 4 surface detectors simultaneously. Times between rebooting for the new boards are in the same range as times for the reference 3rd generation boards. This confirms the stability of the new FEB at least on the same level as the old ones. traces corresponding to the 760th 767th time bin can be used for inserting data related to a particular event, without any modification of the transmission channel and database structure. All prototype FEBs installed in test surface detectors were working in the diagnostic mode. Thresholds for T1, ToT triggers in the fast channel, thresholds in the slow channel, time counting since last UB rebooting, control data etc. have been inserted on the tail of traces. Only during a scientific analysis of ADC traces, that data ( suspicious from the point of view of physics) have to be ignored. 1) Time Since Last Rebooting: The FPGA code can additionally support a 52-bit counter (driven by the same clock as the ADC) to register the interval since the last UB rebooting. Only higher 30 bits are read. This gives, 005 and 0.1 s time resolution for 100, 80 and 40 MHz sampling, respectively. Data from registers, counters etc. are inserted on the fly into the ADC data stream at the 8 last 64-bit words being stored in the temporary shower memory buffer implemented as the dual-ported RAM. In comparison with data from 2008, when 6 test detectors were working also in the diagnostic mode, there are no observable differences in intervals of continuous running. Cyclone III design has proven to operate stably together with the UB (see Fig. 3). 2) Trigger Thresholds: Registers in the FPGA keeping thresholds for T1, ToT triggers in the fast channel as well as thresholds for the slow channel can be read by the UB. However, these variables have not been taken into account for the implementation of the database and transmission structure. Huge daily temperature variations in the electronic box (40 50 ) cause a pedestal drift, which has to be compensated by tuning of the trigger thresholds in order to keep constant relative thresholds and above pedestals (corresponding 1.75 and 0.2 VEM) for T1 and ToT, respectively. Thresholds are controlled from the UB. The UB calculates corrections on the basis of the current trigger rate. In comparison to results from the reference data (2008) from detectors equipped with the 3rd generation of the FEB, the stability of thresholds in the new Cyclone III FEB is at least on the same level (see Fig. 4). This confirms the high reliability of the new design.

6 SZADKOWSKI: TRIGGER BOARD FOR THE AUGER SURFACE DETECTOR WITH 100 MHZ SAMPLING AND DCT 1697 Fig. 4. Thresholds for the T1 triggers for the reference FEB (above) and investigated 4th generation boards (below). The thresholds should correspond to 1.75 VEM ( 85 ADC-counts). For reference detectors Beto, Iaia and Fierita thresholds are kept stable for entire year. However, for Alberto a strange deviation is observed. The relative thresholds for the Cyclone III boards are a little bit smaller in comparison to the Cyclone boards. We estimate that a discrepancy is relatively low and is a consequence of the old, not optimized for 100 MHz sampling HV calibration procedure. Nevertheless, thresholds show a very good stability. D. Edge Rise Time The surface array is sensitive to very inclined and even horizontal air showers. The total depth of the atmosphere increases from 1740 at 60 zenith angle to 31 at 90. The shape of a signal produced by very inclined air showers depends on the depth in the atmosphere where the first interaction occurs. Neutrinos, due to their small cross section, can penetrate the atmosphere deeply and interact at all possible slant depths. Neutrino induced showers can originate from parts below the region where showers induced by nuclear or electro-magnetic primaries start. ADC traces of such young showers are extended in time, compared to that of old ones, where a sharp, narrow peak is expected [5]. Higher sampling frequency allows an improved measurement accuracy of the edge rise time for signals from the PMT. This parameter is crucial for an analysis of neutrino induced showers recognition. Figs. 5 and 6 show traces from very inclined shower ( ). Four SD have been hit: two equipped with standard Cyclone FEB (#940 and #943) and two with the prototype Cyclone III FEB (#956 Matias, 80 MHz sampling and #944 Anabel, 100 MHz sampling). ADC traces for the standard 40 MHz sampling are concentrated in 8 10 time bins, corresponding to a signal width of. The same interval is sampled with higher resolution in Matias and Anabel detectors and corresponds to and, respectively. A time of rising edges has been estimated standardly as ns (corresponding to a single or two time bins). However, Cyclone III FEB gives better estimation on ns (Figs. 5 and 6). E. Resolution The procedure of automatic data range selection described in the Sections III, III.E has been implemented in the field. All data corresponded to either (80 MHz sampling) or (100 MHz sampling). A lack of compressed data is a consequence of a small statistics (an exposition in only 6 detectors over 3 months). Nevertheless, even a small statistics strengthened the evidence, that higher sampling improves time resolution and it gives new physical information. With a higher sampling more details in the ADC traces are visible (see plots in Figs. 5 and 6). For very high zenithal angles the Earth s magnetic field may significantly deflect charged muons and split showers [5].

7 1698 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 Fig. 5. A very inclined event (# , =83:4 ). The graph shows traces from a standard Auger detector (#940), and from Matias (80 MHz sampling). For the standard 40 MHz sampling the rising time is either a single time bin 25 ns (a jump from a pedestal to ca. 500 ADC-counts) or even two time bins 50 ns (the strongest signal). For 80 MHz sampling signals in all channels jump from the pedestal level to a maximal values in a single time bin 12.5 ns. It is clearly visible that the higher sampling allows a better estimation of the rising time. Fig. 7. The DCT trigger rate registered in the real surface detector for various additional Thresholds and occupancies. The width of the acceptance lane has been fixed to 630%. The threshold of 40 ADC-counts corresponds roughly to 0.8 VEM. Twice lower threshold = 0:4VEM(20 ADC-counts) still cuts off noise and keeps a trigger rate on a reasonable level. Fig. 6. The graph shows traces for standard Auger detector (# MHz sampling) and Anabel (# MHz sampling) for the same shower # For the standard 40 MHz sampling the rising time corresponds to two time bins 50 ns (a jump from the pedestal to ca. 400 ADC-counts). For 100 MHz sampling signals in all channels jump from the pedestal level to a maximal values in a single (10 ns in ADC1) or two time bins (20 ns in ADC2 ADC3). The credibility of a rise time estimation (10 20 ns) is higher than for 40 MHz sampling with a single time bin (25 ns). Higher sampling could show a deviation from an expected exponential attenuation for a short traces, indicating a convolution of showers with opposite charge. F. DCT Spectral Trigger The DCT spectral trigger has been tested in a test tank close to the Assembly Building in the Malargüe laboratory. The 16-point DCT is scaled to the 1st harmonics, 0th coefficient is trivial, only 14 DCT coefficients are independent [6]. DCT trigger has been tested in the 1-fold coincidence mode: all 3 PMTs were giving a contribution to the final trigger (this mode corresponds to an anticipated configuration in the Auger North with a single PMT). In histograms (Fig. 9), however, only traces from triggered channels were shown. An implementation of three DCT engines only allowed taking into account 11 DCT coefficients simultaneously, some coefficients have to be avoided due to a lack of DSP blocks in the selected FPGA. have been ignored due to a weak change with the attenuation factor [see Fig. 8(b)]. Hadron induced showers with dominant muon component give an early peak with a typical rise time of 1 to 2 time bins (by 40 MHz sampling) and decay time of the order of 80 ns [11]. This corresponds roughly to an exponential factor for the attenuated tails of ( ). DCT coefficients are independent of the amplitude. They are determined by the shape only. This causes that the DCT trigger could also be accidentally generated by very low noise pulses with the required characteristics. In order to cut this type of the spurious triggers, the spectral trigger was also supported by the amplitude threshold of ( ). Pulses above this threshold are analyzed next with the DCT engines. Due to noise and other factors which can distort the shape of the PMT pulse, strict conditions imposed on all 11 coefficients are too strong. The DCT trigger has been generated if a subset of DCT coefficients (similar to the Occupancy in the ToT) has been simultaneously fired. Fig. 7 shows the DCT trigger rate for additional threshold and 40 ADC-counts for the Occupancy 7 and 8, respectively. Keeping in mind that T1 rate is calibrated for ca. 100 events/s and ToT rate is ca. 2 events/s, the condition for the DCT coefficients have been established to get a spectral trigger rate on the level of events/s. This corresponds to the and the Threshold of 40 ADC-counts above the pedestal. For the assumed attenuation factor the lower and upper scaled thresholds (calculated according to [6, Eq. (11)] are automatically tuned inside the FPGA to keep an arbitrary spectral trigger rate. In contrast to [6] the investigated period was 150 ns, the shift register did not contain empty chains for a delay only required for enlarged time interval analysis (compare [6, Fig. 12]). Due to assumed 80 ns pulse length, a compact shift register configuration was enough. Results from preliminary measurements are very satisfactory. The spectral trigger can be tuned to register traces with an assumed shape. The DCT routine has been programmed to recognize and to trigger ADC traces with a huge jump from the

8 SZADKOWSKI: TRIGGER BOARD FOR THE AUGER SURFACE DETECTOR WITH 100 MHZ SAMPLING AND DCT 1699 Fig. 8. Shapes of traces for various attenuation factors (Left) with a corresponding DCT coefficients (Right). The signal jumps from the pedestal to the amplitude = 100 ADC-counts. Traces with 0:62 are short with a length 60 ns. X =X coefficients vary in a relatively wide range, except for X, which next can be ignored in FPGA DCT routine. Fig. 9. Histogram of traces for selected attenuation factors. For 0:50 the separation of sub-histograms is pretty good. For larger (shorter traces) the separation is a little bit worse. However, it is a consequence of arbitrarily assumed not optimized parameters in preliminary measurements. pedestal to the maximal value and afterwards exponential attenuation. The attenuation factor changed from 0.14 to 1.1 for consecutive measurements. From exact DCT coefficients corresponding to the assumed, the acceptance lane for the trigger has been created by increasing and decreasing the DCT coefficients for high and low thresholds in the FPGA by 30%. Preliminary results from Fig. 9 suggest to correlate the width of the acceptance lane with the factor (lower lane for higher ) and the occupancy. The occupancy: corresponds to too strong restrictions (due to noise) and provides very low trigger rate. The threshold for noise removal decreased even to 10 ADC-counts, but did not significantly increased a trigger rate. For preliminary measurements the optimal parameters were: and. Higher power consumption (due to 100 MHz sampling and DSP blocks) did not violate the power budget. The DAQ with the DCT trigger worked stable continuously for several weeks. V. CONCLUSION The main aim of the tests with prototype FEB was a verification of the new design and data acquisition with 100 MHz sampling rate in a single FPGA chip without the support of an additional dual-ported RAM for the slow channel in real Argentinean pampas conditions and has been fully achieved. Preliminary laboratory tests showed, however, a small imperfection of the analog section. Nevertheless, the new design was focused on the digital part and the reliability of this section has been proven both in the lab and in field tests. Additionally, the new spectral triggers based on the Discrete Cosine Transform were preliminary and successfully tested under field conditions. Despite of the non-optimized analog section and old calibration procedure designed for the standard 40 MHz sampling, all prototype FEB installed in the test surface detectors were working pretty close to the standard Auger parameters: trigger rates, noise level, cooperation with the UB (uptime). The algorithms for the data acquisition with 100 MHz sampling (both for the standard Auger approach as well as for the extension with the spectral triggers) in the Cyclone III FPGA chips have been successfully tested and can be implemented in the Front-End boards being developed for the Auger North. This Front-End Board has been fabricated in the R&D phase before a mass production for the Auger North investigating specific techniques of triggering and testing the DAQ with a high sampling rate. The FEB has been designed to be compatible with the UB and to be tested in the surface detectors on the Auger South. This board has also been used in the 320 MHz prototype for AMIGA in the surface section [12]. It is equipped with a very powerful FPGA (compared to the standard Auger FEB) containing enough resources for NIOS processor implementation. The NIOS can replace a standard additional microcontroller (implemented currently as the Surface Single Board Computer). This Front-End board supports also the tests of the RFI filtering in the FFT + Median filter + Hilbert transform (for the envelope generation) in the prototype of the Front-End for the Auger Engineering Radio Array (AERA). The test system utilizes two channels sampled by two 90 MHz clocks with a relative shift of. The effective sampling is 180 MHz. This board with the standard Auger infrastructure allows simple tests focused on the RFI filtering and the trigger without a support of the big external RAM [13].

9 1700 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 4, AUGUST 2011 Fig. 10. A view of the prototype FEB of the 4th generation with the single Cyclone III chip. ACKNOWLEDGMENT The author thanks Y. Kolotaev from the Siegen University for the PCB design. REFERENCES [1] J. Abraham et al., Properties and performance of the prototype instrument for the Pierre Auger Observatory, Nucl. Instrum. Meth., ser. A, vol. 523, pp , May [2] Z. Szadkowski and D. Nitz, Implementation of the first level surface detector trigger for the Auger Observatory Engineering Array, Nucl. Instrum. Meth., ser. A, vol. 545, pp , Jun [3] Z. Szadkowski, The concept of an ACEX cost-effective first level surface detector trigger in the Pierre Auger Observatory, Nucl. Instrum. Meth., ser. A, vol. 551, pp , Oct [4] Z. Szadkowski, K.-H. Becker, and K.-H. Kampert, Development of a new first level trigger for surface array in the Pierre Auger Observatory based on the Cyclone Altera FPGA, Nucl. Instrum. Meth., ser. A, vol. 545, pp , Jun [5] L. Nellen, Detection of very inclined showers with the Auger Observatory, presented at the 29th Int. Cosmic Rays Conf., Pune, India, Aug [6] Z. Szadkowski, A spectral 1st level FPGA trigger for detection of very inclined showers based on a 16-point Discrete Cosine Transform for the Pierre Auger Observatory, Nucl. Instrum. Meth., ser. A, vol. 606, pp , Jul [7] Z. Szadkowski, 16-point discrete Fourier transform based on the Radix-2 FFT algorithm implemented into Cyclone FPGA as the UHECR trigger for horizontal air showers in the Pierre Auger Observatory, Nucl. Instrum. Meth., ser. A, vol. 560, pp , May [8] Z. Szadkowski, T. Bäcker, K.-H. Becker, P. Buchholz, I. Fleck, K.-H. Kampert, M. Rammes, J. Rautenberg, and O. Taşcău, The 3rd generation front-end cards of the Pierre Auger surface detectors: Test results and performance in the field, Nucl. Instrum. Meth., ser. A, vol. 606, pp , Jul [9] Clock Networks and PLLs in Cyclone III Devices, [Online]. Available: [10] D. Allard et al., The trigger system of the Pierre Auger surface detector: Operation, efficiency and stability, in Proc. 29th Int. Cosmic Rays Conf., Pune, India, Aug. 2005, astro-ph/ [11] M. Aglietta et al., Response of the Pierre Auger Observatory water Cherenkov detectors to muons, in Proc. 29th Int. Cosmic Rays Conf., Pune, India, Aug. 2005, FERMILAB-CONF E-TD. [12] Z. Szadkowski, Triggers, data flow and the synchronization between the Auger surface detector and the AMIGA underground muon counters, presented at the IEEE-NPSS Proc. 17th Real Time Conf., Lisbon, Portugal, May [13] Z. Szadkowski, H. Gemmeke, A. Haungs, K.-H. Kampert, C. Rühle, and A. Schmidt, An FPGA based trigger and RFI filter for radio detection of cosmic rays, presented at the IEEE-NPSS Proc. 17th Real Time Conf., Lisbon, Portugal, May 2010.