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1 HIGH VOLTAG IGNITION COIL DRIVR POWR I.C. TYP V cl I cl I CC 360V A 50mA PRIMARY COIL VOLTAG INTRNALLY ST COIL CURRNT LIMIT INTRNALLY ST LOGIC LVL COMPATIBL INPUT DRIVING CURRNT QUASI PROPORTIONAL TO COLLCTOR CURRNT SINGL FLAG-ON COIL CURRNT LOW VOLTAG CLAMP THRMAL SHUTDOWN DSCRIPTION The is a high voltage power integrated circuit made using the STMicroelectronics VIPower M-3 technology, with vertical current flow power darlington and logic level compatible driving circuit. The enable pin allows to externally block the switch when the input is on. Built-in protection circuit for coil current limiting and collector voltage clamping allows the device to be used as smart, high voltage, high current interface BLOCK DIAGRAM V IN PowerSO- in advanced electronic ignition system. If the input signal from the micro happens to remain high, the device protects itself against over-heating by forcing collector current to smooth decrease (low voltage clamp feature) and no undesidered spark occurs (see figure 4). DRIVR QUASI PROP. BAS CURRNT BD HV C DIAGNOSTIC OUTPUT LIMITR R SNS V F V R - V LIM RFRNC V TH THRMAL PROTCTION SN LGND GND September 203 DocID9672 Rev 6 /9

2 ABSOLUT MAXIMUM RATING Symbol Parameter Value Unit HV c Collector voltage (Internally limited) -0.3 to V clamp V I C Collector current (Internally limited) A I C(gnd) DC current on mitter Power ±.5 A Driving stage supply voltage -0.3 to 7 V I s Driving circuitry supply current ± 200 ma I s(gnd) DC current on Ground pin ± A V IN Input voltage -0.3 to V I IN Maximum Input Current 0 ma f IN Logic Input Frequency in Operative Mode DC to 50 Hz V OUT(flag) Output Voltage Primary Threshold Current Level -0.3 to V I OUT(flag) Flag Output Current 0 ma P max Power Dissipation (T c =25 C) 25 W s/b Self Clamped nergy during Output Power Clamping (See figure 2) 275 mj V SD SD voltage (HV c pin) ± 4 KV V SD SD voltage (nable pin) +.5 ; -2 KV V SD SD voltage (Other pins) ± 2 KV I BD Input Darlington Base Current 50 ma V BD Input Darlington Base Voltage Internally limited V T j Operating Junction Temperature -40 to 50 C T stg Storage temperature Range -55 to 50 C V Maximum nable Voltage -0.3 to 5.5 V I Maximum nable Current ± 50 µa THRMAL DATA Symbol Parameter Value Unit R thj-case Thermal resistance junction-case (MAX) C/W R thj-amb Thermal resistance junction-ambient (MAX) 5 C/W PIN FUNCTION No Name Function - 5 LGND Signal Ground GND mitter Power Ground 6 nable (*) 7 Logic Supply Voltage 8 BD Base Darlington 9 INPUT Logic input channel (Internal Pull Down) FLAG Diagnostic Output Signal (Open mitter) TAB HV C Primary Coil Output Driver (Open Collector) (*) When grounded the Input is nabled CONNCTION DIAGRAM (TOP VIW) Pin and Pin 5 must be externally connected to Pins 2 4. BD INPUT FLAG LGND GND GND GND LGND TAB HV C 2/9

3 LCTRICAL CHARACTRISTICS (5.3V < V bat < 24V; =5V ± %; -40ºC < T j < 25ºC; R coil =580mΩ; L coil =3.75mH unless otherwise specified; See note ) Symbol Parameter Test Conditions Min Typ Max Unit V cl High Voltage Clamp I coil =6.5A V V lcl Low Voltage Clamp I coil =6.5A; T j =T sd V V ce(sat) Power Stage Saturation Voltage I C =6A; V IN =4V.5 2 V I CC(stdby) Stand-by Supply Current IN=Off ma I CC DC Logic Current V b =6V; I C =6.5A; f=0hz; Load = Coil; =5.5V 40 ma I CC(peak) Peak DC Logic Current during On Phase I C =6.5A 0 50 ma DC Logic Voltage V I cl Coil Current Limit -40ºC < T j < 25ºC (See note 2) 9 A I c(off) Output Off State Current IN=Off; V HVC =24V; =5V; T j =25ºC 5 ma T Ic_ctr Thermal Temperature Output Current Control OUT=On 50 (*) ºC V INH High Level Input Voltage =4.5V 4 V V INL Low Level Input Voltage =5.5V V V IN(hyst) Input Threshold Hysteresis 0.4 V I INH High Level Input Current V IN =4V 0 µa I INL Low Level Input Current V IN =0.8V 0 30 µa I INpd Input Active Pull Down V IN =4V 0 µa V diagh High Level Flag Output Voltage R XT =22KΩ; C XT =nf (See note 3) - V V diagl Low Level Flag Output Voltage R XT =22KΩ; C XT =nf (See note 3) 0.5 V I diagth Coil Current Level Threshold T j =25ºC A I diagtd Coil Current Level Threshold Drift (See figure ) I diag High Level Flag Output Current I C > I diagth ; V diag =3V 0.5 ma I diag(leak) Leakage Current on Flag Output V IN =Low; =5.5V µa V F Antiparallel Diode Forward Voltage I C = -A 2 V s/b Single Pulse Avalanche nergy L=6mH; I C = 8A (See figure 2) 80 mj t ON Turn-on time R c =0.5Ω; L c =3.75mH; T j =25ºC; V bat =3V (See figure 6) 5 µs t OFF Turn-off time R c =0.5Ω; L c =3.75mH; I C =6.5A; T j =25ºC; V bat =3V (See figure 6) 5 25 µs T sd Thermal shut-down intervention 50 ºC V H High Level nable Voltage V IN =V INH ; OUT=Off (See Note 4) 2 V V L Low Level nable Voltage V OUT free to follow V IN 0.40 V Note : parametric degratation are allowed with 5.3<V b <V and V b >24V. Note 2: the primary coil current value I cl must be measured ms after desaturation of the power stage. Note 3: no internal Pull-down. Note 4: if NABL pin is floating OUT=Off for every input status. (*) Internally Limited 3/9

4 LCTRICAL CHARACTRISTICS (continued) Symbol Parameter Test Conditions Min Typ Max Unit High Level Sinked nable I H V Current =5V 500 µa Low Level Sinked nable I L V Current <0.4V µa V BD(off) Base Darlington Voltage Off V =V H V V BD(on) Base Darlington Voltage On V IN =V INH ; V =V L ; I C =6.5A.8 V PRINCIPL OF OPRATION The is mainly intended as a high voltage power switch device driven by a logic level input and interfaces directly to a high energy electronic ignition coil. The input V IN of the is fed from a low power signal generated by an external controller that determinesboth dwell time and ignition point. During Vin high ( 4V) the increases current in the coil to the desired, internally set current level. After reaching this level, the coil current remains constant until the ignition point, that corresponds to the transition of Vin from high to low (typ..9v threshold). During the coil current switch-off, the primary voltage HV C is clamped at an internally set value Figure : Flag current Vs. temperature V cl, typically 380V. The transition from saturation to desaturation, coil current limiting phase, must have the ability to accomodate an overvoltage. A maximum overshoot of 20V is allowed. FDBACK When the collector current exceeds 6.5A, the feedback signal is turned high and it remains so, until the input voltage is turned-off. OVRVOLTAG The can withstand the following transients of the battery line: -0V/2msec(R i = Ω) +0V/0.2msec (R i = Ω) +50V/400msec (R i = 4.2 Ω, with V IN = 3V) Figure 2: Single pulse avalanche energy capability (mj) Tc=25º Tc=50º L (mh) 4/9

5 Figure 3: Self Clamped Inductive Switching Current Vs. Time Figure 4: Low voltage clamp feature 8 Inductive Current (A) T=25º 6 4 T=50º Time in Clamp (µsec) Figure 5: Typical application diagram µp +5V µf 0nF K K K V IN FLAG BD nf 8K LGND GND HV C V bat NABL pin can be alternatively connected to LGND 5/9

6 Figure 6: Switching time for inductive load V bat R gen V gen V gen 0V V bat 3V t ON t OFF D.U.T C t t 6/9

7 PowerSO- MCHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A (*) A B B (*) C C (*) D D (*) (*) e F F (*) H H (*) h L L (*) α 0º 8º 0º 8º α (*) 2º 8º 2º 8º (*) Muar only POA P03P H 2 0. A B e 0.25 B DTAIL "A" B SATING PLAN A C 4 A A F h D = D= = = SATING PLAN A DTAIL "A" L α P095A 7/9

8 PowerSO- SUGGSTD PAD LAYOUT TUB SHIPMNT (no suffix) C B CASABLANCA MUAR A A C TAP DIMNSIONS According to lectronic Industries Association (IA) Standard 48 rev. A, Feb 986 Tape width W 24 Tape Hole Spacing P0 (± 0.) 4 Component Spacing P 24 Hole Diameter D (± 0./-0).5 Hole Diameter D (min).5 Hole Position F (± 0.05).5 Compartment Depth K (max) 6.5 Hole Spacing P (± 0.) 2.27 All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.) Casablanca Muar TAP AND RL SHIPMNT (suffix 3TR ) RL DIMNSIONS Base Q.ty 600 Bulk Q.ty 600 A (max) 330 B (min).5 C (± 0.2) 3 F 20.2 G (+ 2 / -0) 24.4 N (min) 60 T (max) 30.4 All dimensions are in mm. B All dimensions are in mm. nd Start Top cover tape No components 500mm min Components mpty components pockets saled with cover tape. No components 500mm min User direction of feed 8/9

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