Le79489 SLIC Device Evaluation Board User s Guide. Rev. B, Ver

Transcription

1 SLIC Device Evaluation Board User s Guide Rev. B, Ver. 007

2 For more information about all Zarlink products visit our Web Site at Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively Zarlink ) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink s conditions of sale which are available on request. Purchase of Zarlink s IC components conveys a license under the Philips IC Patent rights to use these components in an IC System, provided that the system conforms to the IC Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE

3 SLIC Evaluation Board User s Guide Table of Contents Table of Contents.0 Introduction....0 Board Setup and Connection.... Power Connections.... Telephone Line Interface.... Analog Signal Connections....4 Digital Interface....5 Interconnecting to SLAC Device Evaluation Boards Board Operation and Control Controlling the SLIC Jumper Settings JR SLIC Control Source JR BSWTH Pin Connection JR4 BSWEN Connection JR5 AUXIN Connection JR9 VBREF Option JR0 Test Relay Driver Control DIP Switches S, S, S Component Carriers CC and CC Two-Wire Impedance and Gain Control Loop Detect Threshold Setting (RD/CD) Battery Feed Control and Setting (RDC, CDC, RDC) LED Indicators DA, DB, and RINGOUT Banana Jacks Breadboard Area Software Operation WinSLAC Software SLACIFP Software SLIC Circuit Simulation Models SLIC Device Simulation Model ExLeple Schematic Circuit Representative Transmission Performance Ω Line (Default) Ω Line German Line Evaluation Board Standalone Operational Test Board Operation LED Indicator Test Setup to Verify Ringing Evaluation Board Schematic... 6 SLIC Evaluation Board User s Guide

4 .0 INTRODUCTION Figure The SLIC Evaluation Board provides a platform to evaluate the different capabilities of the SLIC device. The evaluation board's two modes of operation, INTERNAL and EXTERNAL, provide a flexible platform to evaluate the SLIC device. All digital control signals and voice band signals have test points for easy probing. All user selectable components are mounted on component carriers for easy modification where required. A surge protection circuit, robust enough to meet Bellcore GR-089-CORE specifications, is part of the telephone interface. All power is brought to the board via a single keyed connector. LEDs are provided to indicate when the loop detect/ground-key, TESTOUT, RINGOUT, and BSWOUT circuits are active or non-active. Detailed device explanations, operational circuit descriptions and required formulas can be found in the Linecard Products Data Book and the individual SLIC device data sheets. The SLIC evaluation board physical layout is shown in Figure. SLIC Evaluation Board User s Guide

5 .0 BOARD SETUP AND CONNECTION The SLIC evaluation board operates either standalone or in conjunction with an Zarlink SLAC device evaluation board. Standalone operation is supported using manual switch settings to control operation. When connected to a SLAC device board, control and digital transmission access is provided through the programmable pins of the SLAC device, which is then controlled by Zarlink s computer interface evaluation software.. Power Connections Input power is supplied to the board via the 0-pin connector PW. The power cables are color coded and labeled at the banana jack. The following chart details all ten cables by color and description. Pin # Cable Color Label Description Black Common ground for VBAT White VBAT Main Battery supply Gray VBAT Low Battery supply (typically 4 V) 4 Blue VTMG Not required 5 Violet RING SRC External ringing signal input 6 Orange AUX_VCC Supply for all 5 V requirements except the SLIC 7 Red VCC SLIC supply only 8 Brown Common ground 9 Green VNEG Not required 0 Yellow VEE Fixed 5 V supply The SLIC board does not require the V TMG or V NEG cables to be connected as these inputs do not go to or affect the operation of the SLIC device. (A common cable is used on all Zarlink SLIC evaluation boards, and the extra connections represent those possibly used with other devices or boards.). Telephone Line Interface To interface the evaluation board to a telephone station set, simply plug the phone connector into the RJ- modular jack. The TIP and RING banana jacks are connected in parallel with the RJ- jack and allow the evaluation board to also be interfaced to telephony test equipment. A tip/ring surge protection circuit is included on the board. The protection circuit is placed in series with the tip and ring leads as they connect to the A and B leads of the SLIC. The circuit is composed of a diode bridge, a Teccor Sidactor protection device, and the thick-film hybrid fusing resistor assembly (FRP). While this circuit is not the definitive type, it is typical of a circuit that will withstand the rigors of Bellcore testing.. Analog Signal Connections Analog four-wire signal connections are provided to the SLIC by shielded BNC connectors on the board. One connector, VRX, is used for connecting an analog input signal to the SLIC, where that signal will appear across the tip/ring two-wire interface. The other connector, VTX, is an analog signal output representing the two-wire signal, which appears across tip and ring..4 Digital Interface The SLIC is an analog part but may be placed in different operating states through logic control signals, which are presented to the digital control inputs. Five input signals and one output signal comprise the digital interface to the SLIC device. Operation of the SLIC with these control inputs is explained in the SLIC data sheet. The following table gives a general description of the signals: SLIC Evaluation Board User s Guide

6 Name Type Description C Input SLIC control pin. C is the LSB. C Input SLIC control pin. C Input SLIC control pin. C is the MSB. Internally pulled high. OVH Input Overhead control. Set to enables non-metering. Set to 0 enables. V metering. E Input Ground-key/Detect. E= sets the switchhook detect. E=0 sets the ground-key detect. DET Output Indicates when the selected condition of C-C and E is detected..5 Interconnecting to SLAC Device Evaluation Boards Figure In addition to operating in a standalone mode, the SLIC board may be connected to an Zarlink SLAC device evaluation board, utilizing that SLAC device together with the SLIC as the complete front-end system solution of an analog line interface circuit. The SLAC device performs the digital conversion, and through its connection with the Computer Interface (ACIF) Board, provides companded digital input and output of the line circuit. The SLAC device boards have a pair of analog input and output BNC connectors, representing the analog input and output of the SLAC device s channel and are wired directly to the SLIC board s corresponding output and input analog connectors. Control of the SLIC is provided through the digital control cable that is wired from the SLAC device board s control header for that channel to the control signal header on the SLIC board. The INTERNAL/EXTERNAL jumpers on the SLIC board must be placed in the external position to enable this control. A representative connection of the SLIC board to an Zarlink SLAC device board, along with the other major items and their interconnect, is shown in Figure. PCM-4 Digital Analog Telephone ACIF Serial QSLAC SLIC Computer Mouse Notes:. ACIF Computer Interface Board.. QSLAC (SLAC) Device Evaluation Board.. SLIC Device Evaluation Board. SLIC Evaluation Board User s Guide 4

7 .0 BOARD OPERATION AND CONTROL The SLIC board is controlled through on-board dip switches (standalone), through an external control interface (in conjunction with an Zarlink SLAC device board), and by selection of onboard jumpers. Operational performance is programmable by user selection of on-board components. Indicators are also included to provide visual state indication of key functions. User operation and programming selection is described in this section.. Controlling the SLIC The SLIC Evaluation Board can be operated in either an INTERNAL (standalone) mode or EXTERNAL (controlled via a 0-pin header) mode. The INTERNAL mode can be selected by placing the shunts provided on JR between the center and left columns. This allows switches S and S to control the device. The EXTERNAL mode can be selected by placing the shunts on JR between the center and right columns.. Jumper Settings.. JR SLIC Control Source This jumper header allows the SLIC to be controlled by the on-board DIP switches S and S or by an external Zarlink SLAC device board via the ribbon cable provided. Each pin and/or switch can be individually selected for internal (DIP switch) or external (DSLAC /QSLAC) control by changing the JR jumpers. The different jumper positions are shown in Figure. Figure JR Jumper Options JR JR I N T E R N A L E X T E R N A L I N T E R N A L E X T E R N A L JR SHOWN JUMPERED FOR EXTERNAL CONTROL JR SHOWN JUMPERED FOR INTERNAL CONTROL As the board is shipped from Zarlink, the default setting is the EXTERNAL mode. The functions of each of these jumpers and the corresponding signal pins from the DSLAC and QSLAC device boards is shown in the following table. (Refer to the particular SLAC device data sheet for further explanations of their control pin functions.) Jumper Row SLIC Pin SLAC Device Board Control Pins QSLAC Device DSLAC Device P Control Header Pin JR- C CD C JR- C C C JR- C C4 C 5 JR-4 E MCLK/E C4 7 JR-5 OVH C5 C5 * 9 Note: * The Le79C0/Le79C0 DSLAC devices are provided with pin C5. The Le79C0 DSLAC device has pins C through C4 only. The Le79Q0 has the CDx and CDx pins only. SLIC Evaluation Board User s Guide 5

8 .. JR BSWTH Pin Connection This jumper allows automatic battery switching to be disabled by connecting BSWTH to ground, or normal battery switching operation with BSWTH connected to BAT. BSWTH Connection JR Setting BAT Default.. JR4 BSWEN Connection If this jumper is installed, battery switch control is transferred to the BSWEN DIP switch and overrides normal automatic battery switching...4 JR5 AUXIN Connection This jumper, when installed, allows connection of the auxiliary BNC connector to RSN. This would allow external signals such as metering to be summed in to RSN. The default is to not install this jumper...5 JR9 VBREF Option JR9 allows VBREF (SLIC device pin ) to be connected to VBAT or left floating. This will set VBREF to the same voltage as VBAT at the SLIC via D. Default position is pin is shorted to pin. JR9 Setting - BAT Open VBREF Potential Floating..6 JR0 Test Relay Driver Control This jumper allows pin C4 to be set high or low. TESTOUT Status JR0 Setting INACTIVE Default ACTIVE. DIP Switches S, S, S S selects between the on board ring trip bridge components and ring relay and external access to the DA, DB, and RINGOUT pins via the corresponding 4 mm banana jack sockets. S controls the SLIC state (C, C, C) if internal control is selected via JR. S controls OVH and E if internal control is selected via JR, and BSWEN if JR4 is installed..4 Component Carriers CC and CC The two component carriers are designed to accommodate the more commonly changed external components, i.e., the user-programmable components. CC carries the DC feed setting components RDC (R5), RDC (R4), CDC (C) and RFA (R9) along with CBSWEN and the loop detect threshold setting components, RD (R8) and CD (C). CC carries the input impedance programming and receive gain-setting components. The header is arranged to allow a variety of configurations to be supported. The default components supplied with the Evaluation Board are designed to provide a nominal 600 Ω two-wire input impedance using a group delay compensated network comprised of RT (R), RT (R), CT (C6), and an open circuit receive gain of.0 via RRX (R). SLIC Evaluation Board User s Guide 6

9 Figure 4 CD RD RDC CDC RDC CBSWEN R9 JUMPER RRX RTX RTX CTX CC CC.5 Two-Wire Impedance and Gain Control Two BNC connectors, V TX and V RX, provide the audio signal I/O paths for the SLIC device. V TX is the direct output of the SLIC pin. V RX is the four-wire input to the impedance circuit between the SLIC and SLAC devices. Placing the appropriate components on CC can program impedance matching. The interface configuration can be as simple as Diagram or as complex as Diagrams and 4. Diagram is the factory default configuration when the board is shipped. The default components supplied with the Evaluation Board are designed to provide a nominal 600 Ω two-wire input impedance using a group delay compensated network and an open circuit receive gain of.0. SLIC Evaluation Board User s Guide 7

10 Figure 5 Impedance Matching Network Configuration Diagrams RTX RRX RTX VTX RSN RRX VRX Diagram VTX RTX JUMPER RRX RTX RTX CX RSN RTX CX RRX VRX Diagram VTX RA CA RTX RTX JUMPER RSN CA RA RTX RTX VRX Diagram VTX RA CA RRX RTX RTX CX RSN CA RA RTX RTX CX RRX VRX Diagram 4 The component values installed at the factory are calculated using the formulas in the data sheet. The hybrid fuse resistors on the board are 50 Ω each. The G 4 gain value (i.e., SLIC to phone or four-wire to two-wire) used in the Z RX formula (from the data sheet) is..6 Loop Detect Threshold Setting (RD/CD) The Loop Detect Circuit is a filter composed of a resistor (RD) and capacitor (CD) in parallel with each other and in series with the RD pin. Component values for this circuit are chosen to set the threshold and filter point for the off-hook detector to on-hook transition. Components are mounted on CC (refer to Figure ). The values are derived by the following formula, which is also explained in the device data sheet: SLIC Evaluation Board User s Guide 8

11 0. 5mS CD = RD Where: 0.5 ms is the time constant RD is a selected resistance CD is the calculated capacitive value.7 Battery Feed Control and Setting (RDC, CDC, RDC) The components for the loop current circuit of the evaluation board are set to provide a programmed DC loop current (I L ) of approximately 5 ma. The components for the loop current are located on CC. The visual placement of components on CC and the electrical equivalent circuit are shown in Figure 6. Please note, the last two components on CC (CSBWEN & RFA) are user defined and, as such, are not placed on the component carrier when shipped from the factory. They are shown here to facilitate their identification to the user when being placed on the board. Figure 6 CD [C] RD [R8] RDC [R4] CDC [C] RDC [R5] CSBWEN RFA [R9] RSN RDC RDC CDC RDC CC CC Component Carrier DC Feed Control Circuit.8 LED Indicators LED indicators are provided to monitor the various SLIC outputs. LED On Off RINGOUT Low RINGOUT High DET Low DET High BSWOUT Low. Feeding from BAT BSWOUT High. Feeding from BAT. 4 Testout Low Testout High Each LED indicator resides in parallel with, and is isolated from, the main signal by feeding the signal through a 00K resistor to the base of an LED drive transistor. Because the transistor requires only a few micro amps to activate or deactivate the LED, it does not present any loading effect..9 DA, DB, and RINGOUT Banana Jacks External DA and DB input signals can be applied to the SLIC via the DA and DB banana jacks when the top two switches of S are set to the switched position. The banana jacks are incorporated to allow the user to connect to off-board custom-built ringing circuitry. Please be aware that if the RINGOUT signal is switched to this banana jack, the user can no longer control the on-board relay K. The Ring Source input from the PW connector can be used to supply an off-board ring signal to relay K. The ring signal is applied to the unbalanced ring circuit composed of resistors R, R, SLIC Evaluation Board User s Guide 9

12 R, R4, R5 and capacitors C4 and C5, which is used to set the on-board DA and DB inputs of the SLIC device..0 Breadboard Area In order to evaluate the performance of the SLIC device when the application also requires additional circuitry, such as provision for metering (teletax) pulses, a two-square-inch breadboard area and a BNC connector are provided on the evaluation board. The user can use this breadboard area to add whatever external circuitry is desired. For metering applications, the associated BNC connector can be used to directly inject the or 6 khz teletax pulse signal. The connection can then be closed by shorting across J5, optionally using the breadboard area for any desired control or filtering operation. As an example of metering, if V MG is the voltage sent into the BNC connector and V LM is the metering voltage required across the subscriber line loaded with Z LM, the equation describing the signal levels is: VLM ZLM Zr(f) = VMG ZLM + ZSLIC(f) + RF RM The value of R M would depend on the metering signal requirement into the subscriber line, the output voltage of the metering signal source, and the value of the impedance connected across V and R (Z ). TX SN T In the previous equation, (f) denotes the frequency of the metering signal and Z SLIC is Z T /000. V LM and Z LM are specified by the PTT or a similar government agency. Z T is chosen based on the twowire input impedance requirement and R F is the fuse resistor. Hence, R M is directly related to V MG. A suitable notch or low-pass filter to prevent the metering pulses from entering the SLAC can also be installed in the breadboard area. 4.0 SOFTWARE OPERATION The Zarlink SLIC evaluation boards operate either standalone or in conjunction with an Zarlink SLAC device evaluation board. The SLIC devices by themselves do not require any software for operation. However, when connected to Zarlink s SLAC devices, software control is available. Two software families, the WinSLAC software and xslacifp software, are provided for design and evaluation. 4. WinSLAC Software The WinSLAC program is a software tool that aids in the design and development of telephone linecards and related voice band applications. It enables the user to design and generate coefficients for the programmable filters of the Zarlink SLAC family of devices, and provides the user with predicted performance of system parameters. The program models the SLAC device, the line conditions, and associated linecard SLIC components. It calculates an optimum set of filter coefficients based on the overall system design conditions, and generates the corresponding system responses for each of the programmable functions. It also calculates and plots predicted system responses for Two-Wire Return Loss (WRL), Four-Wire Return Loss (4WRL), and Receive and Transmit frequency responses. The WinSLAC program uses gain-phase parameters (G-Parameters) to describe the SLIC circuitry for input to the program. The G-Parameter arrays are typically produced by the program through Spice simulation of the SLIC circuitry. They may also be entered manually, using data obtained by lab measurements on a real SLIC circuit. In order to generate the G-parameters, the WinSLAC program incorporates and uses an evaluation version of MicroSim Corporation's PSpice and Schematics programs to simulate the analog circuitry of the SLIC. Although the evaluation versions of these programs are sufficient for most designs, their limitations may impose certain restrictions on more complex designs. In such SLIC Evaluation Board User s Guide 0

13 cases, the full production version of these programs may be purchased directly from MicroSim Corporation and easily integrated into the WinSLAC program operation. The WinSLAC software is not required to operate the SLIC evaluation board, but becomes a necessary tool whenever the SLIC board is used in conjunction with an Zarlink SLAC device in a full evaluation setup. 4. SLACIFP Software The SLACIFP (DSLACIFP, QSLACIFP) software is used to communicate from a user s computer to the SLAC device through the Computer Interface (ACIF) board. It is not necessary for standalone operation of the SLIC board, but like the WinSLAC software, becomes a necessary tool whenever the SLIC board is used in conjunction with an Zarlink SLAC device in a full evaluation setup. 4. SLIC Circuit Simulation Models As explained previously, the WinSLAC software uses gain-phase parameters (G-Parameters) to describe the SLIC circuitry for input to the program. In order to generate the G-parameters, the WinSLAC program incorporates and uses an evaluation version of MicroSim Corporation's PSpice and Schematics programs to simulate the analog circuitry of the SLIC. In order to support this analysis, a simulation model of the SLIC device must be available. The WinSLAC software includes simulation models for each of the Zarlink SLIC devices. These are very simplified models, intended to produce transmission performance characteristics under limited DC feed conditions. These models are accurate for their intended purpose of transmission band performance representation, but are not intended to accurately represent all SLIC operations. The text listing of the SLIC model is shown in the next section. SLIC Evaluation Board User s Guide

14 4.4 SLIC Device Simulation Model * MODEL FOR LE7949 0//96 *********************************************************************** * This model is intended for use with LeSLAC to model AC performance * and does not fully model all aspects of DC performance. ***********************************************************************.SUBCKT LE *DC PATH EDC R 6 0K VAS 7 0 DC 0 AC 0 HDC 5 0 VAS 0K IAPP 0 7.5M Q NPN Q 7 9 NPN IASB U EAS 9 0 POLY() RB 6 0 K VFSENSE 0 0 F 0 VFSENSE 05. R 6 RNOFLT 0 00MEG C N *AC PATH ETX R 46K R 4 4 C N D 0 DIODE D 6 DIODE.MODEL NPN NPN IS=E-4.MODEL DIODE D IS=E-4.ENDS LE7949 SLIC Evaluation Board User s Guide

15 4.5 Example Schematic Circuit Figure 7 The SLIC device must be included in a top-level analog circuit that represents the entire analog front end of the linecard design. This circuit must include all circuit elements between tip/ring and the analog input/output connections of the connected SLAC device. A basic circuit is included with the WinSLAC software, and the MicroSim Schematics program allows editing of this circuit for updating user-selected component values or adding optional circuitry. The default circuit provided with the program is shown in Figure 7. X8 See Note See Note RF AXBX VTX 4 AXBX 00 CX.n RLDC RLDC See Note 5 CHP RSN CHP.u RDC 5 VBAT 0 6 RDC RDC 5.9K CDC See Note CP 5.9K.47u p RP e-6 RTX RT ROUT e K ROUT CTX 50p K RRX 0K CVTX 0.u e9 RIN 0 CVRX 0.u See Note VTX e6 See Note 4 0 VRX D N400 0 VBAT - 5V + 0 Notes:. Do NOT change the names of the offpage connectors (TIP, RING, VTX, and VRX). Doing so will interfere with the creation of G-parameters.. The default values may or may not be the proper values for a given SLIC. Refer to Note in the datasheet for default values.. Because this model combines the TIP and RING into pin, RF should be twice the value of your fuse resistance and CX should be half. 4. RIN is internal to the QSLAC device. 5. RLDC establishes the DC operating point of the SLIC. This resistor has no effect on transmission performance and therefore we recommend it not be changed. The spice circuit shown in Figure 7 has the default values [as shipped from the factory] for the impedance matching circuit and the loop current circuit for the SLIC device. The loop current components [RDC, RDC, and CDC] are chosen to provide a loop current of approximately 5 ma. SLIC Evaluation Board User s Guide

16 5.0 REPRESENTATIVE TRANSMISSION PERFORMANCE Some typical transmission performance measurements have been taken with the SLIC connected to the Zarlink Le79Q0 QSLAC device. The conditions for these measurements are: QSLAC Device Rev D SLIC device Rev BD0 SLIC model date 0/0/98 BAT -56 V BAT -4 V OVH HIGH SLIC State ACTIVE BSWTH BAT RLOAD 600 Ω The measured results will be approximately: VAB(SLIC) IAB 5.5 V 5. ma The default (as shipped) evaluation board component values for the circuit were used. These values are: Component Value RRX 0K RT 64.9K RT 64.9K CT RF 50 pf RDC 5.9K RDC 5.9K CDC 00 Ω [50 Ω each] 470 nf Three typical line conditions were used for these measurements. These are common values and one or more of these impedance s is typically available in most telecom test instrumentation, making it relatively easy to directly hook up to the evaluation board as a setup verification exercise. These impedance conditions are: 600 Ω line 900 Ω line German complex impedance line For each of these three conditions, graphs of two-wire return loss, four-wire return loss, and receive and transmit path attenuation distortion are provided. These can be compared to actual lab measurements during verification testing. SLIC Evaluation Board User s Guide 4

17 Ω Line (Default) All programmable filters of the QSLAC device, except the Balance Filter, were disabled for this condition. The QSLAC device has the capability of altering the programmed two-wire impedance, frequency response, and path gains. By disabling these functions, the performance measurements represent pure SLIC-only operation. The balance filter was left enabled because it performs the hybrid balance function of the complete solution, and without this, four-wire return loss measurements are meaningless. The TWRL trace was generated with a short loop (BAT active) and a longer loop (VAB = 0 V) when BAT was active. When using the WinSLAC coefficient calculation program, the following table shows, by main menu items and sub-menu items, what the required filter settings should be for the generation of coefficients. Main Menu Item Sub-menu Set System: Desired Impedance: ZD = to 600 Line Impedance: ZL = to 600 SLAC: AISN & Z Filter: AISN to disabled SLAC: R & X Filters/Gain Blocks: X & R to Ziir & Zfir to disabled GX & GR to 0.0 AX & AR to 0.0 SLAC: B Filter & Adaptive Balance: B to calculate SLIC Evaluation Board User s Guide 5

18 Figure Ω Line Two-Wire Return Loss Performance Two Wire Return Loss Figure Ω Line Four-Wire Return Loss Performance Four Wire Return Loss SLIC Evaluation Board User s Guide 6

19 Figure Ω Line Receive Path Attenuation Distortion Performance Receive Attenuation Distortion Figure 600 Ω Line Transmit Path Attenuation Distortion Performance Transmit Attenuation Distortion SLIC Evaluation Board User s Guide 7

20 Ω Line All programmable filter blocks of the QSLAC device were enabled, except AX and AR, which were set to 0 db gain each. The two-wire and balance impedances were specified as 900 Ω, and the WinSLAC program computed programmed coefficients to meet this line condition. When using the WinSLAC coefficient calculation program, the following table shows, by main menu items and sub-menu items, what the required filter settings should be for the generation of coefficients. Main Menu Item Sub-menu Set System: Desired Impedance: ZD = to 900 Line Impedance: ZL = to 900 SLAC AISN & Z Filter: AISN to calculate Ziir & Zfir to calculate SLAC R & X Filters/Gain Blocks: X & R to calculate GX & GR to calculate AX & AR to 0.0 SLAC B Filter & Adaptive Balance: B to calculate SLIC Evaluation Board User s Guide 8

21 Figure 900 Ω Line Two-Wire Return Loss Performance Two Wire Return Loss Figure 900 Ω Line Four-Wire Return Loss Performance Four Wire Return Loss SLIC Evaluation Board User s Guide 9

22 Figure Ω Line Receive Path Attenuation Distortion Performance Receive Attenuation Distortion Figure Ω Line Transmit Path Attenuation Distortion Performance Transmit Attenuation Distortion SLIC Evaluation Board User s Guide 0

23 5. German Line All programmable filter blocks of the QSLAC device were enabled, except AX and AR, which were set to 0 db gain each. The two-wire and balance impedances were specified as the German complex impedance (0 Ω in series with a parallel RC network of 80 Ω and 5 nf) and the WinSLAC program computed programmed coefficients to meet this line condition. When using the WinSLAC coefficient calculation program, the following table shows, by main menu items and sub-menu items, what the required filter settings should be for the generation of coefficients. Main Menu Item Sub-menu Set System: Desired Impedance: ZD = to complex impedance shown below Line Impedance: SLAC AISN & Z Filter: AISN to calculate ZL = to complex impedance shown below Ziir & Zfir to calculate SLAC R & X Filters/Gain Blocks: X & R to calculate GX & GR to calculate AX & AR to 0.0 SLAC B Filter & Adaptive Balance: B to calculate For the complex impedances, the values were entered in S-polynomial format. The formula used is: Ζ= 040+(.0746E - )s +(9.4E -5 )s The representative circuit is: 80 Ω 0 Ω 5 nf SLIC Evaluation Board User s Guide

24 Figure 6 German Complex Line Two-Wire Return Loss Performance Two Wire Return Loss Figure 7 German Complex Line Four-Wire Return Loss Performance Four Wire Return Loss SLIC Evaluation Board User s Guide

25 Figure 8 German Complex Line Receive Path Attenuation Distortion Performance Receive Attenuation Distortion Figure 9 German Complex Line Transmit Path Attenuation Distortion Performance Transmit Attenuation Distortion SLIC Evaluation Board User s Guide

26 6.0 LE79489 EVALUATION BOARD STANDALONE OPERATIONAL TEST 6. Board Operation This section explains a simple setup to verify proper functionality of the SLIC Evaluation Board. This procedure uses the default values (refer to the schematic) when the board is shipped. If any modifications have been made to the board, output voltage reading may vary from those described in this document. Equipment needed for this test is:. A dual channel oscilloscope.. A function generator.. Power supplies: +5, -5, and V BAT supplies. Check that all supplies are turned off while making power supply connections. Please note that all ground connections must terminate at one of the power supplies.. Connect AUX_VCC and V CC to +5 Vdc.. Connect V EE to 5 Vdc.. Connect V BAT and V BAT to the supplies (set V BAT to 48 V and V BAT to 4 V). 4. Connect the ground/common inputs of all supplies and the evaluation board ( and ) together. Remember to keep all grounds terminated at one of the power supplies. 5. Set all three switches on S to Normal. 6. Move all jumpers on JR to the Internal or standalone mode and set the switches on S and S to (Table shows all SLIC decoding states): C = 0 C = C = 0 E = 7. Connect a standard telephone handset to SK (or a loop-holding circuit terminated at 600 Ω between the A (Tip) and B (Ring) banana jacks). 8. Connect a signal generator to the Receive (V RX ) input and one channel of the oscilloscope. Set the output of the generator to a V p/p sine khz. 9. Connect the second channel of the oscilloscope to the V TX output. 0. Check all connections and turn on the power supplies. After step 0, there will be. V p/p sine wave riding on a 5.5 Vdc signal between TIP and RING of the telephone. The same. V p/p signal (minus the dc voltage) will be at the Transmit (V TX ) output. If a standard telephone station set is connected to SK on the board, an audible tone can be heard when the receiver is lifted. A 80 phase shift will occur between V TX and V RX. Note: Not all telephones have the same DC resistance; therefore, the voltage difference between TIP and RING will vary slightly from the above value. 6. LED Indicator Four LEDs on the evaluation board indicate the status of RINGOUT, DET, TESTOUT, and BSWOUT. SLIC Evaluation Board User s Guide 4

27 Table SLIC Decoding States LED On Off RINGOUT Active RINGOUT high DET Active (handset off-hook) DET Inactive (handset on-hook) BSWOUT Active BSWOUT Inactive 4 TESTOUT Active (low) TESTOUT Inactive (high) With switch on S positioned to the left (Normal), an audible click will be heard as the relay activates when the switch is flipped to the right. Indicates VBAT connected to VBAT. Indicates VBAT not connected to VBAT. 6. Test Setup to Verify Ringing The ringing on the PLCC Evaluation Board is based on an unbalanced ringing source. The ringing voltage can be supplied via the RING SOURCE cable on PW. To use the ringing circuit:. Place the S switches in the Normal position.. Connect the RING SOURCE cable to the ring voltage.. Set the S and S switches as follows (JR jumpered to the left sets the board in the standalone mode): C = to activate the ring relay C = 0 C = 0 As C is set to, an audible click will be heard indicating the relay is activated. If an on-hook station set is connected across the TIP and RING leads (or through connector SK, the RJ-- type phone connector), the phone will ring. To deactivate the ringing set, switch C to 0. Setting C to will return the station set to normal active. Table SLIC Decoding State State C C C -Wire Status DET Output E = E = Standby, Reverse Polarity Loop Detect GK 0 0 Reserved 0 0 Active, Reverse Polarity Loop Detect or GK GK 0 Tip Open * GK GK Disconnect Ring Trip Ring Trip 5 0 Ringing Ring Trip Ring Trip 6 0 Active, Normal Loop Detect GK 7 Standby, Normal Loop Detect GK Note: * In the Tip Open state, the ground key detector is active irrespective of E. SLIC Evaluation Board User s Guide 5

28 7.0 EVALUATION BOARD SCHEMATIC See the attached page. SLIC Evaluation Board User s Guide 6

29 A B C D RING SOURCE DA DB RINGOUT TESTOUT BAT BAT DET* C 0uF C 0uF AUX_VCC Q N906 AUX_VCC Q N906 BJ5 GREEN C4 nf + + LED RINGOUT ACTIVE STATUS: LED ON = RINGOUT ACTIVE LED OFF = RINGOUT INACTIVE BJ RED BLACK RED BLACK R7 90 Ohm R9 90 Ohm LED BJ BJ BJ4 C0 0.47uF VBAT VBAT JR DEFAULT POSITION OF JR IS BSWTH JUMPERED TO VBAT. TESTOUT ACTIVE STATUS: LED ON = TESTOUT ACTIVE LED OFF = TESTOUT INACTIVE BSWOUT ACTIVE STATUS: ON = VBAT CONNECTED TO VBAT OFF = VBAT DISCONNECTED FROM VBAT DET* ACTIVE STATUS: LED ON = DET* ACTIVE (LOW) LED OFF = DET* INACTIVE R0.K D N400 C 0.47uF R8 00K Ohm R0 00K Ohm R 49K R4 05K D N400 R 400 Ohm W C5 nf R 05K R5 49K BSWTH RTMG /W 560 5% AUX_VCC Q4 N906 AUX_VCC R 90 Ohm LED4 SWITCH SETTINGS FOR S: LEFT; SIGNALS ROUTED TO RELAY & RINGING NETWORK. RIGHT; SIGNALS ROUTED TO BANANA JACKS CVBAT 0nF R4 S 00K AUX_VCC Q N K TESTOUT LED R 00K K K NC NO NC NO NC NO C NO NO 9 C 7 C NC C NC CVBAT 0nF R 90 Ohm C TMG FRP 50 OHM NETWORK AUX_VCC BSWOUT RINGOUT DB DET* CBX 00pF DA CAS R6.K 5 S 0 NC NO B S 0 NC NO NC NO NC NO NC NO NC NO 0 CAS 0nF Sx HPA CHP 0nF HPB CBSWEN C C SEE NOTE 9 C 7 C 9 C 7 C C C C OVH E BSWEN DEFAULT POSITION IS TOGGLE SWITCH SET TO LEFT OR "NORMAL" FOR SWITCHES S THROUGH S C-COMMON, NC-NORMALLY CLOSED, NO-NORMALLY OPEN USE SWITCH S & S TO CHANGE SLIC CONTROL LINES HIGH = ; LOW = 0. 4 A CAX 00pF U A(TIP) HPA HPB B(RING) DA DB 4 RINGOUT 5 TESTOUT 6 BSWOUT 6 BSWTH 8 VBAT VBAT 7 TMG DET 7 CAS JR4 U ~ - 4 ~ + DIODE BRIDGE BSWEN 0 E OVH 8 C C C 4 5 VCC A/DGND RSVD RD N/C VTX RSN RDC RFA C JR- JR- JR- JR-4 JR-5 U P0640EA70 VCC C C E P 5 C OVH C C C 5 C6 0.uF BSWEN SK CD, RD, AND R9 [RFA] RESIDE ON CC R9 SEE NOTE A\DGND BJ6 RED BJ7 GREEN BJ8 BLACK A TIP B RING JR0 NOTE: JUMPER JR0 PIN TO TO TURN THE TEST RELAY OFF. JUMPER JR0 PIN TO TO TURN TEST RELAY ON. 6 RD CD 6.5K 0nF RD RSN RDC BSWEN RFA RDC R4 5.90K R5 5.90K RDC C CDC 470nF COMPONENTS LOCATED ON CC. CC CD RD VCC RDC CDC RDC 7 CBSWEN 0 8 R9 9 6-PIN CC COMPONENT PLACEMENT FOR CC. NOTE(S):. VALUE OF R9 [RFA] DETERMINED BY USER.. VALUE OF CBSWEN DETERMINED BY USER C8 0uF 7 R 64.9K RTX CTX C6 50pF R 64.9K RTX 0K RRX COMPONENTS LOCATED ON CC. RSN Legerity, Inc Freidrich Lane Austin, Texas Title 4 JUMPER RRX RTX RTX CTX 0 9 COMPONENT PLACEMENT NETWORK FOR CC. SLIC Evaluation Board VTX TRANSMIT BNC# VRX RECEIVE Size Document Number Rev C E Date: R :7:5 BAT BAT RING SOURCE AUX_VCC AUX_VCC VTX VEE JR5 CC VCC VEE D4 N400 VRX 6-PIN CC D N VTX BNC# BNC# PW BREADBOARD AREA BREADBOARD AREA BREADBOARD AREA VTX VRX Sheet of 8 A B C D