DP1276 C169/C433/C868/C915

Transcription

1 C169/C433/C868/C915 Low Power Long Range Transceiver Module Combine Small Form Factor with High Performance Variants for 169 MHz, 433 MHz, 868 MHz and 915 MHz GENERAL DESCRIPTION The includes the LoRa long range modem that provides ultralong range spread spectrum communication and high interference immunity whilst minimizing current consumption. Using Semtech s patented LoRa modulation technique can achieve sensitivity of over 148. The high sensitivity combined with the integrated +20 power amplifier yields industry leading link budget making it optimal for any application requiring range or robustness. LoRa also provides significant advantages in blocking and selectivity over conventional modulation techniques. Solving the design compromise between range, interference immunity and energy consumption. These devices also support high performance (G)FSK modes for Wireless MBus, IEEE g and similar compatibility modes. The deliver exceptional phase noise, selectivity, receiver linearity and IIP3 for significantly lower current consumption than competing devices. APPLICATIONS Wireless alarm and security systems Wireless sensor networks Automated Meter Reading Home and building automation Industrial monitoring and control Long range Irrigation Systems KEY PRODUCT FEATURES LoRa TM Modem 168 maximum link budget mw constant RF output vs. V supply Programmable bit rate up to 300 kbps High sensitivity: down to 148 Bulletproof front end: IIP3 = 12.5 Excellent blocking immunity Low RX current of 10.3 ma, 200 na register retention Fully integrated synthesizer with a resolution of 61 Hz FSK, GFSK, MSK, GMSK, LoRa TM and OOK modulation Builtin bit synchronizer for clock recovery Preamble detection 127 Dynamic Range RSSI Automatic RF Sense and CAD with ultrafast AFC Packet engine up to 256 bytes with CRC Builtin temperature sensor and low battery indicator DEVICE OPTIONS Part Frequency Pin band Package C MHz Board C MHz Board C MHz Board Version

2 Table of Contents 1. PIN DESCRIPTION ELECTRICAL CHARACTERISTICS ABSOLUT MAXIMUM RATINGS OPERATING RANGE SPECIFICATIONS POWER CONSUMPTION SPECIFICATION FREQUENCY SYNTHESIZER SPECIFICATION FSK/OOK MODE RECEIVER SPECIFICATION FSK/OOK MODE TRANSMITTER SPECIFICATION ELECTRICAL SPECIFICATION FOR LoRa MODULATION DIGITAL SPECIFICATION FEATURES LoRa MODEM FSK/OOK MODEM RF POWER AMPLIFIERS HIGH POWER +20 OPERATION RF_MOD/VDD PIN FUNKTION DESKRIPTION SPI INTERFACE INTRODUCTION TO THE LoRa MODEM AND ITS CAPABILITIES LINK DESIGN USING THE LoRa MODEM OVERVIEW SPREADING FACTOR CODING RATE SIGNAL BANDWIDTH LoRa TM TRANSMISSION PARAMETER RELATIONSHIP LoRa PACKET STRUCTURE PREAMBLE HEADER EXPLICIT HEADER MODE IMPLICIT HEADER MODE PAYLOAD TIME ON AIR FREQUENCY HOPPING WITH LoRa PRINCIPLE OF OPERATION TIMING OF CHANNEL UPDATES Anylink

3 8. FSK/OOK MODEM BIT RATE SETTING OPERATING MODES IN FSK/OOK MODE GENERAL OVERVIEW STARTUP TIMES TRANSMITTER STARTUP TIME RECEIVER STARTUP TIME TIME TO RSSI EVALUATION TX TO RX TURNAROUND TIME RX TO TX RECEIVER HOPPING; RX TO RX TX TO TX RECEIVER STARTUP OPTIONS RECEIVER RESTART METHODS RESTART UPON USER REQUEST AUTOMATIC RESTART AFTER VALID PACKET RECEPTION AUTOMATIC RESTART WHEN PACKET COLLISION IS DETECTED TOP LEVEL SEQUENCER SEQUENCER STATES SEQUENCER TRANSITIONS TIMERS SEQUENCER STATE MACHINE PACKET FORMAT FIXED LENGTH PACKET FORMAT VARIABLE LENGTH PACKET FORMAT UNLIMITED LENGTH PACKET FORMAT MECHANICAL DIMENSIONS Anylink

4 1. PIN DESCRIPTION Top View PIN NAME I/O DESCRIPTION 1 GND Ground. 2 RFIO IN/OUT RF input / output 3 GND Ground. 4 VDD Supply voltage. 5 GND Ground. 6 RESET IN Reset trigger input. 7 DIO0 IN/OUT Digital I/O, software configured. 8 DIO1/DCLK IN/OUT Digital I/O, software configured. 9 DIO2/DATA IN/OUT Digital I/O, software configured. 10 DIO3 IN/OUT Digital I/O, software configured. 11 DIO4 IN/OUT Digital I/O, software configured. 12 DIO5 IN/OUT Digital I/O, software configured. 13 SCK IN SPI Clock input. 14 MISO Out SPI Data output. 15 MOSI IN SPI Data input. 16 NSS IN SPI Chip select input. 17 SWXOVDD IN C169 VDD for TCXO and Switch depower in Sleep mode / C433, C868, C915 VDD RFSwitch depower in Sleep mode. Table 1 Anylink

5 2. ELECTRICAL CHARACTERISTICS 2.1. ABSOLUT MAXIMUM RATINGS Description Min Max Unit Supply voltage V Operating temperature C RF Input Level +10 Load capacitance on digital ports 25 pf Table OPERATING RANGE Description Min Max Unit Supply voltage V Operating temperature C Load capacitance on digital ports 25 pf RF Input Level +10 Soldering temperature (max 15 sec) 260 C Table 3 CAUTION: ESD sensitive device. Precaution should be taken when handling the device in order to prevent permanent damage Life Support Policy and Use in Safety Critical Applications ANYLINK PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF ANYLINK PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER S OWN RISK. Anylink

6 3. SPECIFICATIONS The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VDD=3.3 V, temperature = 25 C, FXOSC = 32 MHz, FRF = 169/434 MHz (see specific indication), Pout = +13, 2 level FSK modulation without prefiltering, FDA = 5 khz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. Shared Rx and Tx path matching. Note: Specification corresponds to the performance in Band 1, Band 2 and Band 3, as described in section POWER CONSUMPTION SPECIFICATION Symbol Description Conditions Min Typ Max Unit IDDSL Supply current in Sleep mode µa IDDIDLE Supply current in Idle mode RC oscillator enabled 1.5 µa IDDST Supply current in Standby mode Crystal oscillator enabled ma IDDFS Supply current in Synthesizer mode FSRx 5.8 ma IDDR IDDT Supply current in Receive mode Supply current in Transmit mode with impedance matching LnaBoost Off, Bands1&2 LnaBoost On, Bands1&2 RFOP = +20, on PA_BOOST RFOP = +17, on PA_BOOST Table ma ma ma 3.2. FREQUENCY SYNTHESIZER SPECIFICATION Symbol Description Conditions Min Typ Max Unit FR Synthesizer frequency range Programmable Band 1 Band 2 Band 3 FXOSC Crystal oscillator frequency 32 MHz TS_OSC Crystal oscillator wakeup time 250 µs TS_FS Frequency synthesizer wakeup time to PllLock signal From Standby mode 60 µs TS_HOP Frequency synthesizer hop time at most 10 khz away from the target frequency 200 khz step 1 MHz step 5 MHz step 7 MHz step 12 MHz step 20 MHz step 25 MHz step µs µs µs µs µs µs µs FSTEP Frequency synthesizer step 61.0 Hz FRC RC Oscillator frequency 62.5 khz BRF Bit rate, FSK Programmable values (1) kbps BRA Bit Rate Accuracy ABS(wanted BR available BR) 250 ppm BRO Bit rate, OOK Programmable kbps BR_L Bit rate, LoRa TM Mode From SF6, BW=500kHz to SF12, BW=7.8kHz kbps FDA Frequency deviation, FSK (1) Programmable FDA + BRF/2 =< 250 khz khz Table 5 Note: For Maximum Bit rate the maximum modulation index is MHz Anylink

7 3.3. FSK/OOK MODE RECEIVER SPECIFICATION All receiver tests are performed with RxBw = 10 khz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence. Sensitivities are reported for a 0.1% BER (with Bit Synchronizer enabled), unless otherwise specified. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 above the receiver sensitivity level. Symbol Description Conditions Min Typ Max Unit RFS_F_LF RFS_F_HF Direct tie of RFI and RFO pins, shared Rx, Tx paths FSK sensitivity, highest LNA gain. Bands 1&2 Split RF paths, LnaBoost is turned on, the RF switch insertion loss is not accounted for. Bands 1&2 Direct tie of RFI and RFO pins, shared Rx, Tx paths FSK sensitivity, highest LNA gain. Band 3 /868/915 Split RF paths, LnaBoost is turned on, the RF switch insertion loss is not accounted for. Band 3 /868/915 FDA = 5 khz, BR = 1.2 kb/s FDA = 5 khz, BR = 4.8 kb/s FDA = 40 khz, BR = 38.4 kb/s* FDA = 20 khz, BR = 38.4 kb/s** FDA = 62.5 khz, BR = 250 kb/s*** FDA = 5 khz, BR = 1.2 kb/s FDA = 5 khz, BR = 4.8 kb/s FDA = 40 khz, BR = 38.4 kb/s* FDA = 20 khz, BR = 38.4 kb/s** FDA = 62.5 khz, BR = 250 kb/s*** FDA = 5 khz, BR = 1.2 kb/s FDA = 5 khz, BR = 4.8 kb/s FDA = 40 khz, BR = 38.4 kb/s* FDA = 20 khz, BR = 38.4 kb/s** FDA = 62.5 khz, BR = 250 kb/s*** FDA = 5 khz, BR = 1.2 kb/s FDA = 5 khz, BR = 4.8 kb/s FDA = 40 khz, BR = 38.4 kb/s* FDA = 20 khz, BR = 38.4 kb/s** FDA = 62.5 khz, BR = 250 kb/s*** BR = 4.8 kb/s BR = 32 kb/s RFS_O OOK sensitivity, highest LNA gain shared Rx, Tx paths CCR CoChannel Rejection 9 ACR Adjacent Channel Rejection BI_LF Blocking Immunity Bands 1&2 /169/433 BI_HF Blocking Immunity Band 3 /868/915 AMR IIP2 AM Rejection, AM modulated interfere with 100% modulation depth, fm = 1 khz, square 2nd order Input Intercept Point Unwanted tones are 20 MHz above the LO FDA = 5 khz, BR = 4.8kb/s Offset = +/ 25 khz or Offset = +/ 50 khz Band 1 Band 2 Offset = +/ 1 MHz Offset = +/ 2 MHz Offset = +/ 10 MHz Offset = +/ 1 MHz Offset = +/ 2 MHz Offset = +/ 10 MHz Offset = +/ 1 MHz Offset = +/ 2 MHz Offset = +/ 10 MHz Highest LNA gain +55 IIP3_LF 3rd order Input Intercept point Unwanted tones are 1MHz and MHz above the LO Band 1 Highest LNA gain G1 LNA gain G2, 2.5 sensitivity hit Band 2 Highest LNA gain G1 LNA gain G2, 2.5 sensitivity hit Anylink

8 Symbol Description Conditions Min Typ Max Unit IIP3_HF 3rd order Input Intercept point Unwanted tones are 1MHz and MHz above the LO Band 3 Highest LNA gain G1 LNA gain G2, 5 sensitivity hit BW_SSB Single Side channel filter BW Programmable khz IMR Image Rejection Wanted signal 3 over sens BER=0.1% 50 IMA Image Attenuation 57 DR_RSSI RSSI Dynamic Range AGC enabled * RxBw = 83 khz (Single Side Bandwidth) ** RxBw = 50 khz (Single Side Bandwidth) *** RxBw = 250 khz (Single Side Bandwidth) 3.4. FSK/OOK MODE TRANSMITTER SPECIFICATION Table 6 Symbol Description Conditions Min Typ Max Unit RF_OP ΔRF_ OP_V RF_OPH RF_OPH _MAX ΔRF_ OPH_V ΔRF_T PHN ACP TS_TR RF output power in 50 ohms on RFO pin (High efficiency PA). RF output power stability on RFO pin versus voltage supply. RF output power in 50 ohms, on PA_BOOST pin (Regulated PA). Max RF output power, on PA_BOOST pin RF output power stability on PA_BOOST pin versus voltage supply. RF output power stability versus temperature on both RF pins. Transmitter Phase Noise Transmitter adjacent channel power (measured at 25 khz offset) Transmitter wake up time, to the first rising edge of DCLK Programmable with steps Max Min VDD = 2.5 V to 3.3 V VDD = 1.8 V to 3.7 V Programmable with 1 steps Max Min High power mode +20 VDD = 2.4 V to 3.7 V +/1 From T = 40 C to +85 C +/1 169 MHz, Band 1 10kHz Offset 50kHz Offset 400kHz Offset 1MHz Offset 433 MHz, Band 2 10kHz Offset 50kHz Offset 400kHz Offset 1MHz Offset 868/915 MHz, Band 3 10kHz Offset 50kHz Offset 400kHz Offset 1MHz Offset BT=1. Measurement conditions as defined by EN V2.3.1 Frequency Synthesizer enabled, PaRamp = 10us, BR = 4.8 kb/s Table c/ Hz c/ Hz c/ Hz µs Anylink

9 3.5. ELECTRICAL SPECIFICATION FOR LoRa MODULATION The table below gives the electrical specifications for the transceiver operating with LoRa modulation. Following conditions apply unless otherwise specified: Supply voltage = 3.3 V. Temperature = 25 C. fxosc = 32 MHz. Bandwidth (BW) = 125 khz. Spreading Factor (SF) = 12. Error Correction Code (EC) = 4/6. Packet Error Rate (PER)= 1%. CRC on payload enabled. Output power = 13 in transmission. Payload length = 64bytes Preamble Length = 12 symbols (programmed register PreambleLength = 8) With matched impedances. Electrical specifications: LoRa mode Symbol Description Conditions Min Typ Max Unit BW = 7.8 khz to 62.5 khz 11.0 ma Supply current in receiver LoRa mode, BW = 125 khz 11.5 ma LnaBoost Off, Band1&2/169/433 BW = 250 khz 12.4 ma BW = 500 khz 13.8 ma IDDR_L IDDT_H_L BI_L IIP2_L IIP3_L_LF IIP3_L_HF BR_L RFS_L7.8_LF RFS_L10_LF RFS_L62_LF Supply current in receiver LoRa mode, LnaBoost Off, Band3/868/915 Supply current in transmitter mode with an external impedance transformation Blocking immunity, CW interferer 2nd order input intercept point Unwanted tones are 20 MHz above the LO 3rd order input intercept point Unwanted tones are 1MHz and 1.995MHz above the LO 3rd order Input Intercept point Unwanted tones are 1MHz and MHz above the LO Bit rate, LongRange Mode RF sensitivity, LongRange Mode, highest LNA gain, Band 2 or 3, using split Rx/Tx path 7.8 khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, Band 3, 10.4 khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, Band 3, 62.5 khz bandwidth BW = 7.8 khz to 62.5 khz BW = 125 khz BW = 250 khz BW = 500 khz Using PA_BOOST pin RFOP = 17 offset = +/ 1 MHz offset = +/ 2 MHz offset = +/ 10 MHz Anylink ma ma ma ma 90 ma Highest LNA gain +55 Band 1&2 Highest LNA gain G1 LNA gain G2,2.5 sensitivity hit Band 3 Highest LNA gain G1 LNA gain G2,2.5 sensitivity hit From SF6, CR = 4/5, BW = 500 khz to SF12, CR = 4/8, BW = 125 khz SF = 12 SF = 11 SF = 6 SF = 7 SF = 8 SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = kbps

10 Symbol Description Conditions Min Typ Max Unit SF = 6 SF = RFS_L125_LF SF = RF sensitivity, LongRange Mode, highest SF = LNA gain, Band 3, 125 khz bandwidth SF = SF = 11 SF = RFS_L250_LF BR_L500_LF RFS_L10_HF RFS_L62_HF RFS_L125_HF RFS_L250_HF RFS_L500_HF CCR_LL RF sensitivity, LongRange Mode, highest LNA gain, Band khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, Band khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, LnaBoost for Band 1, using split Rx/Tx path 10.4 khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, LnaBoost for Band 1, using split Rx/Tx path 62.5 khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, LnaBoost for Band 1, using split Rx/Tx path 125 khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, LnaBoost for Band 1, using split Rx/Tx path 250 khz bandwidth RF sensitivity, LongRange Mode, highest LNA gain, LnaBoost for Band 1, using split Rx/Tx path 500 khz bandwidth Cochannel rejection SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = 12 SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = 12 SF = 6 SF = 7 SF = 8 SF = 11 SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = 12 SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = 12 SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = 12 SF = 6 SF = 7 SF = 8 SF = 9 SF = 10 SF = 11 SF = 12 Interferer is a LoRa TM signal using same BW and same SF. Pw = Sensitivity Anylink

11 Symbol Description Conditions Min Typ Max Unit ACR_LCW Adjacent channel rejection Interferer is 1.5*BW_L from the wanted signal center frequency 1% PER, Single CW tone = Sens + 3 SF = 7 SF = IMR_LCW Image rejection after calibration 1% PER, Single CW tone = Sens FERR_L Maximum tolerated frequency offset between transmitter and receiver, no sensitivity degradation, SF6 thru 12 Maximum tolerated frequency offset between transmitter and receiver, no sensitivity degradation, SF10 thru 12 All BW, +/25% of BW The tighter limit applies (see below) SF = 12 SF = 11 SF = 10 Table / 25% BW ppm ppm ppm 3.6. DIGITAL SPECIFICATION Conditions: Temp = 25 C, VDD = 3.3 V, FXOSC = 32 MHz, unless otherwise specified. Symbol Description Conditions Min Typ Max Unit VIH Digital input level high 0.8 VDD VIL Digital input level low 0.2 VDD VOH Digital output level high Imax = 1 ma 0.9 VDD VOL Digital output level low Imax = 1 ma 0.1 VDD FSCK SCK frequency 10 MHz tch SCK high time 50 ns tcl SCK low time 50 ns trise SCK rise time 5 ns tfall SCK fall time 5 ns tsetup MOSI setup time From MOSI change to SCK rising edge. 30 ns thold MOSI hold time From SCK rising edge to MOSI change. 20 ns tnsetup NSS setup time From NSS falling edge to SCK rising edge. 30 ns tnhold NSS hold time From SCK falling edge to NSS rising edge, normal mode. 100 ns tnhigh NSS high time between SPI accesses 20 ns T_DATA DATA hold and setup time 250 ns Table 9 4. FEATURES The is equipped with both standard FSK and long range spread spectrum (LoRa ) modems. Depending upon the mode selected either conventional OOK or FSK modulation may be employed or the LoRa spread spectrum modem LoRa MODEM The LoRa modem uses a proprietary spread spectrum modulation technique. This modulation, in contrast to legacy modulation techniques, permits an increase in link budget and increased immunity to inband interference. At the same time the frequency tolerance requirement of the crystal reference oscillator is relaxed allowing a performance increase for a reduction in system cost. Anylink

12 4.2. FSK/OOK MODEM In FSK/OOK mode the can avail of standard modulation techniques including OOK, FSK, GFSK, MSK and GMSK. The is especially suited to narrow band communication thanks the lowif architecture employed and the builtin AFC functionality RF POWER AMPLIFIERS PA1 and PA2 are both connected to pin PA_BOOST. There are two potential configurations of these power Amplifiers, fixed or programmable. In the fixed configuration they can deliver up to +20. In programmable Configuration they can provide from +17 to +2 in 1 programmable steps. PaSelect Mode Power Range Pout Formula 1 PA1 and PA2 combined on pin PA_BOOST +2 to OutputPower 1 PA1+PA2 on PA_BOOST with high output power to OutputPower Table 10 Power Amplifier Mode Selection Truth Table Note: For +20 restrictions on operation please consult the following section. To ensure correct operation at the highest power levels ensure that the current limiter OcpTrim is adjusted to permit delivery of the requisite supply current HIGH POWER +20 OPERATION The has a high power +20 capability on PA_BOOST pin, with the following settings: Register Address Value for High Power Default value PA0 or +17 Description RegPaDac 0x5A 0x87 0x84 High power PA control Table 11 High Power Settings Note: High Power settings must be turned off when using PA0 The Over Current Protection limit should be adapted to the actual power level, in RegOcp Specific Absolute Maximum Ratings and Operating Range restrictions apply to the +20 operation. They are listed in Table 11 and Table 12. Symbol Description Min Max Unit DC_20 Duty Cycle of transmission at +20 output 1 % VSWR_20 Maximum VSWR at antenna port, +20 output 3:1 VDDop_20 Supply voltage, +20 output V Table 12 Operating Range, +20 Operation The duty cycle of transmission at +20 is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the Standard operating range [40;+85 C]. For any other operating condition, contact your Anylink representative RF_MOD/VDD PIN FUNKTION DESKRIPTION The Function of PIN RF_MOD/VDD depends on the Module variant. For C169 it is VDD of TCXO and RFSwitch and can be turned off in sleep mode. For C433, C868 and C915 the Pin is used to power the RFSwitch so in Sleep mode it has to be switched off to achieve the low power consumption of 1 µa. The same applies for C169. Anylink

13 5. SPI INTERFACE The SPI interface gives access to the configuration register via a synchronous fullduplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. Three access modes to the registers are provided: SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The NSS pin goes low at the beginning of the frame and goes high after the data byte. BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally between each data byte. These modes are available for both read and write accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. The figure below shows a typical SPI single access to a register. Figure 1 SPI Timing Diagram (single access) MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high. The first byte is the address byte. It is comprises: A wnr bit, which is 1 for write access and 0 for read access. Then 7 bits of address, MSB first. The second byte is a data byte, either sent on MOSI by the master in case of a write access or received by the master on MISO in case of read access. The data byte is transmitted MSB first. Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without a rising NSS edge and resending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented for each new byte received. The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is therefore a special case of FIFO / BURST mode with only 1 data byte transferred. During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. Anylink

14 6. INTRODUCTION TO THE LoRa MODEM AND ITS CAPABILITIES The LoRa modem uses spread spectrum modulation and forward error correction techniques to increase the range and robustness of radio communication links compared to traditional FSK or OOK based modulation. Examples of the performance improvement possible, for several possible settings, are summarized in the table below. Here the spreading factor and error correction rate are design variables that allow the designer to optimize the tradeoff between occupied bandwidth, data rate, link budget improvement and immunity to interference. Bandwidth (khz) Spreading Factor Coding rate Nominal Rb (bps) Sensitivity () Module valiant / / / / / / / / /433/868/ / / / / /868/915 Table 13 Example LoRa Modem Performances Notes for all bandwidths lower than 62.5 khz, it is advised to use a TCXO as a frequency reference. This is required to meet the frequency error tolerance specifications given in the Electrical Specification Higher spreading factors and longer transmission times impose more stringent constraints on the short term frequency stability of the reference. Please get in touch with a Anylink / Semtech representative to implement extremely low sensitivity products. For European operation the range of crystal tolerances acceptable for each subband (of the ERC 7003) is given in the specifications table. For US based operation a frequency hopping mode is available that automates both the LoRa spread spectrum and frequency hopping spread spectrum processes. Another important facet of the LoRa modem is its increased immunity to interference. The LoRa modem is capable of cochannel GMSK rejection of up to 25. This immunity to interference permits the simple coexistence of LoRa modulated systems either in bands of heavy spectral usage or in hybrid communication networks that use LoRa to extend range when legacy modulation schemes fail. Anylink

15 7. LINK DESIGN USING THE LoRa MODEM 7.1. OVERVIEW The LoRa modem is setup as shown in the following figure. This configuration permits the simple replacement of the FSK modem with the LoRa modem via the configuration register setting RegOpMode. This change can be performed on the fly (in Sleep operating mode) thus permitting the use of both standard FSK or OOK in conjunction with the long range capability. The LoRa modulation and demodulation process is proprietary, it uses a form of spread spectrum modulation combined with cyclic error correction coding. The combined influence of these two factors is an increase in link budget and enhanced immunity to interference. Figure 2 LoRa Modem Connectivity A simplified outline of the transmit and receive processes is also shown above. Here we see that the LoRa modem has an independent dual port data buffer FIFO that is accessed through the SPI interface common to all modes. Upon selection of LoRa mode, the configuration register mapping of the changes. For full details of this change please consult the register description of Semtech SX1276 Datasheet. ( So that it is possible to optimize the LoRa modulation for a given application, access is given to the designer to three critical design parameters. Each one permitting a tradeoff between link budget, immunity to interference, spectral occupancy and nominal data rate. These parameters are spreading factor, modulation bandwidth and error coding rate. Anylink

16 7.2. SPREADING FACTOR The spread spectrum LoRa TM modulation is performed by representing each bit of payload information by multiple chips of information. The rate at which the spread information is sent is referred to as the symbol rate (Rs), the ratio between the nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information. The range of values accessible with the LoRa TM modem are shown in the following table. SpredingFactor (RegModulationCfg) Spreading Factor (Chips / symbol) Table 14 Range of Spreading Factors LoRa TM Demodulator SNR Note that the spreading factor, SpreadingFactor, must be known in advance on both transmit and receive sides of the link as different spreading factors are orthogonal to each other. Note also the resulting signal to noise ratio (SNR) required at the receiver input. It is the capability to receive signals with negative SNR that increases the sensitivity, so link budget and range, of the LoRa TM receiver. Spreading Factor 6 SF = 6 Is a special use case for the highest data rate transmission possible with the LoRa TM modem. To this end several settings must be activated in the SX1276/77/78 registers when it is in use: Set SpreadingFactor = 6 in RegModemConfig2 The header must be set to Implicit mode Write bits 20 of register address 0x31 to value "0b101" Write register address 0x37 to value 0x0C 7.3. CODING RATE To further improve the robustness of the link the LoRa TM modem employs cyclic error coding to perform forward error detection and correction. Such error coding incurs a transmission overhead the resultant additional data overhead per transmission is shown in the table below. CodingRate Cyclic Coding (RegTxCfg1) Rate Overhead Radio 1 4/ / / /8 2 Table 15 Cyclic Coding Overhead Forward error correction is particularly efficient in improving the reliability of the link in the presence of interference. So that the coding rate (and so robustness to interference) can be changed in response to channel conditions the coding rate can optionally be included in the packet header for use by the receiver. Anylink

17 7.4. SIGNAL BANDWIDTH An increase in signal bandwidth permits the use of a higher effective data rate, thus reducing transmission time at the expense of reduced sensitivity improvement. There are of course regulatory constraints in most countries on the permissible occupied bandwidth. Contrary to the FSK modem which is described in terms of the single sideband bandwidth, the LoRa TM modem bandwidth refers to the double sideband bandwidth (or total channel bandwidth). The range of bandwidths relevant to most regulatory situations is given in the LoRa TM modem specifications Table 8 on Page 9. Bandwidth (khz) Spreading Factor Coding rate Nominal Rb (bps) / / / / / / / / / / Table 16 LoRa TM Bandwidth Options Note: In the lower band (169 MHz), the 250 khz and 500 khz bandwidths are not supported LoRa TM TRANSMISSION PARAMETER RELATIONSHIP With knowledge of the key parameters that can be controlled by the user we define the LoRa TM symbol rate as: R s = BW 2 SF where BW is the programmed bandwidth and SF is the spreading factor. The transmitted signal is a constant envelope signal. Equivalently, one chip is sent per second per Hz of bandwidth. Anylink

18 7.6. LoRa PACKET STRUCTURE The LoRa modem employs two types of packet format, explicit and implicit. The explicit packet includes a short header that contains information about the number of bytes, coding rate and whether a CRC is used in the packet. The packet format is shown in the following figure. The LoRa packet comprises three elements: A preamble. An optional header. The data payload. Figure 3 LoRa Packet Structure PREAMBLE The preamble is used to synchronize receiver with the incoming data flow. Although by default, it consists of a 12 symbol long sequence the receiver does not require knowledge of the preamble length. The preamble length may be extended in the interest of reducing to receiver duty cycle in receive intensive applications. However, the minimum length suffices for all communication. The transmitted preamble length may be changed by setting the register PreambleLength from 12 to HEADER Depending upon the chosen mode of operation two types of header are available. The header type is selected by the ImplictHeaderMode bit found within the RegSymbTimeoutMsb register EXPLICIT HEADER MODE This is the default mode of operation. Here the header provides information on the payload, namely: The payload length in bytes. The forward error correction code rate The presence of an optional 16bits CRC for the payload. The header is transmitted with maximum error correction code (4/8). It also has its own CRC to allow the receiver to discard invalid headers IMPLICIT HEADER MODE In certain scenarios, where the payload, coding rate and CRC presence are fixed or known in advance, it may be advantageous to reduce transmission time by invoking implicit header mode. In this mode the header is removed from the packet. In this case the payload length, error coding rate and presence of the payload CRC must be manually configured on both sides of the radio link PAYLOAD The packet payload is a variablelength field that contains the actual data coded at the error rate either as specified in the header in explicit mode or in the register settings in implicit mode. An optional CRC may be appended. Anylink

19 7.7. TIME ON AIR For a given combination of spreading factor (SF), coding rate (CR) and signal bandwidth (BW) the total ontheair transmission time of a LoRa packet can be calculated as follows. From the definition of the symbol rate it is convenient to define the symbol rate: Ts = 1 Rs The LoRa TM packet duration is the sum of the duration of the preamble and the transmitted packet. The preamble length is calculated as follows: T preamble = (n preamble )T sym where n preamble is the programmed preamble length, taken from the registers RegPreambleMsb and RegPreambleLsb. The payload duration depends upon the header mode that is enabled. The following formula gives the number of payload symbols. 8PL 4SF H payloadsymbnb = 8 + max (ceil ( ) (CR + 4), 0) 4(SF 2DE) With the following dependencies: PL is the number of Payload bytes SF is the spreading factor H=0 when the header is enabled, H=1 when no header is present DE=1 when LowDataRateOptimize=1, DE=0 otherwise CR is the coding rate from 1 to 4 The Payload duration is then the symbol period multiplied by the number of Payload symbols T payload = payloadsymnbtsym The time on air, or packet duration, in simply then the sum of the preamble and payload duration FREQUENCY HOPPING WITH LoRa T packet = T preamble + T payload The duration of a single packet could exceed regulatory requirements relating to the maximum permittable channel dwell time. To ease implementation and ensure continued compliance when operating in frequency hopping spread spectrum (FHSS) mode (FhssMode of register RegTxCfg1) can be enabled. Anylink

20 PRINCIPLE OF OPERATION The principle behind the FHSS scheme is that a portion of each LoRa packet is transmitted on each hopping channel from a look up table of frequencies managed by the host microcontroller. After a predetermined hopping period the transmitter changes to the next channel in a predefined list of hopping frequencies and continues transmitting the next symbol of the packet. The time which the transmission will last in any given channel is determined by HoppingPeriod which is an integer multiple of symbol periods: HoppingPeriod = TS FreqHoppingPeriod The frequency hopping transmission and reception process starts at channel 0, following each frequency hop the channel counter stored in FhssPresentChannel is incremented and the interrupt signal FhssChangeChannel is generated. Upon completion of the transmission on any given channel the companion microcontroller must hence read the FhssPresentChannel value and load the corresponding RF centre frequency into the Frf register. FHSS Reception always starts on channel 0. The receiver waits for a valid preamble detection before starting the frequency hopping process as described above. Note that in the eventuality of header CRC corruption, the receiver will automatically request channel 0 and recommence the valid preamble detection process TIMING OF CHANNEL UPDATES The interrupt requesting the channel change, FhssChannelChange, is generated at least 1 ms before the next frequency value must be written allowing ample time for most MCUs to update the register. The frequency hopping process is recapitulated in the diagram below: Figure 4 Interrupts generated in the case of successful frequency hopping communication Anylink

21 8. FSK/OOK MODEM 8.1. BIT RATE SETTING The bitrate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalently chip) rate of the radio. In continuous transmit mode the data stream to be transmitted can be input directly to the modulator via pin 9 (DIO2/DATA) in an asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin 8 (DIO1/DCLK) is used to synchronize the data stream. In Packet mode or in Continuous mode with Gaussian filtering enabled, the Bit Rate (BR) is controlled by bits Bitrate in RegBitrateMsb and RegBitrateLsb BitRate = FXOSC BitRate(15,0) + BitrateFrac 16 Note: BitrateFrac bits have no effect (i.e may be considered equal to 0) in OOK modulation mode. The quantity BitrateFrac is hence designed to allow very high precision (max. 250 ppm programing resolution) for any bitrate in the programmable range. Table 24 below shows a range of standard bitrates and the accuracy to within which they may be reached. Type BitRate (15:8) BitRate (7:0) (G)FSK (G)MSK OOK Actual BR (b/s) Classical modem baud rates (multiples of 1.2 kbps) Classical modem baud rates (multiples of 0.9 kbps) Round bit rates (multiples of 12.5, 25 and 50 kbps) 0x68 0x2B 1.2 kbps 1.2 kbps x34 0x kbps 2.4 kbps x1A 0x0B 4.8 kbps 4.8 kbps x0D 0x kbps 9.6 kbps x06 0x kbps 19.2 kbps x03 0x kbps x01 0xA kbps x00 0xD kbps x02 0x2C 57.6 kbps x01 0x kbps x0A 0x kbps 12.5 kbps x05 0x00 25 kbps 25 kbps x80 0x00 50 kbps x01 0x kbps x00 0xD5 150 kbps x00 0xA0 200 kbps x00 0x kbps x00 0x6B 300 kbps Watch Xtal frequency 0x03 0xD kbps kbps Table 17 Bit Rate Examples Anylink

22 9. OPERATING MODES IN FSK/OOK MODE 9.1. GENERAL OVERVIEW The has several working modes, manually programmed in RegOpMode. Fully automated mode selection, packet transmission and reception is also possible using the Top Level Sequencer described in Section Mode Selected mode Symbol Enabled blocks 000 Sleep mode Sleep None 001 Standby mode Stdby Top regulator and crystal oscillator 010 Frequency synthesiser to Tx frequency FSTx Frequency synthesizer at Tx frequency ( Frf ) 011 Transmit mode Tx Frequency synthesizer and transmitter 100 Frequency synthesiser to Rx frequency FSRx Frequency synthesizer at frequency for reception ( FrfIF ) 101 Receive mode Rx Frequency synthesizer and receiver Table 18 Basic Transceiver Modes When switching from a mode to another the subblocks are woken up according to a predefined optimized sequence STARTUP TIMES The startup time of the transmitter or the receiver is dependent upon which mode the transceiver was in at the beginning. For a complete description, Figure 6 below shows a complete startup process, from the lower power mode Sleep. Figure 5 Startup Process TS_OSC is the startup time of the crystal oscillator which depends on the electrical characteristics of the crystal. TS_FS is the startup time of the PLL including systematic calibration of the VCO. Anylink

23 TRANSMITTER STARTUP TIME The transmitter startup time, TS_TR, is calculated as follows in FSK mode: TS TR = 5µs PaRamp Tbit PaRamp is the rampup time programmed in RegPaRamp. Tbit is the bit time. In OOK mode, this equation can be simplified to the following: TS TR = 5µs Tbit RECEIVER STARTUP TIME The receiver startup time, TS_RE, only depends upon the receiver bandwidth effective at the time of startup. When AFC is enabled (AfcAutoOn=1), AfcBw should be used instead of RxBw to extract the receiver startup time: RxBw if AfcAutoOn=0 RxBwAfc if AfcAutoOn=1 TS_RE (+/5%) 2.6 khz 2.33 ms 3.1 khz 1.94 ms 3.9 khz 1.56 ms 5.2 khz 1.18 ms 6.3 khz 984 µs 7.8 khz 791 µs 10.4 khz 601 µs 12.5 khz 504 µs 15.6 khz 407 µs 20.8 khz 313 µs 25.0 khz 264 µs 31.3 khz 215 µs 41.7 khz 169 µs 50.0 khz 144 µs 62.5 khz 119 µs 83.3 khz 97 µs khz 84 µs khz 71 µs khz 85 µs khz 74 µs khz 63 µs Table 19 Receiver Startup Time Summary TS_RE or later after setting the device in Receive mode, any incoming packet will be detected and demodulated by the transceiver. Anylink

24 TIME TO RSSI EVALUATION The first RSSI sample will be available TS_RSSI after the receiver is ready, in other words TS_RE + TS_RSSI after the receiver was requested to turn on. Figure 6 Time to Rssi Sample TS_RSSI depends on the receiver bandwidth, as well as the RssiSmoothing option that was selected TX TO RX TURNAROUND TIME Figure 7 Tx to Rx Turnaround Note The SPI instruction times are omitted, as they can generally be very small as compared to other timings (up to 10MHz SPI clock) RX TO TX Figure 8 Rx to Tx Turnaround Anylink

25 RECEIVER HOPPING; RX TO RX Two methods are possible: Figure 9 Receiver Hopping The second method is quicker, and should be used if a very quick RF sniffing mechanism is to be implemented TX TO TX Figure 10 Transmitter Hopping Anylink

26 9.3. RECEIVER STARTUP OPTIONS The receiver can automatically control the gain of the receive chain (AGC) and adjust the receiver LO frequency (AFC). Those processes are carried out on a packetbypacket basis. They occur: When the receiver is turned On. When the Receiver is restarted upon user request, through the use of trigger bits RestartRxWithoutPllLock or RestartRxWithPllLock, in RegRxConfig. When the receiver is automatically restarted after the reception of a valid packet, or after a packet collision. The receiver startup options available in are described in Table 18. Triggering Event Realized Function AgcAutoOn AfcAutoOn RxTrigger (2:0) None None Rssi Interrupt AGC AGC & AFC PreambleDetect AGC AGC & AFC Rssi Interrupt & PreambleDetect AGC AGC & AFC Table 20 Receiver Startup Options When AgcAutoOn=0, the LNA gain is manually selected by choosing LnaGain bits in RegLna RECEIVER RESTART METHODS The options for restart of the receiver are covered below. This is typically of use to prepare for the reception of a new signal whose strength or carrier frequency is different from the preceding packet to allow the AGC or AFC to be reevaluated RESTART UPON USER REQUEST In Receive mode the user can request a receiver restart this can be useful in conjunction with the use of a Timeout interrupt following a period of inactivity in the channel of interest. Two options are available: No change in the Local Oscillator upon restart: the AFC is disabled, and the Frf register has not been changed through SPI before the restart instruction: set bit RestartRxWithoutPllLock in RegRxConfig to 1. Local Oscillator change upon restart: if AFC is enabled (AfcAutoOn=1), and/or the Frf register had been changed during the last Rx period: set bit RestartRxWithPllLock in RegRxConfig to 1. Note ModeReady must be at logic level 1 for a new RestartRx command to be taken into account AUTOMATIC RESTART AFTER VALID PACKET RECEPTION The bits AutoRestartRxMode in RegSyncConfig control the automatic restart feature of the receiver, when a valid packet has been received: If AutoRestartRxMode = 00, the function is off, and the user should manually restart the receiver upon valid packet reception. If AutoRestartRxMode = 01, after the user has emptied the FIFO following a PayloadReady interrupt, the receiver will automatically restart itself after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence avoiding a false RSSI detection on the tail of the previous packet. If AutoRestartRxMode = 10 should be used if the next reception is expected on a new frequency, i.e. Frf is changed after the reception of the previous packet. An additional delay is systematically added, in order for the PLL to lock at a new frequency. Anylink

27 AUTOMATIC RESTART WHEN PACKET COLLISION IS DETECTED In receive mode the is able to detect packet collision and restart the receiver. Collisions are detected by a sudden rise in received signal strength, detected by the RSSI. This functionality can be useful in network configurations where many asynchronous slaves attempt periodic communication with a single a master node. The collision detector is enabled by setting bit RestartRxOnCollision to 1. The decision to restart the receiver is based on the detection of RSSI change. The sensitivity of the system can be adjusted in 1 steps by using register RssiCollisionThreshold in RegRxConfig TOP LEVEL SEQUENCER Depending on the application, it is desirable to be able to change the mode of the circuit according to a predefined sequence without access to the serial interface. In order to define different sequences or scenarios, a userprogrammable state machine, called Top Level Sequencer (Sequencer in short), can automatically control the chip modes. NOTE: THIS FUNCTIONALITY IS ONLY AVAILABLE IN FSK/OOK MODE. The Sequencer is activated by setting the SequencerStart bit in RegSeqConfig1 to 1 in Sleep or Standby mode (called initial mode). It is also possible to force the Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time. Note: SequencerStart and Stop bit must never be set at the same time SEQUENCER STATES As shown in the table below, with the aid of a pair of interrupt timers (T1 and T2), the sequencer can take control of the chip operation in all modes. Sequencer State SequencerOff State Idle State Transmit State Receive State PacketReceived LowPowerSelection RxTimeout Description The Sequencer is not activated. Sending a SequencerStart command will launch it. When coming from LowPowerSelection state, the Sequencer will be Off, whilst the chip will return to its initial mode (either Sleep or Standby mode). The chip is in lowpower mode, either Standby or Sleep, as defined by IdleMode in RegSeqConfig1. The Sequencer waits only for the T1 interrupt. The transmitter in on. The receiver in on. The receiver is on and a packet has been received. It is stored in the FIFO. Selects low power state (SequencerOff or Idle State) Defines the action to be taken on a RxTimeout interrupt. RxTimeout interrupt can be a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt. Table 21 Sequencer States Anylink

28 SEQUENCER TRANSITIONS The transitions between sequencer states are listed in the forthcoming table. Variable IdleMode FromStart LowPowerSelection FromIdle FromTransmit FromReceive FromRxTimeout FromPacketReceived Transition Selects the chip mode during Idle state: 0: Standby mode 1: Sleep mode Controls the Sequencer transition when the SequencerStart bit is set to 1 in Sleep or Standby mode: 00: to LowPowerSelection 01: to Receive state 10: to Transmit state 11: to Transmit state on a FifoThreshold interrupt Selects Sequencer LowPower state after a to LowPowerSelection transition 0: SequencerOff state with chip on Initial mode 1: Idle state with chip on Standby or Sleep mode depending on IdleMode Note: Initial mode is the chip LowPower mode at Sequencer start. Controls the Sequencer transition from the Idle state on a T1 interrupt: 0: to Transmit state 1: to Receive state Controls the Sequencer transition from the Transmit state: 0: to LowPowerSelection on a PacketSent interrupt 1: to Receive state on a PacketSent interrupt Controls the Sequencer transition from the Receive state: 000 and 111: unused 001: to PacketReceived state on a PayloadReady interrupt 010: to LowPowerSelection on a PayloadReady interrupt 011: to PacketReceived state on a CrcOk interrupt. If CRC is wrong (corrupted packet, with CRC on but CrcAutoClearOn is off), the PayloadReady interrupt will drive the sequencer to RxTimeout state. 100: to SequencerOff state on a Rssi interrupt 101: to SequencerOff state on a SyncAddress interrupt 110: to SequencerOff state on a PreambleDetect interrupt Irrespective of this setting, transition to LowPowerSelection on a T2 interrupt Controls the statemachine transition from the Receive state on a RxTimeout interrupt (and on PayloadReady if FromReceive = 011): 00: to Receive state via ReceiveRestart 01: to Transmit state 10: to LowPowerSelection 11: to SequencerOff state Note: RxTimeout interrupt is a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt. Controls the statemachine transition from the PacketReceived state: 000: to SequencerOff state 001: to Transmit on a FifoEmpty interrupt 010: to LowPowerSelection 011: to Receive via FS mode, if frequency was changed 100: to Receive state (no frequency change) Table 22 Sequencer Transition Options Anylink

29 TIMERS Two timers (Timer1 and Timer2) are also available in order to define periodic sequences. These timers are used to generate interrupts, which can trigger transitions of the Sequencer. T1 interrupt is generated (Timer1Resolution * Timer1Coefficient) after T2 interrupt or SequencerStart. command. T2 interrupt is generated (Timer2Resolution * Timer2Coefficient) after T1 interrupt. The timers mechanism is summarized on the following diagram. Figure 11 Timer1 and Timer2 Mechanism Note: The timer sequence is completed independently of the actual Sequencer state. Thus, both timers need to be on to achieve periodic cycling. Variable Timer1Resolution Timer2Resolution Timer1Coefficient Timer2Coefficient Description Resolution of Timer1 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms Resolution of Timer2 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms Multiplying coefficient for Timer1 Multiplying coefficient for Timer2 Table 23 Sequencer Timer Settings Anylink

30 SEQUENCER STATE MACHINE The following graphs summarize every possible transition between each Sequencer state. The Sequencer states are highlighted in grey. The transitions are represented by arrows. The condition activating them is described over the transition arrow. For better readability, the start transitions are separated from the rest of the graph. Transitory states are highlighted in light grey, and exit states are represented in red. It is also possible to force the Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time. Figure 12 Sequencer State Machine Anylink

31 10. PACKET FORMAT FIXED LENGTH PACKET FORMAT Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater than 0. In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the same packet length value. The length of the payload is limited to 2047 bytes. The length programmed in PayloadLength relates only to the payload which includes the message and the optional address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte. An illustration of a fixed length packet is shown below. It contains the following fields: Preamble ( ) Sync word (Network ID) Optional Address byte (Node ID) Message data Optional 2bytes CRC checksum Figure 13 Fixed Length Packet Format VARIABLE LENGTH PACKET FORMAT Variable length packet format is selected when bit PacketFormat is set to 1. This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to 255 bytes. Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. An illustration of a variable length packet is shown below. It contains the following fields: Preamble ( ) Sync word (Network ID) Length byte Optional Address byte (Node ID) Message data Optional 2bytes CRC checksum Anylink

32 Figure 14 Variable Length Packet Format UNLIMITED LENGTH PACKET FORMAT Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can then transmit and receive packet of arbitrary length and PayloadLength register is not used in Tx/Rx modes for counting the length of the bytes transmitted/received. In Tx the data is transmitted depending on the TxStartCondition bit. On the Rx side the data processing features like Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero (SyncOn = 0). The filling of the FIFO in this case can be controlled by the bit FifoFillCondition. The CRC detection in Rx is also not supported in this mode of the packet handler, however CRC generation in Tx is operational. The interrupts like CrcOk & PayloadReady are not available either. An unlimited length packet shown below is made up of the following fields: Preamble ( ). Sync word (Network ID). Optional Address byte (Node ID). Message data Optional 2bytes CRC checksum (Tx only) Figure 15 Unlimited Length Packet Format Anylink