IMPLEMENTATION OF VLSI BASED ARCHITECTURE FOR KAISER-BESSEL WINDOW USING MANTISSA IN SPECTRAL ANALYSIS
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1 IMPLEMENTATION OF VLSI BASED ARCHITECTURE FOR KAISER-BESSEL WINDOW USING MANTISSA IN SPECTRAL ANALYSIS Ms.Yamunadevi.T 1, AP/ECE, Ms.C.EThenmozhi 2,AP/ECE and Mrs.B.Sukanya 3, AP/ECE 1,2,3 Sri Shanmugha College of Engineering and Technology, Pullipalayam, Sankiri,Salem(Dt) Abstract - This paper, proposed VLSI based Architecture for Kaiser-Bessel Window is implemented by using mantissa. Since most of the implementation of windowing functions for real time application are based on ROM based or flexible processor. Here the proposed architecture is designed using mantissa. This proposed architecture is suitable to use before FFT for real time digital spectral analysis system and also can be used for filtering applications to compute Kaiser-Bessel window coefficients and the error analysis has been discussed. The proposed architecture has synthesised in Synopsys design compiler (Design Vision) using TSMC 90 nm technology library. Index Terms Bessel argument generator, Bessel Function, Kaiser Bessel Window Co-efficient, Mantissa. I. INTRODUCTION Digital Signal Processing is the mathematical manipulation of information signal to modify or improve it in some way. To digitally analyze and manipulate an analog signal, it must be digitized with an analog to digital converter. In many digital signal processing application, Fast Fourier Transform (FFT) is widely used for real time spectral analysis. In any practical measurement system it is necessary to limit the time during which a signal is observed. This process is known as windowing. Only in the case of an exact synchronization between the observation time and the period of the signal, there is no truncation error at the end of the window so that the spectrum of the signal is correct. In any other case, any frequency component of the signal not periodic with the observation time will present an uncertainty in the determination of the component due to the loss of continuity at the boundaries of the window. The error introduced is known as spectral leakage and produces a spread of energy over the whole frequency spectrum of the signal [7]. The classical approach to reduce the effect of the spectral leakage associated with finite observation intervals is the use of windows functions. These are weighting functions that are applied to data to reduce the discontinuities at the boundaries of the observation time. There are many possible window functions with different responses in the frequency domain. The objective when choosing a window function is to obtain the best frequency resolution (the main-lobe as narrow as possible) and the least contribution from interfering spectral components (minimum side lobe levels). These two conditions are closely related and a compromise should be made between main-lobe width and side lobe level reduction [7]. The choice of a window function has a great influence on the performance of the measurement of harmonics and inters harmonics. Detectability, resolution and dynamic range are dependent on the window function chosen. An in-depth analysis of many window functions and their effect on the detection of harmonic signals in the presence of noise and in the presence of nearby strong harmonic interference, using the DFT All Rights Reserved 1
2 A Window Function To reduced spectral resolution windows function is generally used. As time domain multiplication will be equivalent to a convolution in frequency domain, the window function introduces an artificial structure to the original signal being transformed. The spectral resolution in particular will be dramatically reduced when the window function is used; interpolation in time domain is equivalent to an extrapolation in frequency domain. During this operation, there is an assumption that the spectrum is outside the range of the original signal being transformed. In some applications such as FFT, signal processing and measurement where higher side lobe attenuation is required compared to Hamming, Hanning and Blackman window. B Spectral Analysis The spectral leakage can be produced by a synchronization error between the fundamental period of the signal and the window width and by the presence of inter-harmonics non-synchronized with the fundamental frequency [5]. A fundamental condition of using Discrete Fourier is that the signal being transformed needs to be periodic and transform is performed on an integer number of these periods. In practice, due to some physical limitations, this condition is not always satisfied. A phenomenon known as leakage will occur and cause serious distortion in the transformed signal. In signal processing parlance, windowing refers to the process of modifying the input samples before utilizing them for computing discrete Fourier transforms (DFT), such that spectral leakage and picket fence effect can be minimized. Thus it becomes essential to have high throughput hardware realization for window functions to match the speed of the FFT architecture in order to develop an efficacious real-time spectral analysis system. Depending on the intended application, the system designer can choose from a handful of available windows to satisfy the trade-off between various parameters such as accuracy of amplitude and spectral purity [1]. Window functions or time domain interpolation resampling is used in case a transform needs to be applied to data that does not satisfy this coherent condition. An introduction to the leakage problem and an overview of the properties of different windows can be found in multiple references. We multiply a window function to make the data artificially periodic. As time domain multiplication is equivalent to a convolution in frequency domain, the window function introduces an artificial structure to the original signal being transformed. Rest of this paper is organised as follow. Section II describes Kaiser Windowing function. Our proposed Kaiser architecture and Mantissa Algorithm with its architectures is discussed in section III. Section IV presents the synthesis results and discussions, and finally Section V concludes the paper. II. BACKGROUND A Kaiser Bessel Window During Spectral Analysis, the input signals are to be truncated to fit a finite observation window according to the length of FFT processor. This direct truncation is done by using windowing. When we are using rectangular window function leads to undesirable affects known as spectral leakage in frequency domain. To minimize these spectral affects during spectral analysis, we are using different kinds of windowing function such as Hamming, Hanning, Blackman and Kaiser Bessel Window. Kaiser Bessel window have narrow spectrum compared to the Blackman window. ROM Based implementation restricts the flexible implementation and also restricts fitting with the advanced FFT All Rights Reserved 2
3 Fig.1. Block Diagram for spectrum Analysis Basic idea of this work is to propose a flexible architecture for Kaiser Bessel Windowing function to fit with the advanced FFT Processor. Kaiser Bessel Windowing function has been highlighted here briefly. A typical block diagram for real time FFT based spectral analysis system is shown in Fig.1, where input samples are pre-processed with real time Kaiser Bessel Windowing function before FFT as follows S o (n) = W k (n) S i (N 1 + r n) (1) Here r indicates presents time variable. n is discrete time index ranges from 0 to N-1, where N is the windowing length. Si and So are input and output signals for windowing function, whereas wk (n) is co-efficient of Kaiser Bessel Window. The general equation of the Kaiser- Bessel Window is given as I O (β {1 [ 2n N ] 2} ) 1 2 w k (n) = for ( N I o (β) 2 1) n + (N 2 1) 0 { (2) Where Io(.) implies the zeroth order Bessel Function that can be expressed by the following equation: I o (x) = e x ( x ) 2πx (3) Where x represents the Bessel Function variable which vary depends on the numerator parts are varied. For flexible window length is setting where window length (N) is user defined as per requirement for the application and high throughput VLSI architecture using Mantissa whose implementation is less hardware cost. Since equation (2) needs trigonometric function, so the implementation using Mantissa algorithm is better choice in terms of computation. The trigonometric functions are hyperbolic and exponential function which is done by using Mantissa algorithm. III. PROPOSED ARCHITECTURE The proposed Architecture describes the computation of Kaiser Bessel window coefficient and the major parts of the proposed architecture are described in detail. A. Bessel Angle Generator Architecture A pipelined implementation of the single- precision floating-point square root unit. We used the highspeed carry-propagation circuit in the design. Because the high-order square root bits can be All Rights Reserved 3
4 very fast, it is not necessary to use a whole pipeline stage for one bit. Pipeline registers are placed between the stages. The implementation is fully pipelined and capable of accepting a new square root instruction on every cycle. Fig.2. Block Diagram of Pipelined implementation of floating-point square root to generate Bessel Argument In Eq (2), the numerator part denotes the Bessel argument generator (BAG), the sequence of the Bessel Argument is A (n) = (β) 2 (2πβ/n) 2 (5) Let β be the time-bandwidth, N be the window length and n be the N/2 i.e half of the Window length. Here β as 8.5, N as 64 and n varies from 0 to All Rights Reserved 4
5 Fig.3. Floating point Division to generate Bessel Function Fig 4. Floating Point Multiplication to generate Output Sample The architecture to generate sequence of Bessel Argument A(n ) is shown in Fig. 2. By dividing the sequence of angle generator and the sequence of Bessel function, we get the window co-efficient. In Eq (3), the denominator part is denoted as the Bessel Function. The Bessel Function which contain square root, exponential and multiplication. The constant term 2πx as in Eq (3). All these trigonometric function are done by using All Rights Reserved 5
6 B Kaiser Window Architecture Window Coefficient Fig.5. Kaiser Window Architecture Input Sample Output Sample Table.1. Window Co-Efficient and input samples The Kaiser Bessel Window Architecture consist of Bessel Argument Generator, Bessel Function and Input Sample. The Bessel Function is generated as shown in Fig.3. The Floating Point Division is done to generate Bessel Function. It produces the exponential function which is given in the Lookup Table. In eq(3), the square root function which produces the square root value for the sequence of Bessel argument generator. Finally it s generated the sequence of Bessel Function. Floating Point Division is used to divide the numerator part of the sequences of the Bessel Argument with the denominator part of the sequences of the Bessel Function which produces the Kaiser Window Co-efficient Wk (n). The signal Si is generated from the analog to digital convertor. Mantissa Multiplier (Rotation mode) is used to multiply the input signal Si with Kaiser Bessel Window Co-efficient Wk (n) which produces the output signal so. Steps to Compute Floating Point Multiplication: i. First compute the sign, exponent, mantissa of the two operands. ii. The sign bit of the result is obtained by xoring the sign bits of two operands. iii. First convert the biased exponents to unbiased notation, add the exponents and then result of the exponent should be represented in biased notation. iv. Multiply the mantissas of two operands and this result should be normalized that means the mantissa result should be in the range of [0:31]. v. The result is normalized by shift left, right correspondingly exponent was adjusted. vi. After the normalization result is rounded to nearest All Rights Reserved 6
7 IV. SYNTHESIS RESULTS AND DISCUSSIONS The proposed architecture for 16 bit word size has been coded using VHDL at structural level and simulated using Xilinx is shown in Fig.6 and finally synthesized in Synopsys Design Complier (Design Vision) using TSMC 90nm technology library. It has been found that it can operate at a maximum frequency of 200 MHz. The synthesized results shows that, the chip occupies a core area of units. Thus the implementation of Kaiser Bessel Window Architecture using Mantissa enhances the result in terms of throughput i.e. the throughput of this implementation is 200 M Samples/s. The comparison synthesized result of Windowing function is shown in Table.2. Table.2.Comparison of Synthesis Result of Windowing Function Parameters Hamming Window Kaiser Bessel Window Area Power mw mw Frequency 200 MHZ 200 MHZ Fig.6. Simulation of Kaiser Window Architecture V. CONCLUSION The Proposed Kaiser Bessel Window architecture has been achieved the high throughput and low power. The Kaiser Bessel Window architectures are used with low hardware cost. The Kaiser Bessel Window co-efficient is efficiently generated by using Mantissa compared to other window Function. In future, the design of a FFT Algorithm based spectrum Analyzer using FPGA for real time application is to be done. REFERENCES [1] R. Zimmerman, Efficient VLSI Implementation of Modulo 2n+1Þ Addition and Multiplication, Proc. 14th IEEE Symp. Computer Arithmetic, pp , Apr [2] Park, S.Y., & Cho, N.I. (2004). Fixed-point error analysis of CORDIC processor based on the variance propagation formula. IEEE Transactions on Circuits and Systems-1. 51(3), [3] M. Birman, A. Samuels, G. Chu, T. Chuk, L. Hu, J. McLeod, and J. Barnes, Developing the WTL3170/3171 Sparc Floating-Point Coprocessors, IEEE MICRO February, All Rights Reserved 7
8 [4] Padala, S.K., & Prabhu, K.M.M. (1999). Pipelined CORDIC processors for generating Gaussian random numbers. Signal Processing, 72(3), [5] M. Ercegovac and T. Lang, Radix-4 Square Root Without Initial PLA, IEEE Transaction on Comput- ers, Vol. 39, No. 8, pp [6] G. Knittel, A VLSI-Design for Fast Vector Normal- ization Comput. & Graphics, Vol. 19, No. 2, pp [7] Prabhu, K.M.M., & Bhoopathy Bagan, B.K. (1989). Variable parameter window families for digital spectral analysis. IEEE Transactions on Speech and Signal Processing, 37(6), [8] J. Prabhu and G. Zyner, 167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages, Proc. of 12th IEEE Symposium on Computer Arith- metic, IEEE Computer Society Press, pp [9] Sung, T.U., & Hsin, H.C. (2007). Fixed point error analysis of arithmetic for special-purpose signal processing. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, A(9), [10] Shuenn-shyang, W., & Chien-Sung, L. (2008). An area-efficient design of variable length fast Fourier transform processor. Journal of Signal Processing Systems, 51, [11] Zhang S., Yu, D & Sheng S. (2006). A discrete STFT processor for real-time spectrum analysis. In Proceedings on circuits and systems, IEEE Asia-Pacific conference, (pp ). [12] S.-H. Lin and M.-H. Sheu, VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Section, IEEE Trans. Circuits and Systems II, vol. 55, no. 9, pp , Sept [13] Shuenn-shyang W & Chien-Sung L (2008). An area-efficient design of variable length fast Fourier transform processor. Journal of Signal Processing Systems, 51, [14] Dhanabal R,,Bharathi V,Saira Salim, Bincy Thomas, Hyma Soman, Dr Sarat Kumar Sahoo DESIGN OF 16-BIT LOW POWER ALU - DBGPU,International Journal of Engineering and Technology (IJET) [15] S.-H. Lin and M.-H. Sheu, VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Section, IEEE Trans. Circuits and Systems II, vol. 55, no. 9, pp , Sept. All Rights Reserved 8
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