HIGH-SPEED VLSI IMPLEMENTATION SYSTEMATIC SCHEME FOR DWT

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1 International Journal of Civil Engineering and Technology (IJCIET) Volume 8, Issue 10, October 2017, pp , Article ID: IJCIET_08_10_043 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed HIGH-SPEED VLSI IMPLEMENTATION SYSTEMATIC SCHEME FOR DWT M. Vijay Albert William Assistant Professor, Department of ECE, Vel Tech University, Chennai, India D. Balaji Assistant Professor, Department of ECE, Vel Tech University, Chennai, India K. Bhaskar Assistant Professor, Department of EEE, Vel Tech University, Chennai, India ABSTRACT The wavelet transform has proved to be the efficient transform for the decade for realtime signal processing. The scalar wavelets have been widely used in applications like signal denoising image compression and in medical fields. Wavelet transform possesses a number of desirable properties such as compact support, regularities, orthogonality and symmetry. Information or data are carried by signals in the field of communication. While transmission interference combine with the pure signal to form noise. Even though many algorithms are developed for the removal of noise in the receiver side, the SNR ratio is not appreciable to receive the original signal from the noise. Due to certain disadvantages in Fourier transform, the researchers concentrated on Wavelet transform by which removal of noise was found easy. In such case wavelet transform has to be implemented as circuit and made available in the receiver side. Thus recent researches aim in forming VLSI architecture, for wavelet transform. If wavelet transform is implemented in VLSI, the speed can be increased and thus latency, area, power can be reduced. The first architecture for wavelet transform was named as folded architecture by Parhi [10]. But the architecture found many disadvantage in terms of speed. Several other architectures were formed to increase the speed and to reduced the power. This research proposal with this literature survey aims in the VLSI architecture of wavelet transform by modifying the existing architecture. Since multipliers are available in the architecture of wavelet transform, the proposal decreses the no of multipliers there by decreasing the area. If area is reduced speed is increased. Key words: DWT, VLSI, FFT editor@iaeme.com

2 M. Vijay Albert William, D. Balaji and K. Bhaskar Cite this Article: M. Vijay Albert William, D. Balaji and K. Bhaskar, High-Speed VLSI Implementation Systematic Scheme for DWT. International Journal of Civil Engineering and Technology, 8(10), 2017, pp INTRODUCTION Many signal encoding and decoding applications like signal processing, edge detection, feature extraction, digital signal processing, speech recognition, digital synthezier, echo cancelation and multimedia compression deploy the DWT. JPEG2000, the image compression engine, has adopted the DWT as its conversion standard. Multiresolution checking, time & frequency analysis and coding are some of the main features which make the DWT is a major choice. FIR structures are considered to be an inevitable part of filter design in DWT. FIR filters which are mainly composed of sub-filters, when directly implemented for DWT are mostly found to be inefficient. Different logics have been derived toward deriving filtering process in the olden days. The logical algorithms will first arrive a small filters and then multiplied or iterated them to design finite impulse response (FIR) filters with many different blocks of filter sizes. Eventhough, the mini sized filter were calculatively efficient, and the number of required time delaying paramenters increases with respect to level of parallelism. The work is carried out in three different steps. Implementation of wavelet transform in MATLAB 2008a and to check the performance of DB4 Wavelet by decomposing and reconstructing an ID signal. Implementation of wavelet transform is done by using the Xilinx system generator with Matlab/Sinuslink. The architecture then has to be synthesized in Xilinx ISE for the target device virtex5 2. BACKGROUND The finite impulse response filter have continues to be fundamental processing elements in digital signal processing system. finite impulse response filters are used in signal processing applications and range from moving and motion picture processing through wire less communications. In some of the applications, such as motion picture processing, the finite impulse response filter circuit must be used to work at high frequency ranges, and in other applications, such as mobile, the finite impulse response filter circuit can be a low power, that is capable of functioning at moderate frequencies [1]. Block, processing can be applied to digital finite impulse response filters to either increase the effective output or to reduce the power consumption of the actual filter. Techinically, they were used for processing an finite impulse response filter involves the duplcation of hardware units that is available as the original filter. If the circuit requires the original filter as A, then the Lparallel circuit requires an area of L x A. With the continuing trend to reduce chip size and integrate multi-chip solutions into a single chip solution, it is important to limit the silicon area required to implement a FIR digital filter in it VLSI implementation. In many design situations, the hardware overhead that is incurred by processing cannot be tolerated due to limitations in design area. Therefore, it is advantageous to realize DWT filtering structures that consume less area than traditional FIR filtering structures. While FIR filters have been given extensive consideration in the existing literature, most of this work focuses on only a single aspect such as filter design (coefficient generation) [2] or filter coefficient quantization [3] or generation of filter circuits through compilation. Furthermore, very little work has been done that deals directly with reducing the hardware complexity of FIR filters [4]. In order to design areaefficient filter must consider the entire design process editor@iaeme.com

3 High-Speed VLSI Implementation Systematic Scheme for DWT 3. SIGNIFICANT WORK Discrete wavelet transform (DWT) has traditionally been applioed by convolution or FIR filter bank, based on its structures. For a image, we use direct implementation of DWT requires a computing time of around 4N2 time where N represents the image size. Traditionally, many hardware succesful fast Very Large Sale Implementaition DWT architectures has been presented. Lifting and flipping-based DWT implementations have many advantages and have recently been proposed for the JPEG2000 standard for image compression. For example, they often require fewer computations, compared to the convolution or FIR filters bank-based DWT [8]. All the reported DWT architectures are usually designed for a certain processing speed and cannot be easily extended to achieve a higher processing speed. For example, as far as the authors know, the current high-speed convolution-based and liftingbased DWT VLSI architectures can achieve the lowest computing time of N2/3 and N2+N, respectively. When the processing speed is improved, must also control the increase of hardware cost. A new DWT VLSI implementation scheme is proposed in this paper. 4. CONTRIBUTION This work presents a novel approach for implementing area-efficient (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by 61 factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is advantageous to produce FIR filter implementations that require less area than traditional block FIR filtering structures. In this project, a method to design FIR filter structures that require a less-than-linear increase in the hardware cost is proposed. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, it is shown that FIR: filtering structures with up to a 45% reduction in hardware is achieved. 5. ORGANIZATION OF THE DISSERTATION The remainder of this document is organized as follows. Chapter one explained related work in this field. Chapter two describes Wavelet transform based existing implementation and literature survey. Next, chapter three explains the design and implementation of the DWT using FIR filters in Xilinx system generator. Then, chapter four summarizes the development platform used for the project. Chapter 5 deals with the software description and finally chapter 6 summarizes the results as synthesis report. Finally the last chapter discusses about the conclusion and future. 6. DESIGN IMPLEMENTATION It is well-known that the application of processing to a FIR filter can increase the throughput of the DWT filter. If an L filter is operated at the same clock rate as the original filter, L output samples are generated every clock cycle compared to the single output sample that is produced every clock cycle in the original filter. This implies that the L- filter effectively operates at L times the rate of the original FIR filter. The architecture for DWT is done for DB4 wavelet. The function of decomposition and reconstruction for the wavelet is checked using MATLAB editor@iaeme.com

4 M. Vijay Albert William, D. Balaji and K. Bhaskar 7. PROGRAM LOGICFOR XILINX11.4 Clearall Closeall clc Loadleleccum s=leleccum(1:3920); Plot (s) // Shown in figure 1 l=length(s); [ca1,cd1]=dwt(s,'db1'); a1=upcoef('a', ca1,'db1',1, l); Figure Plot (a1)// shown in figure 2 d1=upcoef('d',cd1,'db1',1,l); Figure Plot (d1)// shown in figure Figure 1 Input signal Figure 2 Denoised signal Figure 3 Noise present in the signal editor@iaeme.com

5 High-Speed VLSI Implementation Systematic Scheme for DWT Wave Scope Sy stem Generator Resource Estimator WaveScope Noisy.wav To Wave File out Counter addrz -1 ROM In Gateway In Out1 In1Out1 Out2 In2Out2 In1 Out3 In3Out3 Out4 In4Out4 Analysis filters Down samplers In1 Out1 In2 In3 Out2 In4 Interleaver In1Out1 Denoising Out1 In1 Out2 Out3 In2 Out4 In1Out1 In2Out2 In3Out3 In4Out4 In1Out1 In2Out2 In3Out3 In4Out4 Deinterleaver Up samplers by 4 synthesis filters In1 In2 Out1 In3 In4 Adder Out Gateway Out4 Scope4 Denoised.wav To Wave File1 Figure 4 Proposed DWT structure based on FIR filter 8. HARDWARE DETAILS The vital step in designing implementation is to take a working model h/w coding with the use of VHDL RTL. Ideal design is checked based on analysing the result attained from the VHDL RTL with an output cummulated from the standard point of itreations. Output waveforms in the MATLAB & VHDL RTL design are graphically drawn and verified its functions for their operation. Architecture implemented in the past had several design issues. That includes huge critical path delay in cascaded finite impulse responce filters, due to poor hardware usuage and the application of redundant filters with level two & greater and in effective power dissipation will loss every alternate calculatins observed at the output of the deceremental filters. While Addressing these inefficient and developing design of analysis method helps us to increase their performance analysis. The verified output architecture can be by applied with a combination of various filter optimizations methods that will use as a basic design to get better hardware functionality, and by thus its reduction critical path and better power utilization algorithims. In the below hardware performance steps will assist in improving the hardware architecture. 9. RESULTS AND SYNTHESISREPORT: In this proposal the results were obtained by analysying and synthesizing the implementations presented in our earlier discussion. The optimizations performance of discrete wavelet transform design of synthesesis were analysed. The architectures are compared with respect to resources available, with design output, power transformed and the hardware parameters delay. Our discussions can be categeoried into 4 sub categeories. our first categeory on how to select the computational accuracy required in implementing design in the hardware. And the next categeory will explain the experimental analysis setup and the tools used in calculating the area, in the throughput and the power for the designs. Final results obtained from the synthezis and analysed. And all the results were selected an implementation that will perform well in terms of area, power, output and latency. 10. DAUBACHIES- FOUR TAP WAVELET FILTER Consider the Daubachies-4 tap wavelet FIR filters. The filter coefficients of low-pass filter are shown in Table 6.1. To get whole number values of co efficients, they will be multiplied by 100 and approximated. The coefficient values obtained are h (0) =48, h (1) =84, h (2) =22, h (3) =13. And the high pass filter co efficients can be obtained from the low pass coefficients editor@iaeme.com

6 M. Vijay Albert William, D. Balaji and K. Bhaskar from the property of orthogonality and orthonormality. The relation between low pass filter and high pass filter coefficients were given by g (k) = (-1) kh(n-1-k) where N is the number of coefficients. The high pass coefficients are shown in Table 6.2 with their corresponding approximations. The two s complement of both the high pass filter co efficient and low pass filter co efficients are shown in Table 6.3. Table 1 Lowpass filter coefficients Coefficients Values Approx.values Variable h(0) a h(1) b h(2) c h(3) d Table 2 Highpass filter coefficients Coefficients Values Approx.values Variable g(0) E g(1) f g(2) g g(3) h Table 3 2 S complement representation of filter coefficients Variable Value 2 s complement a b c BIT PRECISION It will Analysis the effects on fixed point of precision on the combined value of output signals in its pre requisite to Verilog hardware model implementation of discrete wavelet transform design. The fix point outputs results by using different length word sizes on the inputs & filter coefficients to floating point of the model of discrete wavelet transform algorithm were compared and cross checked. The error calculation metrics were used in comparison to Mean Square Error & Peak Absolute Error which were defined as in Equation 6.1. [ ] [ ] Where y [n] and y [n] were floating point numbes and fixed point numbers. The maximum values for y [n] and y [n] are y max and y max respectively. Then K is the sequence length. The MSE is mean of cumulative squared value error between the floating number and fixed point numbers and PAE is in the difference between the absolute maximum floating and fixed point numbers. These metrics help us assess the impact of scaling on the floating point numbers. Use quantized signals as the input signal to test quality and measure the effects of scaling. Table 6.1 summarizes the quantization errors for N = 8, 12 and 16-bit input and coefficient word sizes. From Table II, observe that the error metrics improved for higher bit precision but at the cost of increased resource utilization and power consumption editor@iaeme.com

7 High-Speed VLSI Implementation Systematic Scheme for DWT Table 4 Quantization Results for Fixed-Point DWT Implementation Input Coefficient bits Output bits PAE MSE * * * * * * SYNTHESIS RESULTS The implementation is done in VHDL HDL and logic simulation is done in ModelSim Simulator 6.2 and the synthesis is done using XILINX11.4 The disadvantage of proposed architecture is that due to the increased delay elements power dissipation increases, but it is overcome by reducing the number of multipliers and address there by reducing its consumed power. Table 5 Synthesis ReportofAreaUtilizationofDWTBasedOn2 FIRFilter Resource Used Available Utilization Input/output % LogicElements % DSPBlock % FIR filters which are mainly composed of subfilters, when directly implemented for DWT are mostly found to be inefficient, but in the proposed architecture have successfully made the subfilter share so as to reduce hardware and increase efficiency. Table 6 Synthesis Report Timing Analyser Details ofdwtbasedon2firfilter Type Worstcasetdp Actual Timing ns Table 7 Comparison of Proposed Architecture with Other Architectures DWT ClkFrequency Worstcasetdp Power Proposed Architecture MHz ns 26.7mW Lifting 90MHz 66ns 23mW Conventional Convolution 42MHz 35ns 32mW Pipelined Architecture 63MHz 56ns 37mW Figure 8 Comparison of the Proposed Architecture with Other Existing Architectures editor@iaeme.com

8 M. Vijay Albert William, D. Balaji and K. Bhaskar Figure 2 RTL Netlist Output 13. RESULT & SYNTHESIS REPORT In this paper the results obtained by synthesizing the implementations presented. The impact on optimizations and the performance of the discrete wavelet transform design in synthesizing were analysed. Architectures are compared with available resource utilization methods, design output and power dissipated with hardware latency. This paper is divided as 4 sections. In the first section we will discuss on how to select the computational accuracy required in implementing hardware design. The next section describes the experimental setup and tools used to calculate the area, throughput and power for the designs. Then present the results obtained from the synthesis and analyse the results to select an implementation that performs well in terms of area, power, throughput and latency. 14. DAUBACHIES- FOUR TAP WAVELET FILTER Consider the Daubachies-4 tap wavelet FIR filters. The filter coefficients of low-pass filter are shown in Table 6.1. In order to get the whole number values of coefficients, they are multiplied by 100 and approximated. The coefficient values obtained are h(0)=48, h(1)=84, h(2)=22, h(3)=13. The high-pass filter coefficients can be obtained from the low pass coefficients from the property of orthogonality and orthonormality. The relationship between low pass and high pass filter coefficients is given by g (k) = (-1) kh(n-1-k) where N is the number of coefficients. The high pass coefficients are shown in Table 6.2 with their corresponding approximations. The two s complement of both the high pass and low pass filter coefficients are shown in Table 6.3. Table 8 Lowpass filter coefficients Coefficients Values Approx.values Variable h(0) a h(1) b h(2) c h(3) d editor@iaeme.com

9 High-Speed VLSI Implementation Systematic Scheme for DWT Table 9 Highpass filter coefficients Coefficients Values Approx.values Variable g(0) E g(1) f g(2) g g(3) h Table 10 2 S complement representation of filter coefficients Variable Value 2 s complement a b c BIT PRECISION Analysis of the effects of fixed point precision on the integrity of the output signals is a prerequisite to the Verilog hardware implementation of the DWT design. The fixed point outputs using different word sizes for the inputs and filter coefficients to the floating point model of the DWT algorithm was compared. The error metrics used for comparison are Mean Square Error (MSE) and Peak Absolute Error (PAE) which are defined in Equation 6.1. [ ] [ ] Where y[n] and y [n] are the floating point and fixed point numbers respectively. The maximum values for y[n] and y [n] are ymax and y max respectively and K is the sequence length. The MSE is the mean of the cumulative squared error between the floating and fixed point numbers and PAE is the difference between the absolute maximum floating and fixed point numbers. These metrics help us assess the impact of scaling on the floating point numbers. Use quantized signals as the input signal to test quality and measure the effects of scaling. Table 6.1 summarizes the quantization errors for N = 8, 12 and 16-bit input and coefficient word sizes. From Table II, observe that the error metrics improved for higher bit precision but at the cost of increased resource utilization and power consumption. Table 11 Quantization Results for Fixed-Point DWT Implementation Input Coefficient bits Output bits PAE MSE * * * * * * CONCLUSIONS In this paper, the performance of the DWT design architectures were analyzed and compared the performance results of the architectures with respect to resource utilization, power, and area utilization. Finally it is concluded that the design tradeoffs which make the design flexible depending on the application needs in the attempt to create an architecture that is efficient in terms of area, power, latency and throughput. The results displayed were obtained by synthesizing these designs onto a Xilinx system generator Other FPGAs results in different performance results. However, the method used to develop a design that performed editor@iaeme.com

10 M. Vijay Albert William, D. Balaji and K. Bhaskar well can be applied to different FPGAs.A systematic scheme for high-speed VLSI implementation of DWT is presented in this paper. Hardware efficient FIR filter structures are developed to speed up the processing speed of DWT and to control the increase of hardware cost at the same time. The proposed design can be easily extended to achieve higher processing speed than the given highest processing speed with computing time N 2 /12 in this paper. The proposed design is suitable for high-speed VLSI implementation of DWT because of its regular structure, simple control and 100% hardware utilization for continuous images. Using the proposed first-level non-separable DWT structures can get proposed non-separable DWT structure with higher resolution levels. For this an interleaving filtering could be employed which is a pair of DEMUX and MUX used switch to next channel i when the i th level of DWT is being computed. Proposed design can also be used to implement DWT suitable for lifting or Flipping based implementation schemes. REFERENCES [1] Christian Tenllado, Javier Setoain, Manuel Prieto, Luis Pinuel, Francisco Tirado (2008), Parallel Implementation of the Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting, IEEE Transactions on parallel and distributed systems, vol. 19, no. 3, pp [2] T. Acharya and C. Chakrabarti(2006), A survey on lifting-based discrete wavelet transform, J. VLSI Signal Process., vol. 42, no. 3, pp [3] C. Y. Xiong, J. W. Tian, and J. Liu (2006), A note on Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transforms, IEEE Trans. Signal Process., vol. 54, no. 5, pp [4] C. T. Huang, P. C. Tseng, and L. G. Chen (2004), Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform, IEEE Trans. Signal Process., vol. 52, no. 4, pp [5] C. Cheng and K. K. Parhi(2004), Hardware efficient fast parallel FIR filter structures based on iterated short convolution, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 51, no. 8, pp [6] Chao Cheng, and Keshab K. Parhi(2004), Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution, IEEE Transactions On Circuits And Systems I: Regular Papers, Vol. 51, No. 8. [7] Q. Dai, X. Chen, and C. Lin(2004), A novel VLSI architecture for multidimensional discrete wavelet transform,ieee Trans. Circuits Syst. Video Technol., vol. 14, no. 8, pp [8] H. Liao, M. K. Mandal, and B. F. Cockburn (2004), Efficient architectures for and liftingbased wavelet transform, IEEE Trans. Signal Process. vol. 52, no. 5, pp [9] Ramsey Hourani, IshitaDalal, W. Rhett Davis, Christopher Doss, Winser Alexander(2003), An Efficient VLSI Implementation for the 1D Convolutional Discrete Wavelet Transform, Design, Automation and Test in Europe Conference and Exhibition, vol. 2, pp [10] J. G. Chung and K. K. Parhi(2002), Frequency-spectrum-based low-area low-power parallel FIR filter design, EURASIP J. Appl. Signal Process., vol. 2002, no. 9, pp [11] K. Andra, C. Chakrabarti, and T. Acharya(2002), A VLSI architecture for lifting-based forward and inverse wavelet transform, IEEE Trans. Signal Process., vol. 50, no. 4, pp editor@iaeme.com

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