Six-Channel Digital Isolator

Transcription

1 Click here for production status of specific part numbers. General Description The is a six-channel digital isolator utilizing Maxim s proprietary process technology, whose monolithic design provides a compact and low-cost transfer of digital signals between circuits with different power domains. The technology enables low power consumption and high channel density. The four unidirectional channels are each capable of DC to Mbps, with two of the four channels passing data across the isolation barrier in each direction. The two bidirectional channels are open-drain, each capable of data rates from DC to Mbps. Independent 3.V to.v supplies on each side of the isolator also make it suitable for use as a level translator. The can be used for isolating SPI buses, IC buses, RS-3, RS-/RS- buses, and general-purpose isolation. When used as a bus isolator, extra channels are available for power monitoring and reset signals. The is available in a -pin QSOP (3.9mm x.9mm) package. The device is specified over the - C to + C temperature range. Applications Industrial Control Systems IC, SPI, SMBus, PMBus Interfaces Isolated RS-3, RS-/RS- Telecommunication Systems Battery Management Medical Systems Benefits and Features Complete Digital Isolation Solution V RMS Isolation for Seconds Short-Circuit Protection on Unidirectional Outputs V RMS Working Isolation Voltage Four Unidirectional Signal Paths: -In/-Out Two Bidirectional Open-Drain Signal Paths Mbps (max) Unidirectional Data Rate Mbps (max) Bidirectional Data Rate Compatible with Many Interface Standards IC SPI RS-3, RS-/RS- SMBus, PMBus Interfaces Ordering Information appears at end of data sheet. Functional Diagram INA INA OUTA V CCA OUTB OUTB INB OUTA V RMS DIGITAL ISOLATOR INB I/OA I/OB I/OA I/OB PMBus is a trademark of SMIF, Inc. 9-; Rev ; /7

2 Absolute Maximum Ratings V CCA to...-.3v to +V to...-.3v to +V OUTA, OUTA to V to (V CCA +.3V) OUTB, OUTB to V to ( +.3V) INA, INA to...-.3v to +V I/OA, I/OA to V to (V CCA +.3V) INB, INB, I/OB, I/OB to...-.3v to +V OUTA, OUTA, OUTB, OUTB Continuous Current...±3mA I/OA, I/OA Continuous Current...±3mA Package Thermal Characteristics (Note ) QSOP Junction-to-Ambient Thermal Resistance (θ JA ) C/W Junction-to-Case Thermal Resistance (θ JC )...37 C/W I/OB, I/OB Continuous Current...±mA Continuous Power Dissipation (T A = +7 C) QSOP (derate 9.mW/ C above +7 C)...77.mW Junction Temperature...+ C Storage Temperature Range... - C to + C Lead Temperature (soldering, s)...+3 C Note : Package thermal resistances were obtained using the method described in JEDEC specification JESD-7, using a four-layer board. For detailed information on package thermal considerations, refer to Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (V CCA - V = 3.V to.v, - V = 3.V to.v, T A = - C to + C, unless otherwise noted. Typical values are at V CCA - V = 3.3V, - V = 3.3V, and T A = + C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT VOLTAGE SUPPLY Supply Voltage Supply Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis V CCA Relative to 3.. Relative to 3.. I CCA, I CCB All inputs static at GND_ or VCC_. No load. All inputs switching (INA_, INB_ at Mbps and I/OA_ at Mbps). No load. (Note 3) V CCA = +V.9 = +V 3.. V CCA = +3.3V 3.. = +3.3V 3.. V CCA = +V.. = +V. 9. V CCA = +3.3V. 7. = +3.3V..7 V UVLO_ V CC_ rising (Note )... V V UVLOHYS (Note ) mv V ma Maxim Integrated

3 DC Electrical Characteristics (continued) (V CCA - V = 3.V to.v, - V = 3.V to.v, T A = - C to + C, unless otherwise noted. Typical values are at V CCA - V = 3.3V, - V = 3.3V, and T A = + C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT UNIDIRECTIONAL LOGIC INPUTS AND OUTPUTS (INA_, INB_, OUTA_, OUTB_) Input Logic-High Voltage V IH INA_ relative to INB_ relative to.7 x V CCA.7 x V INA_ relative to. Input Logic-Low Voltage V IL INB_ relative to. INA_ relative to. Input Hysteresis V HYST INB_ relative to. Input Leakage Current I L INA_/INB_ = or V CC_ - + µa Input Capacitance C IN INA_, INB_, f = MHz pf Output Logic-High Voltage Output Logic-Low Voltage V OH OUTA_ relative to, source current = ma OUTB_ relative to, source current = ma V CCA OUTA_ relative to, sink current = ma. V OL OUTB_ relative to, sink current = ma. BIDIRECTIONAL LOGIC INPUTS AND OUTPUTS (I/OA_, I/OB_) Input Threshold Voltage V IT I/OA_ relative to..7 V Input Logic-High Voltage V IH I/OA_ relative to.7 I/OB_ relative to. x Input Logic-Low Voltage V IL I/OA_ relative to. Input/Output Logic-Low Threshold Difference V TOL I/OB_ relative to I/OA_ relative to,.ma I OUT 3.mA sink current (Note ) I/OA_ relative to 7 Input Hysteresis V HYST I/OB_ relative to.3 x mv I/OA_ = V CCA - + Input Leakage Current I L I/OB_ = - + Output Logic-Low Voltage V OL I/OA_ relative to,.ma I OUT 3.mA sink current.. I/OB_ relative to, I OUT = 3mA sink current. V V V V V V mv µa V Maxim Integrated 3

4 Switching Electrical Characteristics (V CCA - V = 3.V to.v, - V = 3.V to.v, T A = - C to + C, unless otherwise noted. Typical values are at V CCA - V = 3.3V, - V = 3.3V, and T A = + C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Common-Mode Transient Immunity CMTI V IN_, I/O_ = V CC _ or V GND _ (Note 7) 3. kv/µs UNIDIRECTIONAL DYNAMIC SWITCHING CHARACTERISTICS (INA_, INB_, OUTA_, OUTB_) Maximum Data Rate DR MAX INA_ to OUTB_, INB_ to OUTA_ Mbps Minimum Pulse Width PW MIN INA_ to OUTB_, INB_ to OUTA_ ns Propagation Delay.V V CC_.V.. t DPLH INA_ to OUTB_, INB_ to OUTA_, R L = MΩ, C L 3.V V 3.V CC_. 3.3 t DPHL = pf, Figure.V V CC_.V.3. 3.V V CC_ 3.V. 3. ns Pulse-Width Distortion t DPLH t DPHL PWD INA_ to OUTB_, INB_ TO OUTA_, R L = MΩ, C L = pf, Figure (Note ).V V CC_.V.9 3.V V CC_ 3.V. ns Channel-to-Channel Skew t DSKEWCC OUTB to OUTB output skew, Figure (Note ) OUTA to OUTA output skew, Figure (Notes ) ns Part-to-Part Skew t DSKEWPP t DPLH, t DPHL (Note ) ns Rise Time t R OUTA_, OUTB_, % to 9%, C L = pf, Figure Fall Time t F OUTA_, OUTB_, 9% to %, C L = pf, Figure ns Maxim Integrated

5 Switching Electrical Characteristics (continued) (V CCA - V = 3.V to.v, - V = 3.V to.v, T A = - C to + C, unless otherwise noted. Typical values are at V CCA - V = 3.3V, - V = 3.3V, and T A = + C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT BIDIRECTIONAL DYNAMIC SWITCHING CHARACTERISTICS (I/OA_, I/OB_) Maximum Data Rate DR MAX I/OA_ to I/OB_, I/OB_ to I/OA_ Mbps tplhab I/OA_ =.V to I/OB_ =.7 x VCCB, C A = C B = pf, Figure.V V CC_.V, R A = 3W, R B = 3W 3.V V CC_ 3.V, R A = 93W, R B = 9.3W Propagation Delay tphlab tplhba I/OA_ =.V to I/OB_ =.V, C A = C B = pf, Figure I/OB_ =.V x VCCB to I/OA_ =.7 x VCCA, C A = C B = pf, Figure.V V CC_.V, R A = 3W, R B = 3W 3.V V CC_ 3.V, R A = 93W, R B = 9.3W.V V CC_.V, R A = 3W, R B = 3W 3.V V CC_ 3.V, R A = 93W, R B = 9.3W ns tphlba I/OB_ =.3V x VCCB to I/OA_ =.9V, C A = C B = pf, Figure.V V CC_.V, R A = 3W, R B = 3W 3.V V CC_ 3.V, R A = 93W, R B = 9.3W Pulse-Width Distortion PWDAB PWDBA t PLHAB t PHLAB (Note ) t PLHBA t PHLBA (Note ).V V CC_.V. 3.V V CC_ 3.V..V V CC_.V 3. 3.V V CC_ 3.V 37. ns Maxim Integrated

6 Switching Electrical Characteristics (continued) (V CCA - V = 3.V to.v, - V = 3.V to.v, T A = - C to + C, unless otherwise noted. Typical values are at V CCA - V = 3.3V, - V = 3.3V, and T A = + C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT t FA I/OA_ =.7 x V CCA to.3 x V CCA, C A = pf, Figure.V V CC_.V, R A = 3W 3.V V CC_ 3.V, R A = 93W Fall Time t FB t FA I/OB_ =.7 x to.3 x, C B = pf, Figure I/OA_ =.9 x V CCA to 9mV, C A = pf Figure.V V CC_.V, R B = 3W 3.V V CC_ 3.V, R B = 9.3W.V V CC_.V, R A = 3W 3.V V CC_ 3.V, R A = 93W ns t FB I/OB_ =.9 x to mv, C B = pf, Figure.V V CC_.V, R B = 3W 3.V V CC_ 3.V, R B = 9.3W Note : All units are production tested at T A = + C. Specifications over temperature are guaranteed by design. All voltages of side A are referenced to. All voltages of side B are referenced to, unless otherwise noted. Note 3: Guaranteed by design. Not production tested. Note : The undervoltage lockout threshold and hysteresis guarantee that the outputs are in a known state during a slump in the supplies. See the Detailed Description section for more information. Note : ΔV TOL = V OL V IL. This is the minimum difference between the output logic-low voltage and the input logic threshold for the same I/O pin. This ensures that the I/O channels are not latched low when any of the I/O inputs are driven low (see the Bidirectional Channels section). Note : CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to both rising and falling common-mode voltage edges. Tested with the transient generator connected between and. Note 7: Pulse-width distortion is defined as the difference in propagation delay between low-to-high and high-to-low transitions on the same channel. Channel-to-channel skew is defined as the difference in propagation delay between different channels on the same device. Part-to-part skew is defined as the difference in propagation delays (for unidirectional channels) between different devices, when both devices operate with the same supply voltage, at the same temperature and have identical package and test circuits. ESD Protection PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ESD Human Body Model, all pins ± kv Maxim Integrated

7 Insulation and Safety Characteristics PARAMETER SYMBOL CONDITIONS VALUE UNIT Maximum Repetitive Peak Isolation Voltage Maximum Working Isolation Voltage Maximum Transient Isolation Voltage Maximum Withstand Isolation Voltage V IORM (Note ) V P V IOWM Continuous RMS voltage (Note ) V RMS V IOTM t = s V P V ISO f SW = Hz, duration = s (Notes, 9) V RMS Maximum Surge Isolation Voltage V IOSM Basic insulation,./µs pulse per IEC -- kv Insulation Resistance R S T A = ºC, V IO = V > 9 Ω Barrier Capacitance Side A to Side B C IO f SW = MHz (Note) pf External Tracking (Creepage) CPG QSOP 3. mm External Air Gap (Clearance) CLR QSOP 3. mm Internal Clearance Distance through insulation. mm Comparative Tracking Index CTI Material Group II (IEC ) > V Climatic Category // Pollution Degree (DIN VDE, Table ) Note : V ISO, V IOWM, and V IORM are defined by the IEC 77-- standard. Note 9 Product is qualified at V ISO for s and % production tested at % of V ISO for s. Note : Capacitance is measured with all pins on the field-side and logic-side tied together. Maxim Integrated 7

8 Test Circuits/Timing Diagrams VCCA INA, INA % % VCCA.µF VCCA VCCB.µF VCCB tdplh tdphl VCCB Ω OUTB % % INA_ OUTB_ TEST SOURCE CL RL tdskewcc VCCB 9% tdskewcc OUTB % % (A) % tr tf (B) Figure. Test Circuit (A) and Timing Diagram (B) for Unidirectional Channels V CCA R.µF V CCA.µF R I/OA_ I/OB_ C L C L TEST SOURCE (A) V CCA I/OA, I/OA % % I/OB, I/OB % % t DPLH t DPLH t DPHL t DPHL V CCA I/OB % % I/OA % % V OL (min) V OL (min) 9% V CCA 9% I/OB I/OA V OL (min) t F % V OL (min) t F % (B) (C) Figure. Test Circuit (A) and Timing Diagrams (B) and (C) for Bidirectional Channels Maxim Integrated

9 Typical Operating Characteristics (V CCA V = 3.3V, V = 3.3V, all inputs idle, T A = + C, unless otherwise noted.) ICCA (ma) ICCA vs DATA RATE OUTA_/OUTB_ NOT CONNECTED TO PCB INA and INA Switching... DATA RATE (MHz) INB and INB Switching toc ICCB (ma) ICCB vs DATA RATE OUTA_/OUTB_ NOT CONNECTED TO PCB INB and INB Switching... DATA RATE (MHz) INA and INA Switching toc ICCA (ma) ICCA vs DATA RATE I/OB and I/OB Switching I/OA and I/OA Switching kω PULLUPS ON I/OA_ AND I/OB_... DATA RATE (MHz) toc3 9 ICCB vs DATA RATE toc 7 ICCA vs VCCA toc 7 ICCB vs VCCB toc 7 I/OA and I/OA Switching T A = +ºC T A = +ºC T A = +ºC ICCB (ma) 3 I/OB and I/OB Switching kω PULLUPS ON I/OA_ AND I/OB_... DATA RATE (MHz) I CCA (ma) 3 T T A = -ºC A = +ºC V CCA (V) I CCB (ma) 3 T A = -ºC (V) 7 ICC vs TEMPERATURE toc7. OUTA_ V OH vs SOURCE CURRENT toc. OUTA_ V OL vs SINK CURRENT toc9 SUPPLY CURRENT (ma) 3 ICCA ICCB OUTA_ V OH (V) V CCA = 3.3V V CCA = V OUTA_ V OL (V) V CCA = 3.3V V CCA = V TEMPERATURE (ºC) I SOURCE (ma) I SINK (ma) Maxim Integrated 9

10 Typical Operating Characteristics (continued) (V CCA V = 3.3V, V = 3.3V, all inputs idle, T A = + C, unless otherwise noted.) OUTB_ V OH (V) OUTB_ V OH vs SOURCE CURRENT = V = 3.3V. 3 I SOURCE (ma) toc OUTB_ V OL (V) OUTB_ V OL vs SINK CURRENT = 3.3V. 3 I SINK (ma) = V toc vs SUPPLY VOLTAGE V -V = -V V -V = V V -V = +V V CCA = INA_ to OUTB_ LOW TO HIGH TRANSITION V CCA (V) toc vs SUPPLY VOLTAGE V -V = V V -V = -V V -V = +V V CCA = INA_ to OUTB_ HIGH TO LOW TRANSITION V CCA (V) toc3 vs. CAPACITIVE LOAD INA_ TO OUTB_ C L (pf) LOW TO HIGH HIGH TO LOW toc vs. TEMPERATURE LOW TO HIGH INA_ TO OUTB_ TEMPERATURE (ºC) HIGH TO LOW toc vs. SUPPLY VOLTAGE V -V = +V V -V = V V CCA (V) V -V = -V toc V CCA = INB_ TO OUTA_ LOW TO HIGH TRANSITION vs. SUPPLY VOLTAGE V -V = -V V -V = V V -V = +V V CCA (V) toc7 V CCA = INB_ TO OUTA_ HIGH TO LOW TRANSITION vs. CAPACITIVE LOAD HIGH TO LOW LOW TO HIGH INB_ TO OUTA_ C L (pf) toc Maxim Integrated

11 Typical Operating Characteristics (continued) (V CCA V = 3.3V, V = 3.3V, all inputs idle, T A = + C, unless otherwise noted.) vs. TEMPERATURE HIGH TO LOW LOW TO HIGH INB_ TO OUTA_ TEMPERATURE (ºC) toc vs. SUPPLY VOLTAGE V CCA = I/OA_ TO I/OB_ LOW TO HIGH TRANSITION PULLUP = kω V -V = V V -V = +V V -V = -V V CCA (V) toc 9 7 vs. SUPPLY VOLTAGE V CCA = I/OA_ TO I/OB_ HIGH TO LOW TRANSITION PULLUP = kω V -V = V V CCA (V) toc V -V = +V V -V = -V 9 7 vs. TEMPERATURE HIGH TO LOW LOW TO HIGH 3 I/OA_ TO I/OB_ PULLUP = kω _ TEMPERATURE (ºC) toc 9 7 vs. SUPPLY VOLTAGE V CCA = I/OB_ TO I/OA_ LOW TO HIGH TRANSITION PULLUP = kω V -V = V V -V = +V V CCA (V) V -V = -V toc vs. SUPPLY VOLTAGE V CCA = I/OB_ TO I/OA_ HIGH TO LOW TRANSITION PULLUP = kω V -V = V V CCA (V) V -V = -V V -V = +V toc 9 vs. TEMPERATURE toc OUTA EYE DIAGRAM (V - V = V) toc OUTA EYE DIAGRAM (V - V = ±3VAC) toc7 7 HIGH TO LOW LOW TO HIGH 3 I/OB_ TO I/OA_ PULLUP = kω _ ns/div OUTA V/div V - 3V/div V ns/div OUTA V/div V - 3V/div V TEMPERATURE (ºC) Maxim Integrated

12 Pin Configuration TOP VIEW V CCA + INA OUTB INA OUTA 3 3 OUTB INB OUTA INB I/OA I/OB I/OA 7 I/OB 9 QSOP Pin Description PIN NAME FUNCTION REFERENCE Supply Voltage of Logic Side A. Bypass V V CCA with a.µf ceramic CCA capacitor to. INA Logic Input on Side A. INA is translated to OUTB. 3 INA Logic Input on Side A. INA is translated to OUTB. OUTA Logic Output on Side A. OUTA is a push-pull output. OUTA Logic Output on Side A. OUTA is a push-pull output. I/OA Bidirectional Input/Output on Side A. I/OA is translated to/from I/OB and is an open-drain output. 7 I/OA Bidirectional Input/Output on Side A. I/OA is translated to/from I/OB and is an open-drain output. Ground Reference for Side A 9 Ground Reference for Side B I/OB Bidirectional Input/Output on Side B. I/OB is translated to/from I/OA and is an open-drain output. I/OB Bidirectional Input/Output on Side B. I/OB is translated to/from I/OA and is an open-drain output. INB Logic Input on Side B. INB is translated to OUTA. 3 INB Logic Input on Side B. INB is translated to OUTA. OUTB Logic Output on Side B. OUTB is a push-pull output. OUTB Logic Output on Side B. OUTB is a push-pull output. Supply Voltage of Logic Side B. Bypass V with a.µf ceramic CCB capacitor to. Maxim Integrated

13 Detailed Description The is a six-channel digital isolator. The device is rated for V RMS isolation voltage for seconds. This digital isolator offers a low power, lowcost, and high electromagnetic interference (EMI) immunity through Maxim s proprietary process technology. The device uses a monolithic solution to isolate different ground domains and block high-voltage/high-current transients from sensitive or human interface circuitry. Four of the six channels are unidirectional, two in each direction. All four unidirectional channels support data rates of up to Mbps. The other two channels are bidirectional with data rates up to Mbps. Isolation of IC, SPI/MICROWIRE, and other serial busses can be achieved with the. The device features two supply inputs, V CCA and, that independently set the logic levels on either side of the device. V CCA and are referenced to and, respectively. The also features a refresh circuit to ensure output accuracy when an input remains in the same state indefinitely. Digital Isolation The provides galvanic isolation for digital signals that are transmitted between two ground domains. Up to V RMS of continuous isolation is supported as well as transient differences of up to V. Level Shifting In addition to isolation, the can be used for level translation. V CCA and can be independently set to any voltage from 3.V to.v. The supply voltage sets the logic level on the corresponding side of the isolator. Unidirectional and Bidirectional Channels The operates both as a unidirectional device and bidirectional device simultaneously. Each unidirectional channel can only be used in the direction shown in the functional diagram. The bidirectional channels function without requiring a direction control input. Unidirectional Channels The device features four unidirectional channels that operate independently with guaranteed data rates from DC to Mbps. The output driver of each unidirectional channel is push-pull, eliminating the need for pullup resistors. The outputs are able to drive both TTL and CMOS logic inputs. Bidirectional Channels The device features two bidirectional channels that have open-drain outputs. The bidirectional channels do not require a direction control input. A logic-low on one side causes the corresponding pin on the other side to be pulled low while avoiding data latching within the device. The input logic-low thresholds (V IT ) of I/OA and I/OA are at least mv lower than the output logic-low voltages of I/OA and I/OA. This prevents an output logic-low on side A from being accepted as an input low and subsequently transmitted to side B, thus preventing a latching action. The I/OA, I/OA, I/OB, and I/OB pins have open-drain outputs, requiring pullup resistors to their respective supplies for logic-high outputs. The output low voltages are guaranteed for sink currents of up to 3mA for side B, and 3.mA for side A (see the DC Electrical Characteristics table). Startup and Undervoltage Lockout The V CCA and supplies are both internally monitored for undervoltage conditions. Undervoltage events can occur during power-up, power-down, or during normal operation due to a slump in the supplies. When an undervoltage event is detected on either of the supplies, all outputs on both sides are automatically controlled, regardless of the status of the inputs (Table ). The bidirectional outputs become high impedance and are pulled high by the external pullup resistor on the open-drain output. The unidirectional outputs are pulled high internally to the voltage of the V CCA or supply during undervoltage conditions. Table. Output Behavior During Undervoltage Conditions V IN V CCA V OUTA_ V OUTB_ Powered Powered Powered Powered X Under Voltage Powered Follows V CCA X Powered Under Voltage Follows Maxim Integrated 3

14 Figure 3 shows an example of the behavior of the outputs during power-up and power-down. This behavior is symmetrical for V CCA and rising/falling. Safety Regulatory Approvals The AEE+ is safety certified by UL. Per UL77, the is % tested at an equivalent V ISO of 7V RMS for one second (see Table ). Applications Information Effect of Continuous Isolation on Lifetime High-voltage conditions cause insulation to degrade over time. Higher voltages result in faster degradation. Even the high-quality insulating material used in the can degrade over long periods of time with a constant high-voltage across the isolation barrier. Figure shows the life expectancy of the vs. working isolation voltage. Power Supply Sequencing The does not require special power-supply sequencing. The logic levels are set independently on either side by V CCA and. Each supply can be present over the entire specified range regardless of the level or presence of the other. Power Supply Decoupling To reduce ripple and the chance of introducing data errors, bypass V CCA and with.µf ceramic capacitors to and, respectively. Place the bypass capacitors as close to the power-supply input pins as possible. Table. Safety Regulatory Approvals SAFETY AGENCY STANDARD ISOLATION NUMBER FILE NUMBER UL UL77 Recognized V RMS isolation voltage for seconds E379 LIFE EXPECTANCY vs. WORKING ISOLATION VOLTAGE V/div VCCA VCCB OUTA_ OUTB_ I/OA_ I/OB_ WORKING LIFE - YEARS (LOG SCALE). V IOWM = V RMS µs/div. 3 7 WORKING ISOLATION VOLTAGE (V IOWM) - V RMS Figure 3. Undervoltage Lockout Behavior Figure. Life Expectancy vs. Working Isolation Voltage Maxim Integrated

15 Calculating Power Dissipation The dissipates power based on the switching data rate of the input and output channels, and loads on the channel outputs. The required current for a given supply (V CCA or ) can be estimated by summing the current required for each channel. The supply current for a channel depends on whether the channel is an input or an output, the channel s data rate, and the capacitive or resistive load, if it is an output. The typical current for an input or output at any data rate can be estimated from the graphs in Figure and Figure. Please note the data in Figure and Figure are extrapolated from the supply current measurements in a typical operating condition. The total current for a single channel is the sum of the no load current (shown in Figure and Figure ) which is a function of Voltage and Data Rate, and the load current which depends upon the type of load. Current into a capacitive load is a function of the load capacitance, the switching frequency, and the supply voltage. where I CL = CL f SW V CC I CL is the current required to drive the capacitive load. CL is the load capacitance on the isolator s output pin. f SW is the switching frequency (bits per second / ). V CC is the supply voltage on the output side of the isolator. Current into a resistive load depends on the load resistance, the supply voltage and the average duty cycle of the data waveform. The DC load current can be conservatively estimated by assuming the output is always high. where I RL = V CC / RL I RL is the current required to drive the resistive load. V CC is the supply voltage on the output side of the isolator. RL is the load resistance on the isolator s output pin. The required supply current for switching bidirectional open-drain inputs/outputs is negligible, and can be ignored when calculating power dissipation. Some current, however, will be pulled from the supply through the pull-up resistors on those pins. To calculate that current under worst-case conditions, assume that the I/O is always low and calculate the current as: where IIO = VCC / RPU I IO is the current through the pull-up resistor. V CC is the supply voltage on the side of the bidirectional input/output. RPU is the pull-up resistance on the input/output. Example (shown in Figure 7): A is operating with V CCA = 3.3V, = V. The bidirectional channels (I/O_ and I/O_), in this application channel (SCL) and channel (SDA), implement an isolated IC Bus, operating at Fast Mode Plus (FM+) with a clock rate of MHz. As noted previously, the power dissipated in these channels during switching is negligible and will be ignored for further calculations. The other channels are unidirectional; INA is a MHz input driving an output OUTB which has a pf capactive load. INA is held low and the channel is not in use and the resistive load is negligible since the isolator is driving a CMOS input. Similarly, INB is held low and the channel is not in use and the load current from OUTA is considered negligible. INB is a MHz input driving an output OUTA which has a with a kω resistive load. Refer to Table 3 and Table for the V CCA and supply current calculation worksheets. Maxim Integrated

16 . SUPPLY CURRENT PER UNIDIRECTIONAL INPUT CHANNEL vs. DATA RATE. SUPPLY CURRENT PER UNIDIRECTIONAL OUTPUT CHANNEL vs. DATA RATE ICC_ (ma) VCC_ = 3V ICC_ (ma) CL = pf VCC_ = 3V... VCC_ = 3.3V VCC_ = V VCC_ =.V... VCC_ = 3.3V VCC_ = V VCC_ =.V DATA RATE (MHz) DATA RATE (MHz) Figure. Supply Current per Input Channel (Estimated) Figure. Supply Current per Output Channel (Estimated) Table 3. Side A Power Dissipation Calculation Worksheet SIDE A VCCA = 3.3V Channel IN/OUT Data Rate (MHz) Load Type Load No Load Current (ma) Load Current (ma) INA IN INA IN. OUTA OUT. OUTA OUT Resistive kω.33 CALCULATED POWER DISSIPATION FOR SIDE A TOTAL..33 TOTAL CURRENT.93 VCCA x ICCA = 3.3V x.93ma =.9mW Table. Side B Power Dissipation Calculation Worksheet SIDE B VCCB =.V Channel IN/OUT Data Rate (MHz) Load Type Load No Load Current (ma) Load Current (ma) OUTB OUT Capacitive pf.. OUTB OUT. INB IN. INB IN kω.3. TOTAL POWER DISSIPATION FOR SIDE B TOTAL 9.. TOTAL CURRENT. VCCB x ICCB = V x.ma = mw Maxim Integrated

17 3.3V.V Master Load on the Bus SCL pf VCCA VCCB I/OA I/OB SCL Slave Loads on the Bus pf pf MHz SDA pf I/OA I/OB SDA pf pf MHz INA INA OUTB OUTB pf OUTA INB MHz OUTA INB KΩ Figure 7. Example Circuit for Supply Current Calculation Typical Operating Circuits 3.3V 3.3V SDA VCCA VCCB I/OA I/OB SDA SCL I/OA I/OB SCL uc GPO GPO INA INA OUTB OUTB ADR ADR MAX9 DELTA-SIGMA ADC GPI GPI VCCB MONITOR OUTA OUTA INB INB RDYB ISOLATED, I C DELTA-SIGMA ADC Maxim Integrated 7

18 Typical Operating Circuits (continued) 3.3V 3.3V VCCA VCCB µc GPI CS SCLK MOSI MISO I/OA I/OB I/OA I/OB INA OUTB INA OUTB OUTA INB FAULT CS SCLK SDI SDO MAX3 THERMOCOUPLE ADC GPI OUTA INB DRDY ISOLATED, PRECISION THERMOCOUPLE TO DIGITAL CONVERTER Ordering Information PART TEMP RANGE PIN-PACKAGE AEE+ - C to + C QSOP AEE+T - C to + C QSOP +Denotes lead(pb)-free/rohs-compliant package. T = Tape and Reel Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. QSOP E Maxim Integrated

19 Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED /7 Initial release For pricing, delivery, and ordering information, please contact Maxim Direct at --9-, or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 7 Maxim Integrated Products, Inc. 9