ATLAS Silicon Detector Upgrade Project at Duke University

Transcription

1 ATLAS Silicon Detector Upgrade Project at Duke University Stefan Cafaro Department of Mechanical Engineering Pratt School of Engineering, Duke University July 25, 2012 Abstract The purpose of this paper is to provide an overview of the ATLAS Silicon Detector Upgrade Project and the role that the Duke University Physics Department plays in contributing to its completion. This document will cover the overall objectives of the upgrade project and highlight the research being done at Duke to meet the projects goals. Contents 1 What is ATLAS? 2 2 How does it work? The Inner Detector Calorimeters Muon Spectrometer Magnet System What is the purpose of the silicon detector upgrade project? 4 4 What is being upgraded? Phase Phase Phase Data Acquisition and Baseline Integration Concepts Staves and Petals Stave Hybrids Stave Modules Stavelets Super-Module Duke Research Research at CERN Research on campus The ABCn Chip Tests and Scans The Signal Intercept Card The Cosmic Ray Detector

2 LIST OF FIGURES 2 List of Figures 1 ATLAS Detector Inner Tracker Baseline Staves and Petals Stave Hybrid Serial powered stavelet Super-Module LVDS Buffer Board Duke s Hardware Setup: ABCn connected to HSIO The Block Diagram of the ABCn Chip Strobe Delay Scan Cosmic Ray Detector Background ATLAS, at the CERN Large Hadron Collider (LHC), is a general-purpose experiment designed to explore protonproton collision through the use of high collision energy and luminosity with the hope that new physics can be observed at the TeV scale. ATLAS has been constructed to fully utilize the physics potential of the collider, which includes the very recent discovery of the Higgs particle (or a particle with similar properties), as well as to search for possibilities outside the realm of the Standard Model (SM). With the LHC successfully collecting data at 7 TeV, plans are actively advancing for a series of upgrades leading to approximately five times the LHC design-luminosity some 10-years from now in the High-Luminosity LHC (HL-LHC) project. Coping with the high instantaneous and integrated luminosity will require many changes to the ATLAS detector. Designs are being rapidly developed with the goal of building a new all-silicon tracker, significantly changing the calorimeter and muon systems, as well as improving triggers. Currently at Duke University, a couple of students (including myself), directed by Dr. Mark Kruse and Dr. Ayana Arce, are conducting research in collaboration with the detector upgrade project at CERN. 1 What is ATLAS? ATLAS (A Toroidal LHC Apparatus) is one of the seven particle detector experiments (ALICE, ATLAS, CMS, TOTEM, LHCb, LHCf and MoEDAL) constructed at the Large Hadron Collider (LHC). The LHC is a relatively new particle accelerator located at the European Organization for Nuclear Research (CERN) based in Switzerland. The ATLAS experiment is designed to observe and record phenomena that involve highly massive particles which had previously been unobservable using earlier lower-energy accelerators. Many of the physicists working with this detector hope that it might one day shed light on new theories of particle physics beyond the Standard Model. ATLAS is designed as a general-purpose detector. When the proton beams produced by the Large Hadron Collider interact in the center of the detector, a variety of different particles with a broad range of energies may be produced. Rather than focusing on a particular physical process, ATLAS is designed to capture the broadest possible range of signals. This is intended to ensure that, whatever form any new physical processes or particles might take, ATLAS will be able to detect them and measure their properties. Experiments at earlier colliders, such as the Tevatron and Large Electron-Positron Collider, were designed based on a similar philosophy. However, the unique challenges of the Large Hadron Colliderits unprecedented energy and extremely high rate of collisions require ATLAS to be larger and more complex than any detector ever built. 2 How does it work? The ATLAS detector consists of a series of large concentric cylinders centered around the interaction point where the proton beams from the LHC collide. The detector can be broken up into four major parts (see Figure 1): the Inner Detector, the calorimeters, the muon spectrometer and the magnet systems. Each of these parts is comprised of multiple layers. The detectors are complementary: the Inner Detector precisely tracks particles, the calorimeters measure the energy of easily stopped particles, and the muon system makes additional measurements of highly penetrating muons.

3 2 HOW DOES IT WORK? 3 The two magnet systems bend charged particles in the Inner Detector and the muon spectrometer, allowing their momenta to be measured. The only established stable particles that cannot be detected directly are neutrinos; their presence is inferred by noticing a momentum imbalance among detected particles. For this to work, the detector must be hermetic, and detect all non-neutrinos produced, with no blind spots. Maintaining detector performance in the high radiation areas immediately surrounding the proton beams is a significant engineering challenge. Figure 1: The ATLAS Experiment 2.1 The Inner Detector The Inner Detector is the most important component of ATLAS with regards to the upgrade project. The goal is to replace the entire detector with an all-silicon upgrade. The detector itself begins a few centimetres from the proton beam axis, extends to a radius of 1.2 metres, and is seven metres in length along the beam pipe. Its basic function is to track charged particles by detecting their interaction with material at discrete points, revealing detailed information about the type of particle and its momentum. 1 The magnetic field surrounding the entire inner detector causes charged particles to curve; the direction of the curve reveals a particle s charge and the degree of curvature reveals its momentum. The starting points of the tracks yield useful information for identifying particles; for example, if a group of tracks seem to originate from a point other than the original protonproton collision, this may be a sign that the particles came from the decay of a bottom quark. 2 The Inner Detector itself is made up of three parts: the pixel detector, the Semi-Conductor Tracker (SCT), and The Transition Radiation Tracker (TRT). The Pixel Detector, the innermost part of the detector, contains three layers and three disks on each end-cap, with a total of 1,744 modules, each measuring two centimetres by six centimetres. The detecting material is 250 m thick silicon. Each module contains 16 readout chips and other electronic components. The smallest unit that can be read out is a pixel (each 50 by 400 micrometres); there are roughly 47,000 pixels per module. The minute pixel size is designed for extremely precise tracking very close to the interaction point. 3 The Semi-Conductor Tracker (SCT) is the middle component of the inner detector, similar in concept and function to the Pixel Detector but with long, narrow strips rather than small pixels. The SCT is the most critical part of the inner detector for basic tracking in the plane perpendicular to the beam. The Transition Radiation Tracker (TRT), the outermost component of the inner detector, is a combination of a straw tracker and a transition radiation detector. The detecting elements are drift tubes (straws), each four millimetres in diameter and up to 144 centimetres long. The uncertainty of track position measurements (position resolution) is about 200 micrometres, not as precise as those for the other two detectors, a necessary sacrifice for reducing the cost of covering a larger volume and having transition radiation detection capability. 2.2 Calorimeters The calorimeters are situated outside the solenoidal magnet that surrounds the inner detector. Their purpose is to measure the energy from particles by absorbing it. There are two basic calorimeter systems: an inner electromagnetic 1 Moles-Valls, Alignment of the ATLAS inner detector tracking system. Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment 617 (1/3). 2 CERN, Inner detector. ATLAS Technical Proposal. CERN Hugging, The ATLAS pixel detector. IEEE Transactions on Nuclear Science 53 (6).

4 3 WHAT IS THE PURPOSE OF THE SILICON DETECTOR UPGRADE PROJECT? 4 calorimeter and an outer hadronic calorimeter. 4 Both calorimeters absorb energy in high-density metal and periodically sample the shape of the resulting particle shower, inferring the energy of the original particle from this measurement. 2.3 Muon Spectrometer The muon spectrometer is an extremely large tracking system, extending from a radius of 4.25 m around the calorimeters out to the full radius of the detector (11 m). 5 Its tremendous size is required to accurately measure the momentum of muons, which penetrate other elements of the detector. These measurements are vital because one or more muons can be a key element of a number of interesting physical processes, and because the total energy of particles in an event could not be measured accurately if they were ignored. 2.4 Magnet System The ATLAS detector uses two large superconducting magnet systems to bend charged particles so that their momenta can be measured. This bending is due to the Lorentz force, which is proportional to velocity. Since all particles produced in the LHC s proton collisions will be traveling at very close to the speed of light, the force on particles of different momenta is equal. Thus high-momentum particles will curve very little, while low-momentum particles will curve significantly. This the amount of curvature can be quantified and the particle momentum can be determined from this value. 3 What is the purpose of the silicon detector upgrade project? In the next years, LHC will undergo a series of upgrades leading ultimately to a five times increase in the instantaneous luminosity in the High-Luminosity LHC (HLLHC) project. The goal is to extend the dataset from about 300 f b 1, expected to be collected by the end of the LHC run around 2020, to 3000 f b 1 by around The foreseen higher luminosity at the HL-LHC is a great challenge for ATLAS. Additionaly, the harsher radiation environment and higher detector occupancies at the HL-LHC imply major changes to most of the ATLAS systems, especially those at low radii and large pseudorapidity. A general guideline for these changes is maintaining the same (or better) level of detector performance as at the LHC. 6 4 What is being upgraded? The inner detector, forward calorimeter and forward muon wheels will be affected primarily by the higher particle fluxes and radiation damage, requiring replacement or significant upgrade, whereas the barrel calorimeters and muon chambers are expected to be capable of handling the conditions and will not be modified. New, radiation-hard tracking detectors with higher granularity and higher bandwidth, as well as radiation-hard front-end electronics will also be needed. The higher event rates and event sizes expected will demand updated trigger and data acquisition (DAQ) systems with significant expansions of their capacity. The ATLAS upgrade is planned in three phases, which correspond to the three long, technical shutdowns of the LHC towards the HL-LHC. Phase-0 will take place in 2013 and 2014, Phase-I will be during 2018, and finally, Phase-II is scheduled for Phase 0 The main objective of the first shutdown of the LHC is to perform interventions which will permit the machine to operate at its design parameters: center-of-mass energy of s = 14 TeV and luminosity of 1x10 34 cm 2 s 1. ATLAS will use this two years period for detector consolidation works, including a new inner detector cooling system, a new neutron shielding of the muon spectrometer, and a new beam pipe. The current beam pipe in the forward region is made of stainless steel which is a source of high backgrounds for the muon spectrometer. The new beam pipe will be of aluminum, thus, reducing the backgrounds by 10 to 20 percent. The central ATLAS upgrade activity in Phase-0 is 4 CERN, Calorimetry. ATLAS Technical Proposal. CERN CERN, Overall detector concept. ATLAS Technical Proposal. CERN CERN, ATLAS Upgrade for the HL-LHC:meeting the challenges of a five-fold increase in collision rate

5 4 WHAT IS BEING UPGRADED? 5 the installation of a new barrel layer in the present Pixel detector, also referred to as the IBL project. The baseline concept of the IBL consists of 14 staves, mounted directly on the beam pipe with a tilt angle of 14 degrees. On each stave there are 16 to 32 modules depending on the sensor type. Currently, two silicon sensor types are under consideration: planar and 3D. (See section Data Acquisition and Baseline Integration Concepts for in-depth analysis of stave setup) 4.2 Phase 1 In 2018, the LHC will be stopped for an upgrade of the injectors and the collimators. Upgrade of the LINAC2 (200 Mhz linear particle accelerator) and increase of the Proton Synchrotron Booster output energy are planned. The datataking will be resumed after a one year shutdown with luminosity of 2x10 34 cm 2 s 1. During the shutdown, ATLAS intends to accomplish the second stage of its upgrade program, the Phase-I. In Phase-I, installation of new Muon Small Wheels and introducing of new trigger schemes are proposed to handle luminosities well beyond the nominal values. 4.3 Phase 2 The ATLAS Phase-II upgrade is scheduled for 2022 and During this time, LHC will be out of operation for furnishing with new inner triplets and crab cavities. As a result, an instantaneous luminosity of 5x10 34 cm 2 s 2 should be achieved. ATLAS Phase-II preparations include a new Inner Detector and further trigger and calorimeter upgrades. ATLAS has decided to replace the entire Inner Detector with a new, all-silicon Inner Tracker (ITk) to combat the expected challenges of utilizing the LHC at higher energies. A combination of higher detector occupancies beyond the TRT design parameters and the fact that by 2022, the Pixel and the SCT subsystems, would seriously degrade their performance due to the radiation damage of their sensors and FE electronics have led to this decision. Figure 2: The baseline layout of the new Inner Detector, traversed by simulated 23 pile-up events (left) and 230 pile-up events (right). The current baseline design of the ITk, depicted in Figure 2, consists of 4 Pixel and 5 Si-strip layers in the barrel part. The two endcap regions are each composed of 6 Pixel and 5 Si-strip double-sided disks, built of rings of modules. The pixel modules are with identical pixels of size 50x250µm, whereas the Si-strip modules come in two types, with short (24 mm) and long (96 mm) strips. As in the current SCT, the Si-strip modules are designed to be of 2 pairs of silicon microstrip sensors, glued back-to-back at an angle of 40 mrad to provide 2D space-points. 7 7 Affolder, Silicon Strip Detectors for the ATLAS HLLHC Upgrade, ATL-UPGRADE-PROC

6 5 DATA ACQUISITION AND BASELINE INTEGRATION CONCEPTS 6 5 Data Acquisition and Baseline Integration Concepts The goal of this section is to outline the design for the new data acquisition setup to be implemented as a part of the ATLAS upgrade project. Most of the research being done by the Duke upgrade team focuses on the silicon strip and data acquisition systems. Stave systems will be further explored in the paragraphs below. 5.1 Staves and Petals The baseline concepts for the integration of sensors, readout electronics, cooling and support structures are staves and petals for the strip barrel and endcap regions, respectively. 8 The biggest differences between the two concepts (illustrated in Figure 3) is shape, with the staves being rectangular and the petals being trapezoidal. In both cases, single-sided modules are glued directly to two sides of a central core which have electrical bus cables laminated to their faces. The core consists of a Titanium cooling tube sandwiched between two carbon fiber facings, spaced with either carbon honeycomb or foam. Modules are constructed by directly gluing kapton flex hybrids, which holds the readout ASICs, to silicon sensors with electronicsgrade epoxy. The resulting structures are highly integrated with short cooling paths between the ASICs, the sensors, and the cooling pipes. For staves, 12 modules are glued to a side with one side having axial strips and the other side small angle stereo. For the petals, there are six different rings of modules with a total of nine different module types. The two sides will be identical with small angle stereo built into the sensors resulting in a u-v topology. Figure 3: Left: Stave barrel strip integration concept. This drawing assumes the 128 channel ABCN25 prototype readout ASIC. Right: Petal endcap integration concept. This drawing assumes the 256 channel ABCN130 production ASIC. The production readout ASIC (ABCN130) is planned to have 256 channels using 130 nm CMOS technology. Until those ASICs are available, prototyping of staves and petals is progressing using a 128 channel, 0.25 µm CMOS ASIC (ABCN25). 9 The 130 nm technology has a large power benefit relative to the 0.25 µm technology, with the current prototype 0.25 µm ASICs predicted to generate four times the heat than the final 130 nm ASICs. 5.2 Stave Hybrids Stave hybrids are designed to have the minimum amount of material. Wire bonds instead of connectors are used to make the electrical connections to the service bus tape; the hybrids use a kapton flex technology with no laminated stiffener. Approximately hybrids will have to be assembled, bonded, and tested in the approximately three year long assembly period, so low cost, industrialized production is important. These requirements have lead to a panelized design of the hybrids as shown in figure 4. Using the ABCN25, each hybrid for the short strip barrel has two columns of 10 ASICs; the final hybrid will have one column of 10 ASICs J. Kiersted, et. al., Nucl. Instr. Meth. A 579 (2007) F.Anghinolfi, et. al., Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade, Proceedings of Topical Workshop on Electronics for Particle Physics(TWEPP-09), Paris, France, CERN , p A. Affolder, et. al., JINST 5 (2010) C12013.

7 5 DATA ACQUISITION AND BASELINE INTEGRATION CONCEPTS 7 Figure 4: Left: Panel of 8 stave hybrids. Right: Module in a DC-DC testing frame. 5.3 Stave Modules Using the ABCN25 readout ASIC, a stave module consists of two 20-ASIC hybrids directly glued onto the sensors surface. As shown in Figure 4, the stave modules are tested in a PCB frames which provides the traces and connections between the hybrids, DAQ system, and power supplies Stavelets To test the effects of the different powering scheme in a multi-module environment, stavelets have been designed and constructed. Stavelets are effectively one-third length staves with four stave modules per side (See Figure 5). Figure 5: Serial powered stavelet In order to evaluate the different powering options, one edge of the bus tapes has been widened to provide space to attach small PCBs which hold discrete powering components or custom powering ASICs, when available. The other edge is also widened to provide space for the Buffer Control Control (BCC) custom ASIC which replaces the final HCC. It provides AC-coupled LVDS clock and command and generates a 80 MHz data clock from a 40 MHz common LVDS clock Super-Module In the alternative super-module integration concept for the barrel region, the modules are doublesided (See Figure 6). Each module consists of two silicon sensors cooled by a central core of thermal pyrolytic graphite (TPG) and 4 hybrids, holding 20 readout ASICs each, which are bridged onto aluminum-nitride (AlN) facings. The 4 metal-layer kapton hybrids are laminated onto carbon-carbon base boards which provides the stiffness needed to bridge the silicon sensors and acts as the cooling path for hybrid P. Allport, et. al., Nucl. Instr. Meth. A 636 (2011) S A. Affolder, ATLAS SHLC Strip Stave Electrical Results/Plans, Third Common ATLAS CMS Electronics Workshop for LHC upgrades (ACES 2011), CERN, 9-11 March 2011, 13 ADD supermodule concept ref

8 6 DUKE RESEARCH 8 Figure 6: Demonstrator with 8 double sided modules and DC-DC converters being assembled and evaluated at CERN. 6 Duke Research As illustrated by the above examples, there have been several different proposals for new data acquisition setups and baseline integration concepts for the ATLAS detector. Now the goal of scientists partaking in the ATLAS upgrade project is to test the various design concepts for results consistent with the expectations of the upgrade. Once modules and full stave setups have been tested for performance and efficiency and can run without errors, they can be implemented into the upgrade of the inner detector. The physics department at Duke University is one of the groups responsible for carrying out the testing of such design concepts. Under the direction of Dr. Mark Kruse and Dr. Ayana Arce, a few graduate and undergraduate students (including myself) are working on the ATLAS silicon detector upgrade project both on campus and at CERN. The details of the testing procedures and hardware setups used by these students will be outlined in the sections below. 6.1 Research at CERN Olivia Miller, an undergraduate student enrolled in Duke s REU physics program, has been doing research at CERN under the direction of Todd Huffman, Carlos Garcia Argos, and Giulio Usai. An electronic log of her progress can be found here: The primary focus of their research is on testing and improving the overall performance and efficiency of the stavelet design; specifically a DC-DC powered stavelet. Dr. Usai has been working on running RF (radio frequency) emission scans on the DC-DC converters that are responsible for distributing power to the stavelet. These scans are important because they allow for the mapping of the magnetic field of the stavelet. The fields created can then be compared to the noise produced as a result of running the various stavelet tests and scans. The analysis of this noise and the generated magnetic field is important because the electromagnetic interference produced from the DC-DC converters can result in malfunctions of the surrounding devices. Adjusting and editing software to make these scans more robust and efficient is also an important part of this process. Reducing radio frequency emission will be especially important once multiple staves are implemented for testing and thus perfecting this reduction on a smaller scale is a necessity. For a DC-DC stavelet module, the power configuration for both converters and the formation of the hybrids themselves is also important to investigate. With both converters powered from the bus, it has been noted that one of the hybrids has an excess of approximately 120 ENC noise. Additional testing suggests this value is halved when running each converter from a separate power feed. The use of an LVDS Buffer Board, seen in figure 7, to reduce noise and enhance overall performance has also been implemented in the configuration of the modules used.

9 6 DUKE RESEARCH 9 Figure 7: LVDS Buffer Board that connects to the module at CERN As of now, a serially powered stavelet fitted with four single sided short strip silicon detector modules has also been successfully constructed. The system functionality has been demonstrated to work efficiently and the initial ENC (Equivalent Noise Charge) results are reported to be close to expectation. Further investigation reveals susceptibility to noise signals correlated with readout activity and additional research is needed to determine the optimal balance of performance. Although a substantial amount of further testing needs to be completed before a final design can be selected for the inner detector itself, the results pertaining to the performance and efficiency of the proposed baseline integration concepts look promising. 6.2 Research on campus Several labs and universities have also been contributing to the upgrade project by testing stavelet configurations of their own and reporting their data along the way. Specifically the physics department of Duke University, under the direction of Dr. Mark Kruse and Dr. Ayana Arce, are beginning to volunteer their resources to the project. While Olivia Miller, the REU student mentioned above, is working at CERN, an undergraduate mechanical engineer, Stefan Cafaro, is performing similar tasks on campus. An electronic log of his progress can be found here: http: //hep-atlas.phy.duke.edu/stefanelog. The research being done on Duke s campus is very similar to that being done abroad. The testing of the silicon strip and module configuration is the primary goal, however the setup used by Duke is a bit more simplistic than its CERN counterpart. A single ABCn chip is used in conjunction with an HSIO interface board for running tests and scans; the configuration can be seen in figure 8. To put it into comparison, a stave contains 12 modules. Each module contains 2 hybrids and every hybrid contains 20 chips. Figure 8: Duke s Hardware Setup: ABCn connected to HSIO The ABCn Chip The ABCN front-end chip implemented in a CMOS 0.25 µm technology and optimized for short silicon strip detectors is the prime candidate for the ATLAS Silicon Tracker Upgrade. A primary aim of this project is to develop an ASIC with full functionality required for readout of short silicon strips in the SLHC environment in a cost-effective and proven technology. Design efforts have been focused on optimizing noise and power performance of the front-end circuit for low detector capacitance, minimizing power consumption in digital blocks and on compatibility with new power distribution schemes being developed for future tracker detectors. The ABCN ASIC will serve as a basic test

10 6 DUKE RESEARCH 10 vehicle in an extensive program on development of sensors and modules for the ATLAS Silicon Tracker Upgrade. A block diagram of the ABCN chip is shown in Figure 9. Figure 9: The Block Diagram of the ABCn Chip The ABCN ASIC follows the concept of binary readout of silicon strip detectors. It comprises 128 channels of preamplifier/shaper/comparator circuits with two memory banks, one used as a pipeline for the trigger latency and another one used as a derandomizing buffer. The front-end has been optimized for 5 pf detector capacitance (2.5 cm long silicon strip detector) and it is compatible with either detector signal polarity. 14 Although the plan is to eventually install a silicon strip and a stavelet configuration on campus, the focus of the Duke research team is currently on completing research on a much smaller scale; that is analyzing the performance and efficiency of the chip itself. The advantage of this approach is being able to observe and record the strengths and weaknesses of the ABCn chip as well as alter the software configurations and script files used to enhance its overall performance Tests and Scans Aside from utilizing capture bursts to determine proper communication between hardware systems, the tests run typically consist of IDelay, Strobe Delay and Noise Occupancy scans. IDelay scans are run simply to accommodate for the phase shift in the clocks of the outgoing and incoming signals of each stream. Usually the DUT is connected to the HSIO by a flat ribbon cable of a certain length which results in a delay of the clock signal provided by the HSIO. Thus the clock of the data being sent back by the ABCN ASICs will be out of sync when sampled using a clock of the original phase. In addition LVDS buffers and BCC chips contribute significantly to this delay. The scan sweeps through the range of Idelay settings sending a burst of triggers and histogramming the number of correctly read back events for each. There usually exists more than one working range of Idelay register values (for which all the chips of a stream responded to all sent triggers). The macro then chooses and sets the delay value in the middle of the largest one. The Strobe Delay scan is used to set the timing (delay) of an injected calibration pulse with respect to the arrival time of the command to actually issue that pulse. This ensures that the discriminators, always firing at the clock 14 F. Campabadal et al., Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker. Nucl. Instr. and Meth. A. 2005,vol. 552, pp

11 6 DUKE RESEARCH 11 frequency, will be synchronous with the calibration signal. If the delay in injecting the test charge is too short, then the discriminator will fire too late and won t give a hit anymore. If it is too long, the discriminator fires too early; not yet seeing the injected charge. Due to the design implementation, the actual delay is dependent upon process variation and as a result needs to be calibrated. The Strobe delay scan consists of 2 parts, a threshold scan followed by the actual scan through the strobe delay. The results can immediately be seen in the ScanData window but more detailed plots are created and stored in a.ps file (See Figure 10). Figure 10: Strobe Delay Scan From the fits for each chip an optimal strobe delay setting is calculated which is set well above the minimum in order to avoid problems that may arise if there exists channel to channel variation in the delay within certain chips. The new Strobe Delay settings immediately take effect but also can be set in the.det config files of per chip basis (although these usually are subject to shifting if the chip temperatures vary). Noise Occupancy scans are used, as the name suggests, to measure the noise occupancy as a function of threshold. As the threshold is increased the occupancy of noise hits decrease this from 0.1 to below In order to measure the noise occupancy down to the level down to 10 6, up to 10 6 events are taken. At the other end of the scale where occupancy approaches 1, only 2000 events are recorded. Between the two extremes ther fractional occupancy of each channel is calculated after each partial burst and the number of events taken is such that, for each scanpoint, a minimum of 50 hits are seen in more than 50% of the active readout channels. A linear fit to a plot of log(noise occupancy) vs. threshold 2 is then created that allows for the estimation of the gaussian noise for each module in ENC The Signal Intercept Card The Duke research team also plans to do some hardware adjustments of their own before upgrading their design to incorporate a stavelet configuration. Similar to the LVDS Buffer Board used at CERN (mentioned above), the goal is to design a Signal Intercept Card (referred to as SIC) that will perform a similar function. The card will be designed so that it is compatible with any hardware configuration; single chip or stavelet. The SIC will most likely be connected to the J37 or J38 port on the HSIO interface board via ribbon cable should a singlechip setup be used, or potentially offer support for a stavelet connection should a stavelet setup be used. The intercept card will have two primary functions. One will be to mimic the performance of the LVDS buffer board used at CERN. The other focus will be to split the incoming LVDS signals in half, converting one set into TTL signals, and then sending those to our oscilloscope. The scope will better be able to interpret these data signals when received in a TTL format and the remaining set of LVDS signals will either be terminated or sent on to the ABCn chip or stavelet depending upon the desired configuration.

12 6 DUKE RESEARCH The Cosmic Ray Detector Running parallel to the ATLAS detector upgrade project at Duke is the cosmic ray detector project. Under the supervision of Dr. Al Goshaw, undergraduate physics majors Jack Matteucci and Yusheng Huang are working to perfect Duke s cosmic ray detector. The detector is nothing more than a series of scintillators and PMTs (Photomultiplier Tubes) used to recognize the presence of cosmic rays (See Figure 11). Figure 11: Cosmic Ray Detector The scintillators respond to the passing of muons through its body by absorbing their energy and reemitting it in the form of light. The PMTs then absorb the light emitted by the scintillator and reemit it in the form of electrons via the photoelectric effect. The subsequent multiplication of those electrons (sometimes called photo-electrons) results in an electrical pulse which can then be analyzed for further information about the particle that originally struck the scintillator. Once completed, the cosmic ray detector will be used in conjunction with the ATLAS upgrade project. The plan is to utilize the signals generated by the cosmic ray detector to test the capabilities of the data acquisition setup. Data produced by the cosmic rays will be monitored using the ABCn chip and the HSIO board and will then be recorded by the sctdaq software. This specific type of experiment will allow the performance and efficiency of the ABCn chip to be tested via particle detection signals. This will also pave the way for the future installation of a silicon strip detector. Conclusions There has been a substantial amount of progress made in the prototyping of the strip region of the HL-LHC upgrade for the ATLAS experiment. Full-size FZ silicon sensors, able to cope with the high track multiplicity and extreme fluences at the HL-LHC within specification, have been produced. Additionaly, irradiations of miniature silicon devices have demonstrated that the FZ sensors are sufficiently tolerant to radiation for the expected fluences. Prototyping of stave, petal and supermodule integration concepts have progressed well with the multiple single and double-sided modules produced. Preliminary studies with serial powering and DC-DC converters have shown acceptable noise performance. Modules have been irradiated with 24 GeV/c proton to fluences beyond those expected and have been shown to be still functional. Over the next several years, the Duke research team plans to further contribute to the ATLAS detector upgrade project. Through further collaboration with faculty members of CERN, Dr. Mark Kruse and Dr. Ayana Arce plan to continually improve upon the testing of the previously mentioned integration concepts for the ugprade of the ATLAS inner detector.

13 REFERENCES 13 References [1] Regina Moles-Valls (2010). Alignment of the ATLAS inner detector tracking system. Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment 617 (1/3). [2] Inner detector. ATLAS Technical Proposal. CERN [3] Hugging, The ATLAS pixel detector. IEEE Transactions on Nuclear Science 53 (6). [4] CERN, Calorimetry. ATLAS Technical Proposal. CERN [5] CERN, Overall detector concept. ATLAS Technical Proposal. CERN [6] CERN, ATLAS Upgrade for the HL-LHC:meeting the challenges of a five-fold increase in collision rate [7] Affolder, Silicon Strip Detectors for the ATLAS HLLHC Upgrade, ATL-UPGRADE-PROC [8] J. Kiersted, et. al., Nucl. Instr. Meth. A 579 (2007) 801. [9] F.Anghinolfi, et. al., Performance of the ABCN-25 readout chip for the ATLAS Inner Detector Upgrade, Proceedings of Topical Workshop on Electronics for Particle Physics(TWEPP-09), Paris, France, CERN , p. 62. [10] A. Affolder, et. al., JINST 5 (2010) C [11] P. Allport, et. al., Nucl. Instr. Meth. A 636 (2011) S90. [12] A. Affolder, ATLAS SHLC Strip Stave Electrical Results/Plans Third Common AT- LAS CMS ElectronicsWorkshop for LHC upgrades (ACES 2011), CERN, 9-11 March 2011, [13] ADD supermodule concept ref [14] F. Campabadal et al., Design and performance of the ABCD3TA ASIC for readout of silicon strip detectors in the ATLAS semiconductor tracker. Nucl. Instr. and Meth. A. 2005,vol. 552, pp