GENERAL DESCRIPTION PACKAGE OUTLINE

Transcription

1 LOW VOLTAGE ch VIDEO AMPLIFIER WITH LPF GENERAL DESCRIPTION The NJM7 is a Low Voltage ch Video Amplifier with LPF. Internal driver is easy to connect TV monitor directly. The NJM7 corresponds to a clamp and bias inputs, and selection of a clamp/ bias is possible for one circuit, and it corresponds to various video signals. The NJM7 features low power and small package, and is suitable for low power design on downsizing of DVC. PACKAGE OUTLINE NJM7SE NJM7V FEATURES Operating Voltage.8 to.v Input type Vin: CLAMP Vin: CLAMP/ BIAS Vin: BIAS Internal LPF Internal 6dB amplifier Internal Driver Circuit (-system drive) Internal Power Saving Circuit Bipolar Technology Package Outline Ω BLOCK DIAGRAM PCSP6, SSOP V V 6dB driver Vin LPF Vout CLAMP Vsag 6dB driver Vin LPF Vout CLAMP/BIAS SW CLAMP BIAS Vsag 6dB driver Vin LPF Vout BIAS GND Power Save GND Ver

2 PIN CONFIGURATION PCSP Vin. Power Save. Vin. NC. GND 6. Vin 7. CLAMP/BIAS SW 8. Vout 9. GND. Vout. Vsag. V. Vout. Vsag. NC 6. V SSOP 6 9. Vsag. V. Vin. Power Save. Vin 6. GND 7. Vin 8. CLAMP/BIAS SW 9. Vout. GND. Vout. Vsag. V. Vout

3 ABSOLUTE MAXIMUM RATINGS (Ta= C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage V 7. V Power Dissipation P D PCSP6 69 (Note) SSOP mw Operating Temperature Range Topr - to 8 C Storage Temperature Range Tstg - to C (Note) At on a board of EIA/JEDEC specification. (76...6mm, layers, FR-) ELECTRICAL CHARACTERISTICS (V =.V,R L =Ω,Ta= C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Operating Voltage Vopr.8.. V Operating Current I CC No Signal ma Operating Current at Power Save Isave Power Save Mode µa Maximum Output Voltage Swing Voltage Gain Low Pass Filter Characteristic Cross talk Differential Gain Differential Phase S/N Ratio nd. Distortion SW Change Voltage High Level SW Change Voltage Low Level Vomv f=khz,thd=%, CLAMP Input.. - Vom RGB Gv Gfy.M Gfy8M Gfy6M CT DG DP SNv Hv f=khz,thd=%, BIAS Input.. - Vin=kHz,.Vp-p,Sin Signal (CLAMP) Vin=kHz.7Vp-p,Sin Signal (BIAS) Vin=.MHz/kHz,.Vp-p(CLAMP) Vin=.MHz/kHz,.7Vp-p(BIAS) Vin=8MHz/kHz,.Vp-p(CLAMP) Vin=8MHz/kHz,.7Vp-p(BIAS) Vin=6MHz/kHz,.Vp-p(CLAMP) Vin=6MHz/kHz,.7Vp-p(BIAS) Vin=.MHz,.Vp-p,Sin Signal (CLAMP) Vin=.MHz.7Vp-p,Sin Signal (BIAS) (CLAMP) Vin=.Vp-p Input step Video Signal (CLAMP) Vin=.Vp-p Input step Video Signal (CLAMP) Vin=.Vp-p,% White Video Signal (BIAS) Vin=.7Vp-p,% Red field Signal (CLAMP) Vin=.Vp-p,.8MHz, Sin Signal, R L = (BIAS) Vin=.7Vp-p,.8MHz, Sin Signal, R L = Vp-p db db db -. - % -. - deg db db VthPH.8 - V VthPL -. V CONTROL TERMINAL PARAMETER STATUS NOTE H Power Save: ON Power Save L Power Save: OFF OPEN Power Save: OFF H BIAS CLAMP/BIAS SW L CLAMP OPEN CLAMP - -

4 TEST CIRCUIT (SSOP) V.µF µf µf Vsag Vout µf V V OUT- OUT- IN.µF Vin Power Save NJM7V Vsag Vout µf µf IN.µF 6 Vin GND GND Vout 9 OUT- OUT- µf IN.µF 7 Vin C/B SW 8 OUT- OUT- - -

5 APPLICATION CIRCUIT (SSOP, VIN: CLAMP) () Standard circuit () SAG correction unused circuit V.µF µf µf V.µF µf Vsag Vout µf C OUT Vsag Vout 7µF OUT V V V V IN IN.µF.µF 6 Vin NJM7V Power Save Vin GND Vsag Vout GND Vout 9 µf µf C µf IN OUT (CLAMP) IN OUT.µF.µF 6 Vin NJM7V Power Save Vin GND Vsag Vout GND Vout 9 7µF µf OUT (CLAMP) OUT IN.µF 7 Vin C/B SW 8 IN.µF 7 Vin C/B SW 8 () Two-line driving circuit V.µF µf µf Vsag Vout µf C OUT OUT V V IN IN IN.µF.µF.µF 6 7 Vin NJM7V Power Save Vin GND Vin Vsag Vout GND Vout C/B SW 9 8 µf µf C µf OUT OUT (CLAMP) OUT OUT () Standard circuit The SAG correction reduces output coupling capacitor values. The capacitor of C (µf) is recommended for the portable application. However, the µf capacitor may deteriorate SAG, and lose synchronization by luminance fluctuation. Adjust the C value, checking the waveform containing a lot of low frequency components like a bounce waveform (In case of worst condition). Change the capacitor of C into a large value to improve SAG. () SAG correction unused circuit Cancel the SAG correction to improve lost synchronization. Connect the coupling capacitor after connecting the Vout pin and Vsag pin. The recommended value is 7µF or more. () Two-line driving circuit The NJM7 drives two-line load of Ω. The capacitance value of C should be µf or more, because SAG is deteriorated than a standard circuit. - -

6 EQUIVALENT CIRCUIT PCSP6 SSOP PIN No. PIN No. PIN NAME FUNCTION INSIDE EQUIVALENT CIRCUIT V VIN Clamp input Vin 7 7 GND V SW k Power Save Power save 8k GND V Vin Clamp/Bias input Vin 7 7 k 7 GND - NC Non connection 6 GND GND V k Vin Bias input Vin GND - 6 -

7 PCSP6 PIN No. SSOP PIN No. PIN NAME FUNCTION INSIDE EQUIVALENT CIRCUIT SW k 7 8 CLAMP/ BIAS SW Clamp/Bias switch 8k GND V 8 9 Vout Bias output 8.8k Vout GND 9 GND GND V Vout Clamp/Bias output 8.8k 7 Vout GND V Vsag Sag compensation Vsag 8.8k 7 GND V Power Supply - 7 -

8 PCSP6 PIN No. SSOP PIN No. PIN NAME FUNCTION INSIDE EQUIVALENT CIRCUIT V Vout Clamp output 8.8k 7 Vout GND V Vsag Sag compensation Vsag 8.8k 7 GND - NC Non connection 6 V Power Supply APPLICATION When the power supply voltage is not impressing, don t impress voltage to the control terminal

9 NJM7 Q APPLICATION SAG correction circuit SAG correction circuit is a circuit to correct for low-frequency attenuation by high-pass filter consisting of the output coupling capacitance and load resistance. Low-frequency attenuation raises the sag in the vertical period of the video signal. Capacitor for Vsag (Csag) is connected to the negative feedback of the amplifier. This Csag increase the low frequency gain to correct for the attenuation of low frequency gain. Example SAG collection circuit Vout Cout Vsag Csag resistance:rl Vout Example of not using sag compensation circuit Vout Cout resistance:rl Vout Vsag Waveform of Vout terminal and Vout terminal using SAG correction circuit Waveform of Vout Waveform of Vout Vertical period not using SAG correction circuit Waveform of Vout Waveform of Vout Vertical period -9-

10 SAG correction circuit generates a low frequency component signal amplified to Vout terminal. Changes of the luminance signal will be low-frequency components, if you want to output a large signal luminance changes. Therefore, generate correction signal of change of a luminance signal to Vout pin. At this time, signal is over the dynamic range of Vout pin. This may cause a lack of sync signal, and waveform distortion. Please see diagram below (green waveform), if you want to output large changes of a signal luminance, such as % white video signal and black signal. Thus, output signal exceed dynamic range of Vout pin and may be the signal lack. Input signal Waveform of Vout The sync signal is missing because exceed the dynamic range of Vout. Dynamic range of Vout Waveform of Vout < Countermeasure for waveform distortion >. Please using small value the Sag compensation capacitor (VSAG). It can ensure the dynamic range by using small value the capacitor (VSAG). It because of low-frequency variation of Vout pin is smaller. However, the output (VOUT) must be use large capacitor for this reason sag characteristics become exacerbated.. Please do not use the sag correction circuit. Signal can output within dynamic range for reason it does not change the DC level of the output terminal. However, the output (VOUT) must be use large capacitor for this reason sag characteristics become exacerbated. - -

11 < Dual drive at using SAG correction circuit > Using sag correction circuit at dual drive circuit is below. Dual drives are less load resistance. Thus, the cut-off frequency of HPF that is composed of the output capacitor and load resistance will be small. Therefore, the sag characteristics deteriorate. Please size up to the output capacitor (Vout) for not to deteriorate the sag characteristics. < Dual drive at not using SAG correction circuit > We recommended two-example dual drive circuit with not use sag correction circuit. Please change the configuration to be used according to the situation. Please configure to meet the following conditions. Then you can adjust the characteristics of each configuration. Cout = Cout Cout Cout = Cout (A) In case of using one output capacitor (B) In case of using two output capacitors - -

12 < Using SAG correction circuit > Input signal: bounce signal (IRE%, IRE%, Hz), resistance=ω Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal Csag=uF Csag=uF Csag=uF Cout=uF Cout=uF Cout=uF Cout=7uF Cout=uF - -

13 Input signal: bounce signal (IRE%, IRE%, Hz), resistance= Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal Csag=uF Csag=uF Csag=uF Cout=uF Cout=7uF Cout=uF Cout=uF Cout=uF - -

14 < Not using SAG correction circuit > Input signal: bounce signal (IRE%, IRE%, Hz), resistance=ω Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal RL= RL=Ω Cout=uF Cout=7uF Cout=uF Cout=uF Cout=uF - -

15 < Using SAG correction circuit > Input signal: Black to White%, resistanceω Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal Csag=uF Csag=uF Csag=uF Cout=uF Cout=uF Cout=uF Cout=7uF Cout=uF - -

16 Input signal: White% to Black, resistanceω Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal Csag=uF Csag=uF Csag=uF Cout=uF Cout=uF Cout=uF Cout=7uF Cout=uF - 6 -

17 < Using SAG correction circuit > Input signal: Black to White%, resistance= Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal Csag=uF Csag=uF Csag=uF Cout=uF Cout=uF Cout=uF Cout=7uF Cout=uF - 7 -

18 Input signal: White% to Black, resistance= Waveform: yellow: input signal, green: Vout signal, purple: Voutsignal Csag=uF Csag=uF Csag=uF Cout=uF Cout=uF Cout=uF Cout=7uF Cout=uF - 8 -

19 Clamp circuit. Operation of Sync-tip-clamp Input circuit will be explained. Sync-tip clamp circuit (below the clamp circuit) operates to keep a sync tip of the minimum potential of the video signal. Clamp circuit is a circuit of the capacitor charging and discharging of the external input Cin. It is charged to the capacitor to the external input Cin at sync tip of the video signal. Therefore, the potential of the sync tip is fixed. And it is discharged charge by capacitor Cin at period other than the video signal sync tip. This is due to a small discharge current to the IC. In this way, this clamp circuit is fixed sync tip of video signal to a constant potential from charging of Cin and discharging of Cin at every one horizontal period of the video signal. The minute current be discharged an electrical charge from the input capacitor at the period other than the sync tip of video signals. Decrease of voltage on discharge is dependent on the size of the input capacitor Cin. If you decrease the value of the input capacitor, will cause distortion, called the H sag. Therefore, the input capacitor recommend on more than.uf. signal input Cin charge current Vin Clamp circuit diccharge current < Clamp circuit > A. Cin is large B. Cin is small (H sag experience) clamp potential clamp potential charge period discharge period charge period charge period discharge period charge period < Waveform of input terminal >. Input impedance The input impedance of the clamp circuit is different at the capacitor discharge period and the charge period. The input impedance of the charging period is a few kω. On the other hand, the input impedance of the discharge period is several MΩ. Because is a small discharge-current through to the IC. Thus the input impedance will vary depending on the operating state of the clamp circuit.. Impedance of signal source Source impedance to the input terminal, please lower than Ω. A high source impedance, the signal may be distorted. If so, please to connect a buffer for impedance conversion

20 TYPICAL CHARACTERISTICS Voltage Gain vs. Frequency Vin=.Vpp V vs Icc. 8 Gv[dB] - - Icc[mA] 6 - ch ch_clamp ch_bias ch Frequency[Hz] V [V] V vs Isave 8 V vs Vomc 7 VomB Vom 6 Isave[uA] Vomc[Vpp] V [V] V [V] V vs Vomv V vs Gv Gv GvC GvB Gv Vomv[Vpp] Vom VomC V [V] Gv[dB] V [V] Ver

21 V vs Gfy.M V vs Gfy 8M. Gf._ Gf._C Gf._B Gf._ Gfy.M [db] Gfy 8M [db] Gf8_ Gf8_C Gf8_B Gf8_ V [V] V [V] V vs Gfy 6M V vs DG - DG DGC - Gfy 6M [db] Gf6_ Gf6_C Gf6_B Gf6_ DG[%] V [V] V [V] V vs DP V vs CTave - DP DPC - DP[deg] CTave[dB] V [V] V [V] - -

22 V vs SNv V vs Hv SNv[dB] 7 Hv[dB] -6 6 SN SNC SNB SN Hv HvC HvB Hv V [V] V [V] V vs VthHL T vs Icc. VthPSH VthPSL VthC/BH VthC/BL 8 6 VthHL[V]. Icc[mA] V [V] T vs Isave T vs Vomc VomB Vom Isave[uA] 6 Vomc[Vpp]

23 T vs Vomv T vs Gv Vom VomC 7. Gv GvC GvB Gv Vomv[Vpp] Gv[dB] T vs Gfy.M T vs Gfy 8M. Gf._ Gf._C Gf._B Gf._ Gfy.M [db] Gfy 8M [db] Gf8_ Gf8_C Gf8_B Gf8_ T vs Gfy 6M T vs DG - DG DGC - Gfy 6M [db] Gf6_ Gf6_C Gf6_B Gf6_ DG[%]

24 T vs DP T vs CTave - DP DPC - DP[deg] CTave[dB] T vs SNv T vs Hv SNv[dB] 7 6 SN SNC SNB SN Hv[dB] Hv HvC HvB Hv T vs VthHL. VthPSH VthPSL VthC/BH VthC/BL VthHL[V] [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - -