Low Voltage, Stereo DAC with Headphone Amp

Transcription

1 Features l 24Pin TSSOP package l 3.6 to 1.8 Volt supply l 24Bit conversion / 96 khz sample rate l 96 db dynamic range at 3 V supply l 80 db THD+N l Low power consumption l Digital volume control 96 db attenuation, 1 db step size l Digital bass and treble boost Selectable corner frequencies Up to 12 db boost in 1 db increments l Dynamic range compression and limiting l Deemphasis for 32 khz, 44.1 khz, and 48 khz l Headphone amplifier 5 mw power output into 16 Ω load 34 db analog attenuation and mute Zero crossing click free level transitions l ATAPI mixing functions I I Low Voltage, Stereo DAC with Headphone Amp Description The CS4346 is a complete stereo digitaltoanalog output system including interpolation, 1bit D/A conversion, analog filtering, volume control and a headphone amplifier, in a 24pin TSSOP package. The CS4346 is based on deltasigma modulation, where the modulator output controls the reference voltage input to an ultralinear analog lowpass filter. This architecture allows infinite adjustment of the sample rate between 2 khz and 100 khz simply by changing the master clock frequency. The CS4346 contains onchip digital bass and treble boost, dynamic range compression, limiting, and deemphasis. The CS4346 operates from a +1.8 V to +3.6 V supply and consumes only 14 mw of power with a 1.8 V supply. These features are ideal for portable CD, MP3 and MD players and other portable playback systems that require extremely low power consumption. ORDERING INFORMATION CS4346KS 24pin TSSOP, 10 to 70 C CDB4346 Evaluation Board SCL/CCLK/DIF1 SDA/CDIN/DIF0 AD0/CS/DEM0 VQ_HP VA_HP RST VA Control Port VD_IO LRCK SCLK/DEM1 Serial Port Deemphasis Digital Volume Control Bass/Treble Boost Compression Limiting Digital Filters Σ DAC Σ DAC Analog Filter Analog Filter Analog Volume Control Analog Volume Control Headphone Amplifier HP_A HP_B SDATA GND GND_IO MCLK FILT+ REF_GND Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas (512) FAX: (512) Copyright Cirrus Logic, Inc (All Rights Reserved) JAN 99 DS328PP1 1

2 TABLE OF CONTENTS 1.0 CHARACTERISTICS/SPECIFICATIONS... 6 ANALOG CHARACTERISTICS... 6 POWER AND THERMAL CHARACTERISTICS... 8 DIGITAL CHARACTERISTICS... 9 ABSOLUTE MAXIMUM RATINGS... 9 RECOMMENDED OPERATING CONDITIONS... 9 SWITCHING CHARACTERISTICS SWITCHING CHARACTERISTICS CONTROL PORT I 2 C MODE SWITCHING CHARACTERISTICS CONTROL PORT SPI MODE TYPICAL CONNECTION DIAGRAM REGISTER QUICK REFERENCE Power and Muting Control (address 01h) Channel A Volume Control (address 02h) Channel B Volume Control (address 03h) Channel A Independent Digital Volume Control (address 04h) Channel B Independent Digital Volume Control (address 05h) Equalizer Control (address 06h) Mode Control (address 07h) Limiter Release Rate (address 08h) Limiter Attack Rate (address 09h) Volume and Mixing Control (address 0Ah) Mode Control (address 0Bh) REGISTER DESCRIPTION AutoMute Soft Ramp or Zero Cross Enable Power On/Off Quiescent Voltage Ramp Power Down Headphone Amplifier ReservED Bit Power Down Volume Control Independent Digital Volume Control Bass Boost Level Treble Boost Level Bass Boost Corner Frequency Treble Boost Corner Frequency Channel A Volume = Channel B Volume DeEmphasis Control Digital Volume Control Bypass Limiter Control Independent Volume Control Enable I 2 C is a registered trademark of Philips Semiconductors. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS IS without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at 2 DS328PP1

3 4.18 Equalizer Enable Music Mode Selection Limiter Enable ATAPI Channel Mixing and Muting Master Clock Edge Select Internal Serial Clock Frequency Digital Interface Format PIN DESCRIPTION Analog Power VA Interface Power VD_IO Headphone Amp Power VA_HP Analog Ground AGND Interface Ground GND_IO Reference Ground REF_GND Positive Voltage Reference FILT Headphone Quiescent Voltage VQ_HP Headphone Outputs HP_A and HP_B Master Clock MCLK Left/Right Clock LRCK Serial Audio Data SDATA Serial Clock SCLK Reset RST Serial Control Interface Clock SCL/CCLK (Control Port Mode) Serial Control Data I/O SDA/CDIN (Control Port Mode) Address Bit / Chip Select AD0/CS (Control Port Mode) Digital Interface Format DIF1 and DIF0 (StandAlone Mode) Deemphasis Control DEM0 and DEM1 (StandAlone Mode) Mute Control MUTEC Mode Select CP/SA Test Outputs TST APPLICATIONS Grounding and Power Supply Decoupling Oversampling Modes Recommended Powerup Sequence Use of the Power ON/OFF Quiescent Voltage Ramp CONTROL PORT INTERFACE SPI Mode I 2 C Mode PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) Dynamic Range Interchannel Isolation Interchannel Gain Mismatch Gain Error Gain Drift REFERENCES PACKAGE DIMENSIONS DS328PP1 3

4 LIST OF FIGURES Figure 1. External Serial Mode Input Timing Figure 2. Internal Serial Mode Input Timing Figure 3. SCLK and LRCK Setup Time Figure 4. Internal Serial Clock Generation Figure 5. Control Port Timing I 2 C Mode Figure 6. Control Port Timing SPI Mode Figure 7. Typical Connection Diagram Figure 8. Control Port Timing, SPI mode Figure 9. Control Port Timing, I 2 C Mode Figure 10. BaseRate Stopband Rejection Figure 11. BaseRate Transition Band Figure 12. BaseRate Transition Band (Detail) Figure 13. BaseRate Passband Ripple Figure 14. HighRate Stopband Rejection Figure 15. HighRate Transition Band Figure 16. HighRate Transition Band (Detail) Figure 17. HighRate Passband Ripple Figure 18. Headphone Output Test Load Figure 19. CS4346 Control Port Mode Serial Audio Format 0 (I 2 S) Figure 20. CS4346 Control Port Mode Serial Audio Format Figure 21. CS4346 Control Port Mode Serial Audio Format Figure 22. CS4346 Control Port Mode Serial Audio Format Figure 23. CS4346 Control Port Mode Serial Audio Format Figure 24. CS4346 Control Port Mode Serial Audio Format Figure 25. CS4346 Control Port Mode Serial Audio Format Figure 26. CS4346 StandAlone Mode Serial Audio Format 0 (I 2 S) Figure 27. CS4346 StandAlone Mode Serial Audio Format Figure 28. CS4346 StandAlone Mode Serial Audio Format Figure 29. CS4346 StandAlone Mode Serial Audio Format Figure 30. DeEmphasis Curve Figure 31. ATAPI Block Diagram DS328PP1

5 LIST OF TABLES Table 1. AutoMute Table 2. Soft Ramp and Zero Cross Enable Table 3. Power On/Off Quiescent Voltage Ramp Table 4. Power Down Headphone Amplifier Table 5. Power Down Table 6. Example Volume Settings Table 7. Example Volume Settings Table 8. Example Bass Boost Settings Table 9. Example Treble Boost Settings Table 10. Bass Boost Corner Frequency Table 11. Treble Boost Corner Frequency Table 12. Channel A Volume = Channel B Volume Table 13. DeEmphasis Control Table 14. Digital Volume Control Bypass Table 15. Example Rate Settings (Fs = 48 khz) Table 16. Independent Volume Control Enable Table 17. Equalizer Enable Table 18. Music Mode Selection Table 19. Limiter Enable Table 20. ATAPI Decode Table 21. Master Clock Edge Select Table 22. Internal Serial Clock Frequency Table 23. Digital Interface Format Table 24. Common Clock Frequencies Table 25. Digital Interface Format DIF1 and DIF0 (StandAlone Mode) Table 26. Internal Serial Clock Mode Table 27. External Serial Clock Mode Table 28. Mode Select CP/SA DS328PP1 5

6 1.0 CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (T A = 25 C; AGND = 0 V Logic "1" = VD_IO = 1.8 V; Logic "0" = GND_IO = 0 V; FullScale Output Sine Wave, 997 Hz; MCLK = MHz; Fs for Baserate Mode = 48 khz, SCLK = MHz, Measurement Bandwidth 10 Hz to 20 khz, unless otherwise specified; Fs for HighRate Mode = 96 khz, SCLK = MHz, Measurement Bandwidth 10 Hz to 40 khz, unless otherwise specified. Test load R L = 16 Ω, C L = 10 pf (See Figure 18) for headphone out.) Parameter Symbol Min Typ Max Min Typ Max Unit Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V Dynamic Range (Note 1) 18 to 24Bit unweighted AWeighted 16Bit unweighted AWeighted Total Harmonic Distortion + Noise (Note 1) 18 to 24Bit 0 db 20 db 60 db 16Bit 0 db 20 db 60 db THD+N Notes: 1. Onehalf LSB of triangular PDF dither is added to data. Baserate Mode HighRate Mode Interchannel Isolation (1 khz) db Headphone Output Dynamic Performance for VA = VA_HP = 3.0 V Dynamic Range. (Note 1) 18 to 24Bit. unweighted AWeighted 16Bit. unweighted AWeighted Total Harmonic Distortion + Noise. (Note 1) 18 to 24Bit. 0 db 20 db 60 db 16Bit. 0 db 20 db 60 db THD+N Interchannel Isolation. (1 khz) db db db db db db db db db db db db db db db db db db db db db 6 DS328PP1

7 ANALOG CHARACTERISTICS (Continued) Parameters Symbol Min Typ Max Units Analog Output Full Scale Headphone Output Voltage 0.55 VA Vpp Headphone Output Quiescent Voltage V Q_HP 0.5 VA_HP VDC Interchannel Gain Mismatch 0.1 db Gain Drift 100 ppm/ C Maximum Headphone Output VA=VA_HP=1.8V I HP 31 ma ACCurrent VA=VA_HP=3.0V 57 ma Baserate Mode HighRate Mode Parameter Symbol Min Typ Max Min Typ Max Unit Combined Digital and Onchip Analog Filter Response (Note 2) Passband (Note 3) to 0.05 db corner to 0.1 db corner to 3 db corner Frequency Response 10 Hz to 20 khz (Note 4) Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 1017) have been normalized to Fs and can be denormalized by multiplying the Xaxis scale by Fs. 4. Referenced to a 1 khz, fullscale sine wave. 5. For BaseRate Mode, the measurement bandwidth is Fs to 3 Fs. For HighRate Mode, the measurement bandwidth is Fs to 1.4 Fs. 6. Deemphasis is not available in HighRate Mode Fs Fs Fs db Passband Ripple ± db StopBand Fs StopBand Attenuation (Note 5) db Group Delay tgd 9/Fs 9/Fs s Passband Group Delay Deviation 0 40 khz 0 20 khz Deemphasis Error (Relative to 1 khz) Fs = 32 khz Fs = 44.1 khz Fs = 48 khz ±0.36/Fs +.2/ /.14 +0/.22 ±1.39/Fs ±0.23/Fs (Note 6) s s db db db DS328PP1 7

8 POWER AND THERMAL CHARACTERISTICS Baserate Mode HighRate Mode Parameters Symbol Min Typ Max Min Typ Max Units Power Supplies Power Supply Current VA=1.8V I A 7 7 ma Normal Operation VA_HP=1.8V VD_IO=1.8V I A_HP I D_IO ma ma Power Dissipation VA=1.8V mw Normal Operation VA_HP=1.8V VD_IO=1.8V mw mw Power Supply Current VA=1.8V I A µa Power Down Mode VA_HP=1.8V VD_IO=1.8V I A_HP I D_IO µa µa Power Dissipation VA=1.8V mw Power Down Mode VA_HP=1.8V VD_IO=1.8V mw mw Power Supply Current VA=3.0V I A ma Normal Operation VA_HP=3.0V VD_IO=3.0V I A_HP I D_IO ma ma Power Dissipation VA=3.0V mw Normal Operation VA_HP=3.0V VD_IO=3.0V mw mw Power Supply Current VA=3.0V I A µa Power Down Mode VA_HP=3.0V VD_IO=3.0V I A_HP I D_IO µa µa Power Dissipation VA=3.0V mw Power Down Mode VA_HP=3.0V VD_IO=3.0V mw mw Total Power Dissipation All Supplies=1.8V mw Normal Operation All Supplies=3.0V mw Package Thermal Resistance θ JA C/Watt Power Supply Rejection Ratio (1 khz) (Note 7) (60 Hz) PSRR Notes: 7. Valid with the recommended capacitor values on FILT+ and VQ_HP as shown in Figure 7. Increasing the capacitance will also increase the PSRR db db 8 DS328PP1

9 DIGITAL CHARACTERISTICS (T A = 25 C; VD_IO = 1.7V 3.6V; GND_IO = 0 V) Parameters Symbol Min Typ Max Units HighLevel Input Voltage V IH 0.7VD_IO V LowLevel Input Voltage V IL 0.3VD_IO V Input Leakage Current (Note 8) I in ±10 µa Input Capacitance 8 pf Maximum MUTEC Drive Capability Notes: 8. I in for CS4346 LRCK is 20µA max. VD_IO=1.8V VD_IO=3.0V ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.) Parameters Symbol Min Max Units DC Power Supplies: Positive Analog Headphone Digital I/O VA VA_HP VD_IO V V V Input Current, Any Pin Except Supplies I in ±10 ma Digital Input Voltage V IND 0.3 VD_IO+0.4 V Ambient Operating Temperature (power applied) T A C Storage Temperature T stg C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND = GND_IO = 0V; all voltages with respect to ground.) Parameters Symbol Min Typ Max Units Ambient Temperature T A C DC Power Supplies: Positive Analog Headphone Digital I/O VA VA_HP VD_IO ma ma V V V DS328PP1 9

10 SWITCHING CHARACTERISTICS (T A = 10 to 70 C; VA = 1.7V 3.6V; Inputs: Logic 0 = GND_IO, Logic 1 = VD_IO, CL = 20pF) Parameters Symbol Min Typ Max Units Input Sample Rate Fs khz MCLK Pulse Width High MCLK/LRCK = ns MCLK Pulse Width Low MCLK/LRCK = ns MCLK Pulse Width High MCLK / LRCK = 384 or ns MCLK Pulse Width Low MCLK / LRCK = 384 or ns MCLK Pulse Width High MCLK / LRCK = 256 or ns MCLK Pulse Width Low MCLK / LRCK = 256 or ns LRCK edge to MCLK rising or falling setup time (Note 9) t lms 10 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) % SCLK Pulse Width Low t sclkl 20 ns SCLK Pulse Width High t sclkh 20 ns SCLK Period MCLK / LRCK = 512, 256 or 384 t sclkw 1 ns SCLK Period MCLK / LRCK = 128 or 192 t 1 sclkw ns SCLK edge to MCLK rising or falling setup time t sms 10 ns (Note 9) SCLK rising to LRCK edge delay t slrd 20 ns SCLK rising to LRCK edge setup time t slrs 20 ns SDATA valid to SCLK rising setup time t sdlrs 20 ns SCLK rising to SDATA hold time t sdh 20 ns Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 10) 50 % SCLK Period (Note 11) t sclkw ns SCLK rising to LRCK edge t sclkr µs 2 SDATA valid to SCLK rising setup time t sdlrs 1 ns SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 ( 128)Fs ( 64)Fs t sdh 1 ns t sdh 1 ns Notes: 9. The setup time will be relative to either the rising or falling edge of MCLK depending upon the setting of the Master Clock Edge Select register. (See Section 4.22) 10. In Internal SCLK Mode, the duty cycle must be 50% +/ 1/2 MCLK Period. 11. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on setting of the Internal Serial Clock Frequency register. (See Section 4.23) 1 SCLK + ( 512)Fs 10 + ( 512)Fs 15 + ( 384)Fs 15 tsclkw 10 DS328PP1

11 LRCK LRCK t slrd t slrs t sclkl t sclkh SDATA t sclkr SCLK t sclkw t sdlrs t sdh tsdlrs t sdh SDATA Figure 1. External Serial Mode Input Timing *INTERNAL SCLK Figure 2. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS4346. t lms LRCK MCLK* SCLK t sms Figure 3. SCLK and LRCK Setup Time *The edge of MCLK is selected via the Master Clock Edge Select Register LRCK MCLK 1 N 2 N *INTERNAL SCLK SDATA Figure 4. Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4346. N equals MCLK divided by SCLK DS328PP1 11

12 SWITCHING CHARACTERISTICS CONTROL PORT I 2 C MODE (T A = 25 C; VD_IO = 1.8 V ±5%; Inputs: logic 0 = GND_IO, logic 1 = VD_IO, C L = 30 pf) I 2 C Mode Parameter Symbol Min Max Unit SCL Clock Frequency f scl 100 KHz RST Rising Edge to Start t irs 500 ns Bus Free Time Between Transmissions t buf 4.7 µs Start Condition Hold Time (prior to first clock pulse) t hdst 4.0 µs Clock Low time t low 4.7 µs Clock High Time t high 4.0 µs Setup Time for Repeated Start Condition t sust 4.7 µs SDA Hold Time from SCL Falling (Note 12) t hdd 0 µs SDA Setup time to SCL Rising t sud 250 ns Rise Time of Both SDA and SCL Lines t r 1 µs Fall Time of Both SDA and SCL Lines t f 300 ns Setup Time for Stop Condition t susp 4.7 µs Notes: 12. Data must be held for sufficient time to bridge the transition time, t f, of SCL. RST t irs Repeated Stop Start Start Stop SDA t buf t t t hdst high hdst t f tsusp SCL t low t hdd t sud tsust t r Figure 5. Control Port Timing I 2 C Mode 12 DS328PP1

13 SWITCHING CHARACTERISTICS CONTROL PORT SPI MODE (T A = 25 C; VD_IO = 1.8 V ±5%; Inputs: logic 0 = GND_IO, logic 1 = VD_IO, C L = 30 pf) SPI Mode Parameter Symbol Min Max Unit CCLK Clock Frequency f sclk 6 MHz RST Rising Edge to CS Falling t srs 500 ns CCLK Edge to CS Falling (Note 13) t spi 500 ns CS High Time Between Transmissions t csh 1.0 µs CS Falling to CCLK Edge t css 20 ns CCLK Low Time t scl 66 ns CCLK High Time t sch 66 ns CDIN to CCLK Rising Setup Time t dsu 40 ns CCLK Rising to DATA Hold Time (Note 14) t dh 15 ns Rise Time of CCLK and CDIN (Note 15) t r2 100 ns Fall Time of CCLK and CDIN (Note 15) t f2 100 ns Notes: 13. t spi only needed before first falling edge of CS after RST rising edge. t spi = 0 at all other times. 14. Data must be held for sufficient time to bridge the transition time of CCLK. 15. For F SCK < 1 MHz RST t srs CS t spi t css t scl t sch t csh CCLK t r2 t f2 CDIN t dsu t dh Figure 6. Control Port Timing SPI Mode DS328PP1 13

14 2.0 TYPICAL CONNECTION DIAGRAM 1.8 to 3.3 V Supply 1.8 to 3.3 V Supply *Ferrite bead µf 0.1 µf *Ferrite bead µf 0.1 µf Digital Audio Source VA VA_HP HP_A VD_IO MCLK LRCK SCLK/DEM1 SDATA CS µf 1.0 µf HP_B FILT+ *Ferrite bead µf + 10 µh 499 Ω * µf Ω *10 µh µf to 3.3 V Supply * Optional 16 Ω Headphones REF_GND 13 µc/ Mode Configuration CP/SA RST SDA/CDIN/DIF0 SCL/CCLK/DIF1 AD0/CS/DEM0 GND_IO VQ_HP AGND µf TST1** TST2** TST3** TST4** TST5** ** TST pins should be left floating Figure 7. Typical Connection Diagram 14 DS328PP1

15 3.0 REGISTER QUICK REFERENCE ** default ==> bit status after powerupsequence or reset. 3.1 Power and Muting Control (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED AMUTE (AutoMute) Default = 1 0 Disabled 1 Enabled SOFT & ZERO CROSS (Soft control and zero cross detection control) Default = 10. Soft Zero Cross Mode 0 0 Changes take effect immediately 0 1 Changes take effect on zero crossings 1 0 Changes take effect with a soft ramp (default) 1 1 Changes take effect in 1/8 db steps on each zero crossing POR (Power on/off Quiescent Voltage ramp) Default = 1. 0 Disabled 1 Enabled PDNHP (PowerDown Headphone Amplifier) Default = 0. 0 Disabled 1 Enabled PDN (PowerDown) Default = 1. 0 Disabled 1 Enabled 3.2 Channel A Volume Control (address 02h) 3.3 Channel B Volume Control (address 03h) VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL VOL70 (Volume) Default = 0 (Refer to Table 6) DS328PP1 15

16 3.4 Channel A Independent Digital Volume Control (address 04h) 3.5 Channel B Independent Digital Volume Control (address 05h) VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL VOL70 (Volume) Default = 0 (Refer to Table 7) 3.6 Equalizer Control (address 06h) BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB BB30 (Bass Boost Level) Default = 0. (Refer to Table 8) TB30 (Treble Boost Level) Default = 0. (Refer to Table 9) 3.7 Mode Control (address 07h) BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP BBCF1, BBCF0 (Bass Boost Corner Frequency) Default = Hz Hz Hz 3 Reserved TBCF1, TBCF0 (Treble Boost Corner Frequency) Default = khz 1 4 khz 2 7 khz 3 Reserved A = B (Channel A Volume = Channel B Volume) Default = 0. 0 HP_A volume is determined by the channel A volume control registers and HP_B volume is determined by the channel B volume control registers. 1 HP_A and HP_B volumes are determined by the channel A volume control registers and the channel B volume control registers are ignored. 16 DS328PP1

17 DEM1, DEM0 (DeEmphasis Mode) Default = 0. 0 Disabled khz DeEmphasis 2 48 khz DeEmphasis 3 32 khz DeEmphasis VCBYP (Digital Volume Control Bypass) Default = 0 0 Disabled 1 Enabled 3.8 Limiter Release Rate (address 08h) 3.9 Limiter Attack Rate (address 09h) RATE7 RATE6 RATE5 RATE4 RATE3 RATE2 RATE1 RATE RATE70 (Limiter Rate) Default = 7, (50 ms at Fs = 48 khz) (Refer to Table 15) 3.10 Volume and Mixing Control (address 0Ah) INDVC EQ MUSICMODE LIMITER ATAPI3 ATAPI2 ATAPI1 ATAPI INDVC (Independent Volume Control Enable) Default = 0 0 Disabled 1 Enabled EQ (Equalizer Enable) Default = 0 0 Disabled 1 Enabled MUSICMODE (Music Mode Selection) Default = 0 0 Classical mode 1 Rock mode LIMITER (Limiter Enable) Default = 0 0 Disabled 1 Enabled ATAPI 30 (Channel mixing and muting) (refer to Table 20) Default = 1001, (Stereo) HP_A = Left Channel HP_B = Right Channel DS328PP1 17

18 3.11 Mode Control (address 0Bh) MCLKEDGE RESERVED RESERVED INTSCLK1 INTSCLK0 DIF2 DIF1 DIF MCLKEDGE (Master Clock Edge Select) Default = 0 0 Positive edge of MCLK 1 Negative edge of MCLK INTSCLK1, INTSCLK0 (Internal Serial Clock Frequency) Default = x Fs Internal SCLK 1 48 x Fs Internal SCLK 2 64 x Fs Internal SCLK 3 Reserved DIF2, DIF1 and DIF0 (Digital Interface Format) Default = 0. 0 I 2 S, up to 24bit Data, Data valid on positive edge of SLCK (default) 1 Left Justified, up to 24bit Data, Data valid on positive edge of SLCK 2 Right Justified, 16bit Data, Data valid on positive edge of SLCK 3 Right Justified, 24bit Data, Data valid on positive edge of SLCK 4 Right Justified, 18bit Data, Data valid on positive edge of SLCK 5 Right Justified, 20bit Data, Data valid on positive edge of SLCK 6 Left Justified, up to 24bit Data, Data valid on negative edge of SLCK 7 Reserved 18 DS328PP1

19 4.0 REGISTER DESCRIPTION 4.1 AUTOMUTE Power and Muting Control Register (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED Access: Default: R/W in I 2 C and write only in SPI. 1 Enabled The DigitaltoAnalog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or 1. A single sample of nonstatic data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similiar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. AMUTE 0 Disabled 1 Enabled MODE Table 1. AutoMute 4.2 SOFT RAMP OR ZERO CROSS ENABLE Power and Muting Control Register (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED Access: Default: R/W in I 2 C and write only in SPI. 10 Soft Ramp enabled. Soft Ramp Enable Zero Cross Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. DS328PP1 19

20 Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implemented on a signal zero crossing. The 1/8 db level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. SOFT ZERO Mode 0 0 Changes take affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled Table 2. Soft Ramp and Zero Cross Enable 4.3 POWER ON/OFF QUIESCENT VOLTAGE RAMP Power and Muting Control Register (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED Access: Default: R/W in I 2 C and write only in SPI. 1 Enabled The power On/Off Quiescent Voltage Ramp allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during poweron or poweroff. Please refer to the applications section for details of implementing this feature. POR MODE 0 Disabled 1 Enabled Table 3. Power On/Off Quiescent Voltage Ramp 20 DS328PP1

21 4.4 POWER DOWN HEADPHONE AMPLIFIER Power and Muting Control Register (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled The headphone amplifier will independently enter a lowpower state whenever this function is activated. PDNHP MODE 0 Disabled 1 Enabled Table 4. Power Down Headphone Amplifier 4.5 RESERVED BIT Power and Muting Control Register (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED Access: Default: R/W in I 2 C and write only in SPI. 1 Note: This bit must be set to 1 for proper operation of the CS4346 DS328PP1 21

22 4.6 POWER DOWN Power and Muting Control Register (address 01h) AMUTE SOFT & ZERO CROSS POR PDNHP RESERVED PDN RESERVED Access: Default: R/W in I 2 C and write only in SPI. 1 Enabled The entire device will enter a lowpower state whenever this function is activated. The powerdown bit defaults to enabled on powerup and must be disabled before normal operation will begin. The contents of the control registers are retained in this mode PDN 0 Disabled 1 Enabled MODE Table 5. Power Down 4.7 VOLUME CONTROL Channel A Volume Control Register (address 02h) Channel B Volume Control Register (address 03h) VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 Access: Default: R/W in I 2 C and write only in SPI. 0 0 db (No attenuation) The Volume Control allows the user to alter the signal level in 1 db increments from +24 to 96 db. Volume settings are decoded as shown in Table 6, using a 2 s complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less than 96 db are equivalent to muting the channel via the ATAPI bits. When Independent Volume Control is disabled (see Section 4.17), the CS4346 chooses the optimal level of analog versus digital attenuation based on the Music Mode Selection register to achieve the total user requested attenuation. When Independent Volume Control is enabled the Analog Volume Control operates independentely from the Digital Volume Control. In this mode, the Volume Control registers allow the user to attenuate the output signal in 1 db increments from 0 to 34 db, using the analog volume control. Volume settings are decoded as shown in Table 6, using a 2 s complement code. The volume changes are implemented as dictated by the Zero Cross bit in the Volume and Mixing Control register. All volume settings less than 34 db are interpreted as 34 db. Any levels greater than zero are ignored in this mode. 22 DS328PP1

23 Binary Code Decimal Value Volume Setting db db db db db Table 6. Example Volume Settings 4.8 INDEPENDENT DIGITAL VOLUME CONTROL Channel A Independent Digital Volume Control Register (address 04h) Channel B Independent Digital Volume Control Register (address 05h) VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 Access: Default: R/W in I 2 C and write only in SPI. 0 0 db (No attenuation) When Independent Volume Control is disabled this register is ignored. (see Section 4.17) When Independent Volume Control is enabled the Independent Digital Volume control allows the user to alter the signal level in 1 db increments from +24 to 96 db, using the Digital Volume Control. Volume settings are decoded as shown in Table 7, using a 2 s complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less than 96 db are equivalent to muting the channel via the ATAPI bits (See Section 4.21). Binary Code Decimal Value Volume Setting db db db db db Table 7. Example Volume Settings DS328PP1 23

24 4.9 BASS BOOST LEVEL Equalizer Control Register (address 06h) BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0 Access: Default: R/W in I 2 C and write only in SPI. 0 0 db (No Bass Boost) The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 db increments from 0 to +12 db of boost. Boost levels are decoded as shown in Table 8. Levels above +12 db are interpreted as +12 db. Binary Code Decimal Value Boost Setting db db db db db Table 8. Example Bass Boost Settings 4.10 TREBLE BOOST LEVEL Equalizer Control Register (address 06h) BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0 Access: Default: R/W in I 2 C and write only in SPI. 0 0 db (No Treble Boost) The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 db increments from 0 to +12 db of boost. Boost levels are decoded as shown in Table 9. Levels above +12 db are interpreted as +12 db. Binary Code Decimal Value Boost Setting db db db db db Table 9. Example Treble Boost Settings 24 DS328PP1

25 4.11 BASS BOOST CORNER FREQUENCY Mode Control Register (address 07h) BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP Access: Default: R/W in I 2 C and write only in SPI Hz The bass boost corner frequency is user selectable as show in Table 10. BBCF1 BBCF0 Corner Frequency Hz Hz Hz 1 1 Reserved Table 10. Bass Boost Corner Frequency 4.12 TREBLE BOOST CORNER FREQUENCY Mode Control Register (address 07h) BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP Access: Default: R/W in I 2 C and write only in SPI. 0 2 khz The treble boost corner frequency is user selectable as show in Table 11. TBCF1 TBCF0 Corner Frequency khz khz khz 1 1 Reserved Table 11. Treble Boost Corner Frequency DS328PP1 25

26 4.13 CHANNEL A VOLUME = CHANNEL B VOLUME Mode Control Register (address 07h) BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the A Channel Volume Control Bytes and the B Channel Bytes is ignored when this function is enabled. A = B Mode 0 Disabled 1 Enabled Table 12. Channel A Volume = Channel B Volume 4.14 DEEMPHASIS CONTROL Mode Control Register (address 07h) BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital deemphasis filter response at 32, 44.1 or 48 khz sample rates. (See Figure 30) NOTE: Deemphasis is not available in HighRate Mode. DEM1 DEMO Description 0 0 Disabled khz khz khz Table 13. DeEmphasis Control 26 DS328PP1

27 4.15 DIGITAL VOLUME CONTROL BYPASS Mode Control Register (address 07h) BBCF1 BBCF0 TBCF1 TBCF0 A=B DEM1 DEM0 VCBYP Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled When this function is enabled the digital volume control section is bypassed. This disables the digital volume control, muting, bass boost, treble boost, limiting and ATAPI functions. The analog volume control will remain functional. VCBYP Mode 0 Disabled 1 Enabled Table 14. Digital Volume Control Bypass 4.16 LIMITER CONTROL Limiter Release Rate Register (address 08h) Limiter Attack Rate Register (address 09h) RATE7 RATE6 RATE5 RATE4 RATE3 RATE2 RATE1 RATE0 Access: Default: R/W in I 2 C and write only in SPI ms at Fs = 48 khz The limiter attack and release rates are user selectable. The rate is a function of sampling frequency, Fs, and the value in Limiter Release or Attack Rate register. Rates are calculated using the function RATE = [(2 14 /{value})/fs]. Where {value} is the decimal value in the Limiter Release or Attack Rate register and RATE is in seconds. NOTE: A value of zero in either register will disable the limiter function. Binary Code Decimal Value Rate (ms) Table 15. Example Rate Settings (Fs = 48 khz) DS328PP1 27

28 4.17 INDEPENDENT VOLUME CONTROL ENABLE Volume and Mixing Control Register (address 0Ah) INDVC EQ MUSICMODE LIMITER ATAPI3 ATAPI2 ATAPI1 ATAPI0 Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled When this function is disabled, the HP_A and HP_B volume levels are controlled by the A and B Volume Control registers and the Independent Digital Volume Control registers are ignored. When this function is enabled, the volume levels are determined by both the Volume Control registers and the Independent Digital Volume Control registers. The Volume Control registers will only control the analog volume control and the Independent Digital Volume Control registers will control the digital volume control. NOTE: The Music Mode Selection register is ignored when Independent Volume Control is enabled; the user must set the digital and analog volume controls manually. INDVC MODE 0 Disabled 1 Enabled Table 16. Independent Volume Control Enable 4.18 EQUALIZER ENABLE Volume and Mixing Control Register (address 0Ah) INDVC EQ MUSICMODE LIMITER ATAPI3 ATAPI2 ATAPI1 ATAPI0 Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled The Bass Boost and Treble Boost features are active when this function is enabled. EQ MODE 0 Disabled 1 Enabled Table 17. Equalizer Enable 28 DS328PP1

29 4.19 MUSIC MODE SELECTION Volume and Mixing Control Register (address 0Ah) INDVC EQ MUSICMODE LIMITER ATAPI3 ATAPI2 ATAPI1 ATAPI0 Access: Default: R/W in I 2 C and write only in SPI. 0 Classical mode When in Classical mode, attenuation is implemented in the analog domain for settings or 1 to 34 db. Attenuation below 34 db is implemented digitally. This maximizes the dynamic range performance of the volume control. When in Rock mode, the CS4346 divides the attenuation between the analog and digital volume controls. For example, if the user requests +10 db of Bass Boost and 20 db of attenuation, the CS4346 will use 10 db of digital attenuation and 10 db of analog attenuation. This helps minimize clipping while still maintianing good dynamic range performance. MUSIC MODE MODE 0 Classical mode 1 Rock mode Table 18. Music Mode Selection 4.20 LIMITER ENABLE Volume and Mixing Control Register (address 0Ah) INDVC EQ MUSICMODE LIMITER ATAPI3 ATAPI2 ATAPI1 ATAPI0 Access: Default: R/W in I 2 C and write only in SPI. 0 Disabled The CS4346 will limit the maximum signal amplitude to prevent clipping when this function is enabled. Limiting is performed by first decreasing the Bass Boost Level. If the signal is still clipping, then the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate register. Once the signal has dropped below the clipping level, the attenuation is decreased back to the user selected level and then, the Bass Boost is increased back to the user selected level. The release rate is determined by the Limiter Release Rate register. LIMITER MODE 0 Disabled 1 Enabled Table 19. Limiter Enable DS328PP1 29

30 4.21 ATAPI CHANNEL MIXING AND MUTING Volume and Mixing Control Register (address 0Ah) INDVC EQ MUSICMODE LIMITER ATAPI3 ATAPI2 ATAPI1 ATAPI0 Access: Default: R/W in I 2 C and write only in SPI HP_A = al, HP_B = br (Stereo) The CS4346 implements the channel mixing functions of the ATAPI CDROM specification. Refer to Table 20 and Figure 31 for additional information. NOTE: All mixing functions occur prior to the digital volume control. ATAPI3 ATAPI2 ATAPI1 ATAPI0 HP_A HP_B MUTE MUTE MUTE br MUTE bl MUTE b[(l+r)/2] ar MUTE ar br ar bl ar b[(l+r)/2] al MUTE al br al bl al b[(l+r)/2] a[(l+r)/2] MUTE a[(l+r)/2] br a[(l+r)/2] bl a[(l+r)/2] b[(l+r)/2] Table 20. ATAPI Decode 30 DS328PP1

31 4.22 MASTER CLOCK EDGE SELECT Mode Control Register (address 0Bh) MCLKEDGE RESERVED RESERVED INTSCLK1 INTSCLK0 DIF2 DIF1 DIF0 Access: Default: R/W in I 2 C and write only in SPI. 0 Positive Edge Selects the edge of MCLK on which LRCK and SCLK edges are sampled. MCLKEDGE MODE 0 Positive Edge 1 Negative Edge Table 21. Master Clock Edge Select DS328PP1 31

32 4.23 INTERNAL SERIAL CLOCK FREQUENCY Mode Control Register (address 0Bh) MCLKEDGE RESERVED RESERVED INTSCLK1 INTSCLK0 DIF2 DIF1 DIF0 Access: Default: R/W in I 2 C and write only in SPI x Fs Internal SCLK The Internal Serial Clock Frequency determines the frequency of the internal serial clock when the CS4346 is configured for Internal Serial Clock Mode. 32x and 64x internal serial clocks can be used with 128x, 256x, or 512x MCLK frequencies. 48x internal serial clock mode can be used with 192x or 384 x MCLK frequencies. INTSCLK1 INSCLK0 INTERNAL SCLK FREQUENCY x Fs x Fs x Fs 1 1 Reserved Table 22. Internal Serial Clock Frequency 4.24 DIGITAL INTERFACE FORMAT Mode Control Register (address 0Bh) MCLKEDGE RESERVED RESERVED INTSCLK1 INTSCLK0 DIF2 DIF1 DIF0 Access: Default: R/W in I 2 C and write only in SPI. 0 Format 0 (I 2 S, up to 24bit data, Data valid on positive edge of SLCK) The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE I 2 S, up to 24bit Data, Data valid on positive edge of SLCK Left Justified, up to 24bit Data, Data valid on positive edge of SLCK Right Justified, 16bit Data, Data valid on positive edge of SLCK Right Justified, 24bit Data, Data valid on positive edge of SLCK Right Justified, 18bit Data, Data valid on positive edge of SLCK Right Justified, 20bit Data, Data valid on positive edge of SLCK Left Justified, up to 24bit Data, Data valid on negative edge of SLCK Reserved Table 23. Digital Interface Format 32 DS328PP1

33 5.0 PIN DESCRIPTION Reset RST 1 24 TST5 Test Output 5 Left/Right Clock LRCK 2 23 TST4 Test Output 4 Serial Data SDATA 3 22 TST3 Test Output 3 AD0/CS/DEM0 AD0/CS/DEM HP_B Headphone Output B Serial Clock/DEM1 SCLK/DEM VA_HP Headphone Amp Power Interface Power VD_IO 6 19 TST2 Test Output 2 Master Clock MCLK 7 18 VA Analog Power SCL/CCLK/DIF1 SCL/CCLK/DIF AGND Analog Ground SDA/CDIN/DIF0 SDA/CDIN/DIF HP_A Headphone OutputA Interface Ground GND_IO TST1 Test Output 1 Mode Select CP/SA FILT+ Positive Voltage Reference HP Quiescent Voltage VQ_HP REF_GND Reference Ground Analog Power VA Pin 18, Input Analog power supply. Typically 1.8 to 3.3 VDC. Interface Power VD_IO Pin 5, Input Digital interface power supply. Typically 1.8 to 3.3 VDC. Headphone Amp Power VA_HP Pin 20, Input Headphone amplifier power supply. Typically 0.9 to 3.3 VDC. Analog Ground AGND Pin 17, Input Analog Ground Reference. Interface Ground GND_IO Pin 10, Input Digital Interface ground reference. Reference Ground REF_GND Pin 13, Input Ground reference for the internal sampling circuits. Must be connected to analog ground. DS328PP1 33

34 Positive Voltage Reference FILT+ Pin 14, Output Positive reference for internal sampling circuits. An external capacitor is required from FILT+ to analog ground, as shown in Figure 7. The recommended value will typically provide 60 db of PSRR at 1 khz and 40 db of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedence of 250 kω and any current drawn from this pin will alter device performance. Headphone Quiescent Voltage VQ_HP Pin 12, Output Filter connection for internal headphone amp quiescent reference voltage. A capacitor must be connected from VQ_HP to analog ground, as shown in Figure 7. VQ_HP is not intended to supply external current. VQ_HP has a typical source impedence of 250 kω and any current drawn from this pin will alter device performance. Headphone Outputs HP_A and HP_B Pins 16 and 21, Output The full scale analog headphone output level is specified in the Analog Characteristics specifications table. 34 DS328PP1

35 Master Clock MCLK Pin 7, Input The master clock frequency must be either 256x, 384x or 512x the input sample rate in Base Rate Mode (BRM) and either 128x or 192x the input sample rate in High Rate Mode (HRM). Table 24 illustrates several standard audio sample rates and the required master clock frequencies. MCLK (MHz) Sample Rate HRM BRM (khz) 128x 192x 256x 384x 512x Table 24. Common Clock Frequencies Left/Right Clock LRCK Pin 2, Input The Left/Right clock determines which channel is currently being input on the serial audio data input, SDA TA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right sample pairs will be simultaneously output from the digitaltoanalog converter whereas Right/Left pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte when in Control Port Mode or by the DIF20 pins when in StandAlone mode. The options are detailed in Figures Serial Audio Data SDATA Pin 3, Input Two s complement MSBfirst serial data is input on this pin. The data is clocked into SDATA via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte when in Control Port Mode or by the DIF20 pins when in StandAlone mode. The options are detailed in Figures Serial Clock SCLK Pin 5, Input Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures The CS4346 supports both internal and external serial clock generation modes. The Internal Serial Clock Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode is always preferred. Internal Serial Clock Mode In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon the Mode Control Byte when in Control Port Mode or the DIF20 pins when in StandAlone mode as shown in Figures Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. DS328PP1 35

36 External Serial Clock Mode The CS4346 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK Reset RST Pin 1, Input The device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port cannot be accessed when Reset is low. Serial Control Interface Clock SCL/CCLK (Control Port Mode) Pin 8, Input Clocks the serial control data into or out of SDA/CDIN. Serial Control Data I/O SDA/CDIN (Control Port Mode) Pin 9, Input/Output In I 2 C mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. Address Bit / Chip Select AD0/CS (Control Port Mode) Pin 4, Input In I 2 C mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a powerdown cycle. Digital Interface Format DIF1 and DIF0 (StandAlone Mode) Pins 8 and 9, Input The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures DIF1 DIF0 DESCRIPTION FORMAT FIGURE 0 0 I 2 S, up to 24bit data Left Justified, up to 24bit data Right Justified, 24bit Data Right Justified, 16bit Data 3 29 Table 25. Digital Interface Format DIF1 and DIF0 (StandAlone Mode) Deemphasis Control DEM0 and DEM1 (StandAlone Mode) Pins 4 and 5, Input Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital deemphasis filter response at 32, 44.1 or 48 khz sample rates. (See Figure 30) When using Internal Serial Clock Mode, as described above, Pin 5 is available for deemphasis control, DEM1, and all deemphasis filters are available, Table 26. When using External Serial Clock Mode, as described above, Pin 5 is not available for deemphasis use and only the 44.1 khz deemphasis filter is available, Table 27. NOTE: Deemphasis is not available in HighRate Mode. 36 DS328PP1

37 DEM1 DEMO DESCRIPTION 0 0 Disabled kHz kHz kHz Table 26. Internal Serial Clock Mode DEMO DESCRIPTION 0 Disabled kHz Table 27. External Serial Clock Mode Mute Control MUTEC Pin 24, Output The Mute Control pin goes high during powerup initialization, reset, muting, powerdown or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be used as a control for an external mute circuit on the line outputs to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Mode Select CP/SA Pin 11, Input The Mode Select pin is used to select control port or standalone mode. When high, the CS4346 will be in control port mode. When low, the CS4346 will be in standalone mode. CP/SA DESCRIPTION 0 StandAlone 1 Control Port Table 28. Mode Select CP/SA Test Outputs TST15 Pins 15, 19, 22,23 and 24, No Connect Function. These pins are for factory testing and should be left floating. DS328PP1 37

38 6.0 APPLICATIONS 6.1 Grounding and Power Supply Decoupling As with any high resolution converter, the CS4346 requires careful attention to power supply and grounding arrangements to optimize performance. Figures 7 show the recommended power arrangement with VA, VA_HP and VD_IO connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. 6.2 Oversampling Modes The CS4346 operates in one of two oversampling modes. Base Rate Mode supports input sample rates up to 50 khz while High Rate Mode supports input sample rates up to 100 khz. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or Recommended Powerup Sequence 1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and VQ_HP will remain low. Set the CP/SA pin at this time. 2. Bring RST high. The device will remain in a low power state with VQ_HP low and will latch CP/SA. The control port will be accesable at this time. The desired register settings can be loaded while keeping the PDN bit set to Set the PDN bit to 0 which will initiate the powerup sequence, which requires approximately 50 µs when the POR bit is set to 0. If the POR bit is set to 1, see Section 6.4 for total powerup timing. 6.4 Use of the Power ON/OFF Quiescent Voltage Ramp The CS4346 uses a novel technique to minimize the effects of output transients during powerup and powerdown. This technique, when used with external DCblocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by singleended singlesupply converters. When the device is initially poweredup, the audio outputs, HP_L and HP_R, are clamped to AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 left/right clock cycles later, the outputs reach V Q_LINE and V Q_HP respectively and audio output begins. This gradual voltage ramping allows time for the external DCblocking capacitor to charge to the quiescent voltage, minimizing the powerup transient. To prevent transients at powerdown, the device must first enter its powerdown state. When this occurs, audio output ceases and the internal output buffers are disconnected from HP_L and HP_R. In their place, a softstart current sink is substituted which allows the DCblocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next poweron. To prevent an audio transient at the next poweron, it is necessary to ensure that the DCblocking capacitors have fully discharged before turning off the power or exiting the powerdown state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the powerdown state is related to the value of the DCblocking capacitance. For example, with a 220 µf capacitor on the headphone outputs, the minimum powerdown time will be approximately 0.4 seconds. Use of the Mute Control function on the line outputs is recommended for designs requiring the ab 38 DS328PP1