192 khz Stereo DAC with Integrated PLL. 3.3 V to 5.0 V. Interpolation Filter with Volume Control. Modulator. Interpolation Filter with Volume Control

Transcription

1 192 khz Stereo DAC with Integrated PLL Features Advanced Multibit DeltaSigma Architecture 109 Dynamic Range 91 THD+N 24Bit Conversion Supports Audio Sample Rates Up to 192 khz LowLatency Digital Filtering SingleEnded or Differential Analog Output Architecture Integrated PLL Locks to Incoming LeftRight Clock Eliminates the Need for External Masterclock Routing Reduces Interference and Jitter Sensitivity No External Loop Filter Components Required Automatic SampleRate Range Detection Popguard Technology for Control of Clicks and Pops Hardware Popguard Disable for Fast Startups Supports All Standard Serial Audio Formats Including TimeDivision Multiplexed (TDM) +1.5 V to 5.0 V Logic Supplies for Serial Port +3.3 V to 5.0 V Control Port Interface Control Port Mode Features SPI and I²C Modes ATAPI Mixing Mute Control for Individual Channels Digital Volume Control with Soft Ramp Attenuation 1/2 Step Size Zero Crossing ClickFree Transitions 3.3 V to 5.0 V 3.3 V to 5.0 V Hardware or I 2 C/ SPI Control Data Reset 1.5 V to 5.0 V Serial Audio Input LRCK Recovered MCLK Level Translator Level Translator Register/ Hardware Configuration RMCK PCM Serial Interface RMCK Phase Locked Loop Interpolation Filter with Volume Control Interpolation Filter with Volume Control Multibit ΔΣ Modulator Multibit ΔΣ Modulator Internal Voltage Reference and Regulation DAC DAC Amp + Filter Amp + Filter External Mute Control Left Channel Output Right Channel Output Left and Right Mute Controls Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc (All Rights Reserved) MARCH '07 DS691PP1

2 Description The is a complete stereo digitaltoanalog system including PLLbased master clock derivation, digital interpolation, 5thorder multibit deltasigma digitaltoanalog conversion, digital deemphasis, volume control, channel mixing, and analog filtering. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The supports all standard digital audio interface formats, including TDM. The is available in a 24pin TSSOP package in both Commercial (40 to +85 C) and Automotive grades (40 to +105 C). The CDB4350 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to Ordering Information on page 40 for complete ordering information. These features are ideal for costsensitive, 2channel audio systems, including DVD players and recorders, settop boxes, digital TVs, minicomponent systems, mixing consoles and automotive audio systems. 2 DS691PP1

3 TABLE OF CONTENTS 1. PIN DESCRIPTION CHARACTERISTICS AND SPECIFICATIONS... 8 RECOMMENDED OPERATING CONDITIONS... 8 ABSOLUTE MAXIMUM RATINGS... 8 DAC ANALOG CHARACTERISTICS COMMERCIAL (CZZ)... 9 DAC ANALOG CHARACTERISTICS AUTOMOTIVE (DZZ) COMBINED INTERPOLATION & ONCHIP ANALOG FILTER RESPONSE SWITCHING SPECIFICATIONS SERIAL AUDIO INTERFACE SWITCHING CHARACTERISTICS CONTROL PORT I²C FORMAT SWITCHING CHARACTERISTICS CONTROL PORT SPI FORMAT DIGITAL CHARACTERISTICS POWER AND THERMAL CHARACTERISTICS TYPICAL CONNECTION DIAGRAM APPLICATIONS Sample Rate Range and Oversampling Mode Detect Sample Rate AutoDetect System Clocking Recovered Master Clock (RMCK) Digital Interface Format TimeDivision Multiplex (TDM) Mode DeEmphasis Mute Control Recommended PowerUp Sequence StandAlone Mode Control Port Mode Popguard Transient Control PowerUp PowerDown Discharge Time Analog Output and Filtering Grounding and Power Supply Arrangements Capacitor Placement STANDALONE OPERATION Serial Port Format Selection DeEmphasis Control Popguard Transient Control CONTROL PORT OPERATION MAP Auto Increment I²C Mode I²C Write I²C Read SPI Mode SPI Write SPI Read Memory Address Pointer (MAP) INCR (Auto Map Increment Enable) MAP (Memory Address Pointer) REGISTER QUICK REFERENCE REGISTER DESCRIPTION Device and Revision ID Register 01h Mode Control Register 02h Digital Interface Format (DIF[2:0]) Bits DS691PP1 3

4 8.2.2 DeEmphasis Control (DEM[1:0]) Bits Functional Mode (FM[1:0]) Bits Volume Mixing and Inversion Control Register 03h Channel A Volume = Channel B Volume (VOLB=A) Bit Invert Signal Polarity (INVERT_A) Bit Invert Signal Polarity (INVERT_B) Bit ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits Mute Control Register 04h AutoMute (AMUTE) Bit AMUTEC = BMUTEC (MUTEC A=B) Bit Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit Channel A & B Volume Control Register 05h & 06h Ramp and Filter Control Register 07h Soft Ramp and Zero Cross Control (SZC[1:0]) Bits Soft Volume RampUp after Error (RMP_UP) Bit Soft RampDown before Filter Mode Change (RMP_DN) Bit Interpolation Filter Select (FILT_SEL) Bit Misc. Control Register 08h Power Down (PDN) Bit Freeze Controls (FREEZE) Bit Popguard Enable (POPG_EN) Bit RMCK control (RMCK_CTR[1:0]) Bits 3: RMCK Ratio Select (R_SELECT[1:0]) Bits 2: FILTER PLOTS PARAMETER DEFINITIONS PACKAGE DIMENSIONS THERMAL CHARACTERISTICS ORDERING INFORMATION REVISION HISTORY DS691PP1

5 LIST OF FIGURES Figure 1. Equivalent Output Load Figure 2. Maximum Loading Figure 3. Serial Port Timing, NonTDM Mode Figure 4. Serial Port Timing, TDM Mode Figure 5. Control Port Timing I²C Format Figure 6. Control Port Timing SPI Mode Figure 7. Typical Connection Diagram Figure 8. LeftJustified up to 24Bit Data Figure 9. I²S, up to 24Bit Data Figure 10. RightJustified Data Figure 11. TDM Mode Connection Diagram Figure 12. TDM Mode Timing Figure 13. DeEmphasis Curve Figure 14. Differential to Singleended Output Filter Figure 15. Passive SingleEnded Output Filter Figure 16. Control Port Timing, I²C Mode Figure 17. Control Port Timing, SPI Mode Figure 18. DeEmphasis Curve Figure 19. ATAPI Block Diagram Figure 20. Stopband Rejection (fast), all Modes Figure 21. Stopband Rejection (slow), all Modes Figure 22. SingleSpeed (fast) Passband Detail Figure 23. SingleSpeed (slow) Passband Detail Figure 24. DoubleSpeed (fast) Passband Detail Figure 25. DoubleSpeed (slow) Passband Detail Figure 26. QuadSpeed (fast) Passband Detail Figure 27. QuadSpeed (slow) Passband Detail LIST OF TABLES Table 1. Pin Descriptions... 7 Table 2. AutoDetect Table 3. Digital Interface Format StandAlone Mode Table 4. Digital Interface Formats Table 5. ATAPI Decode Table 6. Example Digital Volume Settings DS691PP1 5

6 1. PIN DESCRIPTION DIF2(AD1/CDOUT) DEM(AD0/CS) DIF0(SDA/CDIN) DIF1(SCL/CCLK) VLC VD_FILT GND RMCK VLS SCLK SDIN LRCK RST AOUTB AOUTB+ BMUTEC VQ GND VA VBIAS+ AMUTEC AOUTA+ AOUTA TSTO 6 DS691PP1

7 Pin Name # Pin Description VLC 5 Control Interface Power (Input) Positive power for the hardware/software control interface VD_FILT 6 Regulator Voltage (Output) Filter connection for internal voltage regulator GND 7, 19 Ground (Input) Ground reference RMCK 8 Recovered Master Clock (Output) Outputs a master clock derived from LRCK VLS 9 Serial Audio Interface Power (Input) Positive power for the serial audio interface SCLK 10 Serial Clock (Input) Serial bitclock for the serial audio interface SDIN 11 Serial Audio Data Input (Input) Input for two s complement serial audio data LRCK 12 Left/Right Clock (Input) Determines which channel, Left or Right, is currently active on the serial audio data line TSTO 13 Test Output These pins need to be floating and not connected to any trace or plane. AOUTA+, AOUTB+, 14, 15, 22, 23 Differential Analog Outputs (Output) The full scale differential output level is specified in DAC Analog Characteristics Commercial (CZZ) on page 9. AMUTEC BMUTEC 16, 21 Mute Control (Output) Control signals for optional mute circuit. VBIAS 17 Positive Voltage Reference (Output) Positive reference voltage for the internal DAC VA 18 Analog Power (Input) Positive power supply for the analog section VQ 20 Quiescent Voltage (Output) Filter connection for internal quiescent voltage Reset (Input) When pulled low, device will power down and reset all internal registers to their default RST 24 settings. Control Port Definitions AD1/CDOUT 1 Address Bit 1 / Serial Control Data Out (I/O) Chip address bit 1 in I²C Mode or data output in SPI Mode AD0/CS 2 Address Bit 0 / Chip Select (Input) Chip address bit 0 in I²C Mode or Chip Select in SPI Mode SDA/CDIN 3 Serial Control Data In (I/O) Input/Output for I²C data. Input for SPI data SCL/CCLK 4 Serial Control Port Clock (Input) Serial clock for the control port interface StandAlone Definitions DIF0 DIF1 DIF2 1, 3, 4 DEM 2 Digital Interface Format (Input) Defines the required relationship between the Left Right Clock, Serial Clock, and Serial Audio Data Deemphasis (Input) Selects the standard 15 μs/50 μs digital deemphasis filter response for 44.1 khz sample rates Table 1. Pin Descriptions DS691PP1 7

8 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters Symbol Min Typ Max Units DC Power Supply Analog power VA V V Serial Audio Interface power VLS V Control Interface power VLC V Ambient Operating Temperature (Power Applied) Commercial (CZZ) T A C Automotive (DZZ) T A C ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground.(note 1) Parameters Symbol Min Max Units DC Power Supply Analog power VA V Serial Audio Interface power VLS V Control Interface power VLC V Input Current (Note 2) I in ±10 ma Digital Input Voltage Serial Audio Interface V INLS 0.3 VLS+ 0.4 V Control Interface V INLC 0.3 VLC+ 0.4 V Ambient Operating Temperature (power applied) T A C Storage Temperature T stg C Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. 8 DS691PP1

9 DAC ANALOG CHARACTERISTICS COMMERCIAL (CZZ) Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; T A = 25 C; input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT, VQ, and VBIAS and output circuit as shown in the typical connection diagram in Figure 7; Fs = 48 khz, 96 khz, and 192 khz; measurement bandwidth 10 Hz to 20 khz. Parameter Symbol Min Typ Max Unit VA=+5 V Singleended/Differential Dynamic Range (Note 1) 24bit AWeighted unweighted 95/103 92/ /109 98/106 16bit AWeighted unweighted 95/96 92/93 Total Harmonic Distortion + Noise (Note 1) 24bit 16bit VA=+3.3 V Dynamic Range (Note 1) 24bit AWeighted unweighted 16bit AWeighted unweighted Total Harmonic Distortion + Noise (Note 1) 24bit 16bit THD+N THD+N Note: 1. Onehalf LSB of triangular PDF dither is added to data 2. R L and C L represent the minimum resistance and maximum capacitance required for the s internal opamp to remain stable. See Figure 1 and Figure 2 for more details. 95/103 92/ /86 38/ /73 32/ /40 Singleended/Differential 101/109 98/106 95/96 92/ /93 78/86 38/ /73 32/ /40 VA=+5 to+3.3 V Interchannel Isolation (1 khz) 100 DC Accuracy Interchannel Gain Mismatch Gain Drift 400 ppm/ C Analog Output Full Scale Output Voltage Single Ended Vpp Full Scale Output Voltage Differential Vpp Quiescent Voltage V Q 0.5 VA VDC Max DC Current draw from an AOUT pin I OUTmax 10 μa Max Current draw from VQ I Qmax 100 μa Max ACLoad Resistance (Note 2) R L 3 kω Max Load Capacitance (Note 2) C L 100 pf Output Impedance Z OUT 100 Ω DS691PP1 9

10 DAC ANALOG CHARACTERISTICS AUTOMOTIVE (DZZ) Test conditions (unless otherwise specified): VLS = 1.35 V to 5.25 V, VLC = 3.14 V to 5.25 V, T A = 40 C to 85 C, input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT, VQ, and VBIAS and output circuit as shown in the typical connection diagram in Figure 7; Fs = 48 khz, 96 khz, and 192 khz; measurement bandwidth 10 Hz to 20 khz. Parameter Symbol Min Typ Max Unit VA=+4.75 V to V Singleended/Differential Dynamic Range (Note 1) 24bit AWeighted unweighted 95/103 92/ /109 98/106 16bit AWeighted unweighted 95/96 92/93 Total Harmonic Distortion + Noise (Note 1) 24bit 16bit THD+N 91 78/86 38/ /73 32/ /40 VA=+3.14 V to V Singleended/Differential Dynamic Range (Note 1) 24bit AWeighted unweighted 95/103 91/ /109 98/106 16bit AWeighted unweighted 95/96 92/93 Total Harmonic Distortion + Noise (Note 1) 24bit 16bit THD+N 84 91/93 78/86 38/ /73 32/ /40 VA=+3.14 to+5.25 V Interchannel Isolation (1 khz) 100 DC Accuracy Interchannel Gain Mismatch Gain Drift 400 ppm/ C Analog Output Full Scale Output Voltage Single Ended Vpp Full Scale Output Voltage Differential Vpp Quiescent Voltage V Q 0.5 VA VDC Max DC Current draw from an AOUT pin I OUTmax 10 μa Max Current draw from VQ I Qmax 100 μa Max ACLoad Resistance (Note 2) R L 3 kω Max Load Capacitance (Note 2) C L 100 pf Output Impedance Z OUT 100 Ω 10 DS691PP1

11 125 AGND AOUTx µf + R L C L Analog Output Capacitive Load C L (pf) Safe Operating Region Figure 1. Equivalent Output Load Resistive Load R L (kω ) Figure 2. Maximum Loading 20 DS691PP1 11

12 COMBINED INTERPOLATION & ONCHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Amplitude vs. Frequency plots of this data are available in the Filter Plots on page 36 Parameter Min Typ Max Unit Fast RollOff Passband (Note 3) 0.01 corner (Single Speed) Fs 0.1 corner (Double Speed) 0.42 Fs 0.2 corner (Quad Speed) 0.27 Fs 3 corner (All Speed Modes) Fs Frequency Response 10 Hz to 20 khz Single Speed Double Speed, Quad Speed StopBand Fs StopBand Attenuation (Note 4) 102 Total Group Delay (Fs = Output Sample Rate) 9.4/Fs s Intrachannel Phase Deviation ±0.56/Fs s Interchannel Phase Deviation 0 s Deemphasis Error (Note 5) Fs = 32 khz ±0.23 (Relative to 1 khz) Fs = 44.1 khz ±0.14 Fs = 48 khz ±0.09 Slow RollOff (Note 6) Passband (Note 3) 0.01 corner (Single Speed) Fs 0.1 corner (Double Speed) 0.37 Fs 0.2 corner (Quad Speed) 0.27 Fs 3 corner (All Speed Modes) Fs Frequency Response 10 Hz to 20 khz Single Speed Double Speed, Quad Speed StopBand.583 Fs StopBand Attenuation (Note 4) 64 Total Group Delay (Fs = Output Sample Rate) 6.5/Fs s Intrachannel Phase Deviation ±0.14/Fs s Interchannel Phase Deviation 0 s Deemphasis Error (Note 5) Fs = 32 khz ±0.23 (Relative to 1 khz) Fs = 44.1 khz ±0.14 Fs = 48 khz ±0.09 Notes: 3. Response is clock dependent. 4. The Measurement Bandwidth is from stopband to 3 Fs. 5. Deemphasis is available only in SingleSpeed Mode; Only 44.1 khz Deemphasis is available in StandAlone Mode. 6. Slow Rolloff interpolation filter is only available in Control Port Mode. 12 DS691PP1

13 SWITCHING SPECIFICATIONS SERIAL AUDIO INTERFACE Inputs: Logic 0 = GND; Logic 1 = VLS; C L =20pF Parameters Symbol Min Max Units RMCK Output Frequency (Note 7) MHz RMCK Output Duty Cycle % Input Sample Rate SingleSpeed Mode Fs khz DoubleSpeed Mode Fs khz QuadSpeed Mode Fs khz LRCK Duty Cycle (NonTDM Mode) % SCLK Frequency 55.3 MHz SCLK High Time t sckh 11 ns SCLK Low Time t sckl 11 ns SDIN Setup Time Before SCLK Rising Edge t ds 3 ns SDIN Hold Time After SCLK Rising Edge t dh 5 ns NonTDM Mode (refer to Figure 3) LRCK Edge to SCLK Rising Edge t lcks 16 ns SCLK Rising Edge to LRCK Edge t lckd 5 ns TDM Mode (refer to Figure 4) LRCK High Time t lrckh 163 ns SCLK Rising to LRCK Falling Edge t fsh 8 ns LRCK Rising Edge to SCLK Rising Edge t fss 5 ns Notes: 7. RMCK output frequency depends on the input LRCK frequency. See Section 4.1 and Section 4.2 for more details. t lrckh LRCK (input) t lckd t lcks t sckh t sckl LRCK (Input) t fss t fsh t sclkh t sclkl SCLK (input) SCLK (Input) t ds t dh t ds t dh SDIN (input) MSB MSB1 SDIN (Input) MSB MSB1 Figure 3. Serial Port Timing, NonTDM Mode Figure 4. Serial Port Timing, TDM Mode DS691PP1 13

14 SWITCHING CHARACTERISTICS CONTROL PORT I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VLC; C L =20pF. Parameter Symbol Min Max Unit SCL Clock Frequency f scl 100 khz RST Rising Edge to Start t irs 500 ns Bus Free Time Between Transmissions t buf 4.7 µs Start Condition Hold Time (prior to first clock pulse) t hdst 4.0 µs Clock Low time t low 4.7 µs Clock High Time t high 4.0 µs Setup Time for Repeated Start Condition t sust 4.7 µs SDA Hold Time from SCL Falling (Note 8) t hdd 0 µs SDA Setup time to SCL Rising t sud 250 ns Rise Time of SCL and SDA t rc, t rc 1 µs Fall Time SCL and SDA t fc, t fc 300 ns Setup Time for Stop Condition t susp 4.7 µs Acknowledge Delay from SCL Falling t ack ns Notes: 8. Data must be held for sufficient time to bridge the transition time, t fc, of SCL. RST t irs Stop Start Repeated Start t rd Stop t fd SDA t buf t hdst t high t hdst t fc t susp SCL t low t hdd t sud t ack t sust t rc Figure 5. Control Port Timing I²C Format 14 DS691PP1

15 SWITCHING CHARACTERISTICS CONTROL PORT SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VLC; C L =20pF Parameter Symbol Min Max Unit CCLK Clock Frequency f sclk 6 MHz RST Rising Edge to CS Falling t srs 500 ns CCLK Edge to CS Falling (Note 9) t spi 500 ns CS High Time Between Transmissions t csh 1.0 µs CS Falling to CCLK Edge t css 20 ns CCLK Low Time t scl 66 ns CCLK High Time t sch 66 ns CDIN to CCLK Rising Setup Time t dsu 40 ns CCLK Rising to DATA Hold Time (Note 10) t dh 15 ns Rise Time of CCLK and CDIN (Note 11) t r2 100 ns Fall Time of CCLK and CDIN (Note 11) t f2 100 ns Transition Time from CCLK to CDOUT Valid (Note 12) t scdov 100 ns Time from CS rising to CDOUT HighZ t cscdo 100 ns Notes: 9. t spi only needed before first falling edge of CS after RST rising edge. t spi = 0 at all other times. 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For F SCK < 1 MHz. 12. CDOUT should not be sampled during this time. RST t srs CS t spi t css t scl t sch t csh CCLK t r2 t f2 CDIN t dsu t dh CDOUT HiImpedance t scdov t scdov t cscdo Figure 6. Control Port Timing SPI Mode DS691PP1 15

16 DIGITAL CHARACTERISTICS Parameters Symbol Min Typ Max Units HighLevel Input Voltage VLC or VLS = 5.0 V V IH 0.7 V L V VLC or VLS = 3.3 V V IH 2.0 V VLS = 2.5 V V IH 1.7 V VLS = 1.5 V V IH 0.7 V L V HighLevel Input Voltage VLC or VLS = 5.0 V V IL 0.35 V L V VLC or VLS = 3.3 V V IL 0.8 V VLS = 2.5 V V IL 0.7 V VLS = 1.5 V V IL 0.25 V L V Input Leakage Current I in ±10 μa Input Capacitance 8 pf High Level Output Voltage (RMCK) I O = 2 ma (VLS 3.0V) V OH VLS1.0 V Low Level Output Voltage (RMCK) I O = 2 ma (VLS 3.0V) V OL 0.4 V RMCK Output Load Drive 10 pf Maximum MUTEC Drive Current 2 ma MUTEC HighLevel Output Voltage V OH VA V MUTEC LowLevel Output Voltage V OL 0 V POWER AND THERMAL CHARACTERISTICS Parameters Symbol Min Typ Max Units Power Supply Current Normal Operation (Note 13) VA= 5.0 V I A ma VA= 3.3 V I A ma VLS = VLC =5.0 V (Note 14) I LS 4 6 ma VLS = VLC =3.3 V (Note 14) I LS 2 5 ma VLS = VLC = 5.0 V (Note 15) I LC ma VLS = VLC = 3.3 V (Note 15) I LC ma Power Supply Current PowerDown State (Note 16) VA, VLS, VLC I pd 100 μa Power Dissipation Normal Operation (Note 13) VA = VLC= VLS = 5.0 V mw VA = VLC= VLS = 3.3 V mw Power Dissipation PowerDown State (Note 16) VA = VLC= VLS = 5.0 V 0.5 mw VA = VLC= VLS = 3.3 V 0.33 mw Power Supply Rejection Ratio (Note 17) (1 khz) PSRR 60 (60 Hz) PSRR 50 Notes: 13. Current consumption increases with increasing Fs within the range of a speed mode. Typ and Max values are based on highest Fs within a speed mode. Variance between speed modes is small. 14. I LS measured with no external loading on pin 7 (RMCK). 15. I LC measured with no external loading on pin 2 (SDA). 16. Powerdown mode is defined as RST pin = Low with all clock and data lines held static. 17. Valid with the recommended capacitor values on VFILT, VQ, and VBIAS+ as shown in the typical connection diagram in Figure DS691PP1

17 3. TYPICAL CONNECTION DIAGRAM +3.3 V or +5 V 0.1 µf + 10 µf *Optional for PopGuard Disable VLS *47 kω VA 18 VBIAS µf Digital Audio Source RMCK LRCK SCLK SDIN VD_FILT µf + 10 µf +1.5 V to +5 V 9 VLS 0.1 µf AMUTEC 16 AOUTA+ AOUTA Differential or Singleended Output Filter AOUTA +3.3 V to +5 V 5 VLC 0.1 µf BMUTEC 21 µ C/ Mode Configuration 24 RST 4 DIF1(SCL/CCLK) 3 DIF0(SDA/CDIN) AOUTB+ AOUTB Differential or Singleended Output Filter AOUTB 2 DEM(AD0/CS) 1 DIF2(AD1/CDOUT) TSTO GND GND N.C. VQ µf Figure 7. Typical Connection Diagram DS691PP1 17

18 4. APPLICATIONS 4.1 Sample Rate Range and Oversampling Mode Detect The device operates in one of three oversampling modes based on the input sample rate. In Control Port Mode, the allowed sample rate range in each mode will depend on how the FM[1:0] bits are configured. In StandAlone Mode, the sample rate range will be according to Table Sample Rate AutoDetect The AutoDetect feature is enabled by default. In this state, the will autodetect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges shown in Table 2. Sample rates outside the specified range for each mode are not supported when AutoDetect is enabled. Input Sample Rate (Fs) 30 khz 54 khz SingleSpeed Mode 60 khz 108 khz DoubleSpeed Mode 120 khz 216 khz QuadSpeed Mode Table 2. AutoDetect Mode In Control Port Mode, the AutoDetect feature can be disabled by the format bits in the control port register 02h. In this state, the will not autodetect the correct mode based on the input sample rate (Fs). The operational mode must then be set manually according to one of the ranges referred to in Section Sample rates outside the specified range for each mode are not supported. In StandAlone Mode it is not possible to disable autodetect of sample rates. 4.2 System Clocking The device requires external generation of the left/right (LRCK) and serial (SCLK) clocks. The left/right clock frequency is equal to the input sample rate (Fs). Refer to Section 4.3 for the required SCLKtoLRCK timing associated with the selected digital interface format, and Switching Specifications Serial Audio Interface on page 13 for the maximum allowed clock frequencies Recovered Master Clock (RMCK) The generates a highfrequency master clock (RMCK) which it derives from the LRCK input, available on the RMCK pin. In StandAlone Mode, the frequency of RMCK is equal to 256 x LRCK in SingleSpeed and DoubleSpeed Mode; and 128 x LRCK in QuadSpeed Mode. In ControlPort Mode, the frequency of the RMCK signal can be selected through register 08h (see Section 8.7 on page 34 for more details). 18 DS691PP1

19 4.3 Digital Interface Format The device will accept audio samples in 1 of 8 digital interface formats, as shown in Table 3 on page 24 for StandAlone Mode and Table 4 on page 29 for Control Port Mode. The desired serial audio interface format is selected via the DIF[2:0] bits in Control Port Mode (see Section 8.2.1), or the DIF[2:0] pins in StandAlone Mode (see Section 5.1). For illustrations of the required relationship between LRCK, SCLK and SDIN, see Figures 810. For all formats, SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to the Cirrus Logic Application Note AN282, The 2Channel Serial Audio Interface: A Tutorial, available at LRCK Left Channel Right Channel SCLK SDIN MSB LSB MSB LSB Figure 8. LeftJustified up to 24Bit Data LRCK Left Channel Right Channel SCLK SDIN LSB MSB MSB LSB Figure 9. I²S, up to 24Bit Data LRCK Left Channel Right Channel SCLK SDIN LSB MSB LSB MSB LSB Figure 10. RightJustified Data DS691PP1 19

20 4.3.1 TimeDivision Multiplex (TDM) Mode Four TDM interface modes are available that allow the to input stereo PCM data in one of 4 time slots. Figure 11 shows the serial port connections necessary to input 8channel TDM data into four devices, and the corresponding DIF[2:0] pin or registerbit settings required for each. Figure 12 shows the TDM data format for each of the four devices shown in Figure DIF[2:0] = 100 DIF[2:0] = 101 DIF[2:0] = 110 DIF[2:0] = 111 LRCK ILRCK LRCK LRCK SCLK ISCLK SCLK SCLK SDIN SDIN SDIN SDIN LRCK SCLK TDM_OUT TDM Source Figure 11. TDM Mode Connection Diagram LRCK 256 clks SCLK SDIN1 MSB MSB MSB MSB MSB MSB MSB MSB Slot 1, ch A Slot 1, ch B Slot 2, ch A Slot 2, ch B Slot 3, ch A Slot 3, ch B Slot 4, ch A Slot 4, ch B 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks Data MSB LSB zero Figure 12. TDM Mode Timing 20 DS691PP1

21 4.4 DeEmphasis The device includes onchip digital deemphasis. Figure 13 shows the deemphasis curve for Fs equal to 44.1 khz. The frequency response of the deemphasis curve will scale proportionally with changes in sample rate, Fs. Gain 0 T1=50 µs 10 T2 = 15 µs F1 F2 Frequency khz khz Figure 13. DeEmphasis Curve Note: Deemphasis is only available in SingleSpeed Mode. 4.5 Mute Control The mute control pins (AMUTEC and BMUTEC) go active during powerup initialization, reset, muting (see Section 8.4.3), and loss of LRCK. These pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occur in any singleended singlesupply system. Use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idlechannel noise and signaltonoise ratios which are only limited by the external mute circuit. 4.6 Recommended PowerUp Sequence StandAlone Mode 1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are fixed to the appropriate frequencies, as discussed in Section 4.2. In this state, the control port registers are reset to their default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low power state with VQ low for approximately 512 LRCK cycles in SingleSpeed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in QuadSpeed Mode). 3. The device will then initiate the power up sequence which lasts approximately 50 µs when the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of powerup timing. DS691PP1 21

22 4.6.2 Control Port Mode 1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate frequency, as discussed in Section 4.2. In this state, the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a lowpower state with VQ low. 3. Perform a control port write to a valid register prior to the completion of approximately 512 LRCK cycles in SingleSpeed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in QuadSpeed Mode). The desired register settings can be loaded while keeping the PDN bit set to Set the PDN bit to 0. This will initiate the powerup sequence, which lasts approximately 50 µs when the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of powerup timing. 4.7 Popguard Transient Control The uses a novel technique to minimize the effects of output transients during powerup and powerdown. This technology, when used with external DCblocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by singleended singlesupply converters. It is activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DCblocking capacitors PowerUp When the device is initially poweredup, the audio outputs, AOUTA and AOUTB, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DCblocking capacitors to charge to the quiescent voltage, minimizing audible powerup transients PowerDown To prevent audible transients at powerdown, the device must first enter its powerdown state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB. In their place, a softstart current sink is substituted which allows the DCblocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next poweron Discharge Time To prevent an audio transient at the next poweron, the DCblocking capacitors must fully discharge before turning on the power or exiting the powerdown state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the device must remain in the powerdown state is related to the value of the DCblocking capacitance and the output load. For example, with a 3.3 µf capacitor, the minimum powerdown time will be approximately 0.4 seconds. 22 DS691PP1

23 4.8 Analog Output and Filtering The Cirrus Application Note titled Design Notes for a 2Pole Filter with Differential Input, available as AN48 at discusses the secondorder Butterworth filter and differentialtosingleended converter that was implemented on the evaluation board, CDB4350. Figure 14 illustrates this implementation. If only singleended outputs from the are required, the passive output filter shown in Figure 15 can be used pf C0G 4.02 kω 1000 pf AOUTx 4.64 kω 392 Ω AOUTx kω 221 Ω C0G 2700 pf 22 μf 562 Ω 47 kω Analog Output AGND.015 μf C0G 1.37 kω 22 μf C0G Figure 14. Differential to SingleEnded Output Filter AOUTx µf + 10 kω 560 Ω 2200 pf Analog Output AGND Figure 15. Passive SingleEnded Output Filter 4.9 Grounding and Power Supply Arrangements As with any highresolution converter, the requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 7 shows the recommended power arrangements, with VA, VLC, and VLS connected to clean supplies. The use of split analog and digital ground planes is not recommended. However, if planes are split between digital ground and analog ground the GND pins of the should be connected to the analog ground plane. All signals, especially clocks, should be kept away from the VBIAS, VFILT, and VQ pins in order to avoid unwanted coupling into the DAC Capacitor Placement Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. Note: All decoupling capacitors should be referenced to analog ground. The CDB4350 evaluation board demonstrates the optimum layout and power supply arrangements. DS691PP1 23

24 5. STANDALONE OPERATION 5.1 Serial Port Format Selection The desired serial audio format is selected with the DIF2, DIF1 and DIF0 pins. For an explanation of the required relationship between the LRCK, SCLK and SDIN, see Figures 810. For all formats, SDIN is valid on the rising edge of SCLK. TDM Mode requires the selection of which stereo pair time slot is used to output data as shown in Table 3 and Figure DeEmphasis Control DIF2 DIF1 DIF0 DESCRIPTION FORMAT FIGURE LeftJustified, up to 24bit data I²S, up to 24bit data RightJustified, 16bit data RightJustified, 24bit data TDM slot TDM slot TDM slot TDM slot Table 3. Digital Interface Format StandAlone Mode When pulled to VLC, the DEM pin activates the 44.1 khz deemphasis filter. When pulled to GND, the DEM pin turns off the deemphasis filter. 5.3 Popguard Transient Control In StandAlone Mode, Popguard is enabled by default. Popguard can be defeated in StandAlone Mode by placing a 47 kω resistor between RMCK and VLS. 24 DS691PP1

25 6. CONTROL PORT OPERATION The control port is used to load all the internal register settings (see Register Description on page 29). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port can operate in I²C or SPI mode. 6.1 MAP Auto Increment The device has a MAP (memory address pointer) autoincrement capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for consecutive writes or reads. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of consecutive registers. 6.2 I²C Mode In the I²C Mode, data is clocked into and out of the bidirectional serial control data line, SDA, by the serial control port clock, SCL (see Figure 16 for the clock to data relationship). There is no CS pin. AD1 and AD0 enable the user to alter the chip address (10010[AD1][AD0][R/W]) and should be tied to VLC or GND as required before powering up the device. SPI Mode will be selected if the device ever detects a high to low transition on the AD0/CS pin after powerup I²C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Switching Characteristics Control Port I²C Format on page Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be The sixth and seventh bit must match the settings of the AD1 and AD0 pins respectively, and the eighth must be 0 (the eighth bit of the address byte is the R/W bit). 2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus I²C Read To read from the device, follow the procedure below while adhering to the control port switching specifications in Switching Characteristics Control Port I²C Format on page Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be The sixth and seventh bits must match the setting of the AD1 and AD0 pins, respectively, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the DS691PP1 25

26 MAP or the default address (see Section 6.4.2) if an I²C read is the first operation performed on the device. 3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK. 4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the desired registers are read; then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write instructions, followed by step 1 of the I²C Read section. If no further reads from other registers are desired, initiate a STOP condition to the bus SCL CHIP ADDRESS MAP BYTE DATA DATA +1 DATA +n SDA AD1 AD0 R/W INC ACK ACK ACK START Figure 16. Control Port Timing, I²C Mode ACK STOP 6.3 SPI Mode In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK (see Figure 17 for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select signal and is used to control SPI writes to the control port. When the device detects a hightolow transition on the AD0/CS pin after powerup, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK SPI Write To write to the device, follow the procedure below while adhering to the control port switching specifications in Switching Characteristics Control Port SPI Format on page Bring CS low. 2. The address byte on the CDIN pin must then be (R/W =0). 3. Write to the memory address pointer, MAP. This byte points to the register to be written. 4. Write the desired data to the register pointed to by the MAP. 5. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high 26 DS691PP1

27 6.3.2 SPI Read To read from the device, follow the procedure below while adhering to the values specified in Switching Characteristics Control Port SPI Format on page Bring CS low. 2. The address byte on the CDIN pin must then be (R/W =1). 3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the SPI write operation. 4. If the INCR bit (see Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK to read from multiple consecutive registers. Bring CS high when reading is complete. 5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further reads from other registers are desired, bring CS high. CS CCLK CDIN CHIP CHIP ADDRESS MAP DATA ADDRESS R/W MSB LSB R/W byte 1 byte n CDOUT High Impedance MSB LSB MSB LSB MAP = Memory Address Pointer, 8 bits, MSB first Figure 17. Control Port Timing, SPI Mode 6.4 Memory Address Pointer (MAP) INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP INCR (Auto Map Increment Enable) Default = 0 0 Disabled 1 Enabled MAP (Memory Address Pointer) Default = 0000 DS691PP1 27

28 7. REGISTER QUICK REFERENCE Addr Function h Device and RevID DeviceID4 DeviceID3 DeviceID2 DeviceID1 DeviceID0 RevID2 RevID1 RevID0 default h Mode Control Reserved DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0 default h Volume, Mixing, and Inversion Control VOLB=A INVERTA INVERTB Reserved ATAPI3 ATAPI2 ATAPI1 ATAPI0 4h 5h 6h 7h 8h default Mute Control AMUTE Reserved MUTEC MUTE_A MUTE_B Reserved Reserved Reserved A=B default Channel A Volume VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 Control default Channel B Volume VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 Control default Ramp and Filter SZC1 SZC0 RMP_UP RMP_DN Reserved FILT_SEL Reserved Reserved Control default Misc. Control PDN Reserved FREEZE POPG_EN RMCK_ CTRL1 RMCK_ CTRL0 R_ SELECT1 R_ SELECT0 default DS691PP1

29 8. REGISTER DESCRIPTION ** All register access is R/W unless specified otherwise** 8.1 Device and Revision ID Register 01h Device4 Device3 Device2 Device1 Device0 Rev2 Rev1 Rev Function: This register is ReadOnly. It is decoded as follows: Rev Register 01h contents A 1111,0000 B 1111,0001 C2 1111, Mode Control Register 02h Reserved DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM Digital Interface Format (DIF[2:0]) Bits 64 Function: These bits select the interface format for the serial audio input. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 810. DIF2 DIF1 DIF0 Description Format Figure LeftJustified, up to 24bit data 0 (Default) I²S, up to 24bit data RightJustified, 16bit data RightJustified, 24bit data TDM slot TDM slot TDM slot TDM slot Table 4. Digital Interface Formats DS691PP1 29

30 8.2.2 DeEmphasis Control (DEM[1:0]) Bits 32 Default = 0 00 No Deemphasis khz Deemphasis khz Deemphasis khz Deemphasis Function: Gain 0 10 T1=50 µs T2 = 15 µs Selects the appropriate digital filter to maintain the standard 15 μs/50 μs digital deemphasis filter response at 32, 44.1 or 48 khz sample rates. (See Figure 18) Note: Mode Deemphasis is only available in SingleSpeed F1 F2 Frequency khz khz Figure 18. DeEmphasis Curve Functional Mode (FM[1:0]) Bits 10 Default = Auto speed mode detect 01 SingleSpeed Mode (30 to 54 khz sample rates) 10 DoubleSpeed Mode (50 to 108 khz sample rates) 11 QuadSpeed Mode (100 to 216 khz sample rates) Function: Selects the required range of input sample rates or auto speed mode. 8.3 Volume Mixing and Inversion Control Register 03h VOLB=A INVERT_A INVERT_B Reserved ATAPI3 ATAPI2 ATAPI1 ATAPI Channel A Volume = Channel B Volume (VOLB=A) Bit 7 Function: When set to 0 (default), the AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes. When set to 1, the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored Invert Signal Polarity (INVERT_A) Bit 6 Function: When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats. 30 DS691PP1

31 8.3.3 Invert Signal Polarity (INVERT_B) Bit 5 Function: When set to 1, this bit inverts the signal polarity of channel B. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 30 Default = 1001 AOUTA=aL, AOUTB=bR (Stereo) Function: The implements the channel mixing functions of the ATAPI CDROM specification. Refer to Table 5 and Figure 19 for additional information. Left Channel Audio Data A Channel Volume Control MUTE AoutA Σ Σ Right Channel Audio Data B Channel Volume Control MUTE AoutB Figure 19. ATAPI Block Diagram ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0 AOUTA AOUTB MUTE MUTE MUTE br MUTE bl MUTE b[(l+r)/2] ar MUTE ar br ar bl ar b[(l+r)/2] Table 5. ATAPI Decode DS691PP1 31

32 ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0 AOUTA AOUTB 8.4 Mute Control Register 04h AutoMute (AMUTE) Bit 7 Function: When set to 1 (default), the DigitaltoAnalog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or 1. A single sample of nonstatic data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0, this function is disabled AMUTEC = BMUTEC (MUTEC A=B) Bit 5 Function: When set to 0 (default) the AMUTEC and BMUTEC pins operate independently. When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3 Function: al MUTE al br al bl al b[(l+r)/2] a[(l+r)/2] MUTE a[(l+r)/2] br a[(l+r)/2] bl a[(l+r)/2] b[(l+r)/2] Table 5. ATAPI Decode AMUTE Reserved MUTEC A=B MUTE_A MUTE_B Reserved Reserved Reserved When set to 1, the DigitaltoAnalog converter output will mute. The quiescent voltage on the output will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default), this function is disabled. 32 DS691PP1

33 8.5 Channel A & B Volume Control Register 05h & 06h VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL Digital Volume Control (VOL[7:0]) Bits 70 Default = 00h (0 ) Function: The Digital Volume Control registers allow independent control of the signal levels in 1/2 increments from 0 to Volume settings are decoded as shown in Table 6. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/ Ramp and Filter Control Register 07h Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 76 Default = 10 Binary Code Decimal Value Volume Setting Table 6. Example Digital Volume Settings SZC1 SZC0 RMP_UP RMP_DN Reserved FILT_SEL Reserved Reserved SZC1 SZC0 Description 0 0 Immediate Change 0 1 Zero Cross 1 0 Soft Ramp 1 1 Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp PCM Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 steps, from the current level to the new level at a rate of 1 per 8 left/right clock periods. DS691PP1 33

34 Soft Ramp and Zero Cross Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 steps and be implemented on a signal zero crossing. The 1/8 level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel Soft Volume RampUp after Error (RMP_UP) Bit 5 Function: When set to 1 (default), an unmute will be performed after executing a filter mode change, after LRCK is lost, and after changing the Functional Mode. This unmute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate unmute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit Soft RampDown before Filter Mode Change (RMP_DN) Bit 4 Function: When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit Interpolation Filter Select (FILT_SEL) Bit 2 Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off. The specifications for each filter can be found in the Combined Interpolation & OnChip Analog Filter Response on page 12, and response plots can be found in Figures 22 through Misc. Control Register 08h PDN Reserved FREEZE POPG_EN RMCK_CTRL1 RMCK_CTRL0 R_SELECT1 R_SELECT Power Down (PDN) Bit 7 Function: When set to 1 the entire device will enter a lowpower state and the contents of the control registers will be retained. The powerdown bit defaults to 0 on powerup. 34 DS691PP1