TDA1675A VERTICAL DEFLECTION CIRCUIT SYNCHRONISATION CIRCUIT

Transcription

1 TDA7A ERTICAL DEFLECTION CIRCUIT. SYNCHRONISATION CIRCUIT. ESD PROTECTED PRECISION OSCILLATOR AND RAMP GENERATOR POWER PUT AMPLIFIER WITH HIGH CURRENT CAPABILITY FLYBACK GENERATOR OLTAGE REGULATOR. PRECISION PULSE GENERATOR THERMAL SHUT DOWN PROTECTION CRT SCREEN PROTECTION CIRCUIT WHICH BLANKS THE BEAM CURRENT IN THE EENT OF LOSS OF ERTICAL DE- FLECTION CURRENT DESCRIPTION The TDA7A is a monolithic integrated circuit in -lead Multiwatt package. It is a full performance and very efficient vertical deflection circuit intended for direct drive of the yoke of 0 o colour T picture tubes. It offers a wide range of applications also in portable CTs, B&W Ts, monitors and displays. MULTIWATT (Plastic Package) ORDER CODE : TDA7A PIN CONNECTIONS (top view) FLYBACK SUPPLY PUT AMPLIFIER INPUT (-) AMPLIFIER INPUT () RAMP PUT RAMP GENERATOR GROUND ADJUSTMENT OSCILLATOR INPUT OSCILLATOR OSCILLATOR AMPLIFIER SUPPLY AMPLIFIER PUT Tab connected to Pin 8 7A-0.EPS September 99 /

2 TDA7A BLOCK DIAGRAM S C f BLANK GENERATOR AND CRT PROTECTION OLTAGE REGULATOR FLYBACK GENERATOR OSCILLATOR RAMP GENERATOR R CLOCK PULSE R POWER AMP. - R R e Ly Ry Iy 7 BUFFER STAGE THERMAL PROTECTION R a R c C a LIN R b C c R d C b R f 7A-0.EPS ABSOLUTE MAXIMUM RATINGS S Supply oltage at Pin, Flyback Peak oltage Sync. Input oltage 0, Power Amplifier Input oltage S - 0 oltage at Pin S I O Output Current (non repetitive) at t = ms A IO Output Peak Current at f = 0Hz t > 0µs A I O Output Peak Current at f = 0Hz t 0 µs. A I Pin Peak-to-peak Flyback Current at f = 0Hz, tfly.ms A I Pin D.C. Current at < 00 ma P tot Maximum Power Dissipation at T case 0 o C 0 W T stg, T j Storage and Junction Temperature - 0, 0 o C 7A-0.TBL THERMAL DATA R TH(j-c) Thermal Resistance Junction-case Max. R TH(j-a) Thermal Resistance Junction-ambient Max. 0 7A-0.TBL /

3 TDA7A DC ELECTRICAL CHARACTERISTICS (S =, Tamb = o C, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Fig. I Pin quiescent current I = 0 ma b - I 9 Ramp generator bias current 9 = µa b - I9 Ramp generator current 9 = 0 ; - I7 = 0µA µa b I 9 I 9 Ramp generator non linearity 9 = 0 to, - I 7 = 0µA 0. % b I Pin quiescent current ma b Quiescent output voltage S =, R a =.kω, R b = kω S =, R a = 90Ω, R b = kω L Output saturation voltage to ground I =.A,. c H Output saturation voltage to supply - I =.A.. d Oscillator virtual ground 0. b 7 Regulated voltage at pin 7 - I 7 = 0µA.. 7 b 7 Regulated voltage drift with supply m S voltage S = to b Amplifier input () reference voltage...7 b Blanking output saturation voltage I = 0 ma a Pin saturation voltage to ground I = 0 ma. a a 7A-0.TBL Figure : DC Test Circuit. Figure a Figure b S I S I I I 8 7 -I 9 I R a R b 7A-0.EPS A B 7kΩ I 9 -I 7 9 I 7kΩ kω 7A-0.EPS Figure c Figure d S S I H 0 8 L 0 8 -I 8 7A-0.EPS 8 7A-0.EPS /

4 TDA7A AC ELECTRICAL CHARACTERISTICS (Refer to A.C. test circuit of fig., Tamb = o C, S =, f = 0Hz, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit I S Supply Current I Y = A PP 9 ma I Sync Input Current Required to Sync 00 µa Flyback oltage Iy = App 0 Peak-to-peak Oscillator Sawtooth oltage I = 0 I = 00µA 0TH(L) Start Scan Level of the Input Ramp.8 t FLY Flyback Time Iy = App 0. ms t BLANK Blanking Pulse Duration f o = 0Hz, T j = 7 o C f o = 0Hz, T j = 7 o C f o Free Running Frequency = 7.kΩ, = 0nF, T j = 7 o C =.kω, = 0nF, T j = 7 o C ms ms Hz Hz f Synchronization Range I = 00µA, T j = 7 o C Hz Tj Junction Temperature for Thermal Shut-down o C ON Peak-to-peak Output Noise mpp 7A-0.TBL Figure : AC Test Circuit N00 0µF 00µA t blank IN S.kΩ 000µF GND t f I y /fo.7kω.7kω (FREQ.) t blank /fo t sync. 7.kΩ A B Co SERICE SWITCH S (R ) o 0.µF kω S 80kΩ 0kΩ kΩ TDA 7A kω 00kΩ LINEARITY GND kω /fo.ω 0.µF 0Ω 0 0thL 7µF 70Ω.kΩ 0.8Ω I Y 00µF R f /fo 0mH.9Ω R f I y 7A-07.EPS /

5 TDA7A Figure : Application Circuit for Small Scree 90 o CT Set (R y = Ω ; L y = 0 mh ; I y = 0.8 A PP) N00 0µF - PULSE IN C R.7kΩ SERICE SWITCH R 0kΩ S 7.kΩ % 0nF R kω S R 0kΩ RT C 70µF R 90kΩ 00kΩ C TDA 7A C kω R C D C RT LINEARITY 00kΩ C7 R7 90Ω R9.Ω 0.µF R8 0Ω C8.kΩ R0 C9 7µF 0 R 0Ω 000µF R.Ω 7A-08.EPS The value depends on the characteristics of the CRT. The value shown is indicative only. TYPICAL PERFORMANCE S Minimum supply voltage I S Supply current 0 ma t FLY Flyback time 0.7 ms t BLKG Banking time. ms fo Free running frequency. Hz PTOT Power dissipation. W R TH(heatsink) Thermal resistance of the heatsink for Tamb = 0 o C and Tj max = 0 o C for T amb = 0 o C and T j max = 0 o C Worst case condition. 7A-0.TBL /

6 TDA7A Figure : Application Circuit for 0 o CT Set (Ry = 9.Ω ; Ly =. mh ; Iy =. APP) N00 0µF - PULSE IN C R.7kΩ SERICE SWITCH R 0kΩ S 7.kΩ % 0nF R kω S R 80kΩ RT C 70µF R 70kΩ 0kΩ C TDA 7A C kω R C D C RT LINEARITY 00kΩ C7 R7.kΩ R9.Ω 0.µF R8 0Ω C8.kΩ R0 C9 7µF 0 R 0Ω 00µF R.Ω 7A-09.EPS The value depends on the characteristics of the CRT. The value shown is indicative only. TYPICAL PERFORMANCE S Minimum supply voltage. I S Supply current 8 ma t FLY Flyback time ms t BLKG Banking time. ms f O Free running frequency. Hz P TOT Power dissipation.7 W RTH(heatsink) Thermal resistance of the heatsink for Tamb = 0 o C and T j max = 0 o C for T amb = 0 o C and T j max = 0 o C Worst case condition... 7A-0.TBL /

7 TDA7A Figure : Application Circuit for 0 o CT Set (Ry =.9Ω ; Ly = 0 mh ; Iy =.9 APP) N00 0µF - PULSE IN C R.7kΩ SERICE SWITCH R 0kΩ S 7.kΩ % 0nF R kω S R 80kΩ RT C 000µF R 0kΩ 0kΩ C TDA 7A C kω R C D C RT LINEARITY 00kΩ C7 R7 kω R9.Ω 0.µF R8 0Ω C8.kΩ R0 C9 7µF 0 R 0Ω 00µF R 0.8Ω 7A-0.EPS The value depends on the characteristics of the CRT. The value shown is indicative only. TYPICAL PERFORMANCE S Minimum supply voltage I S Supply current 8 ma t FLY Flyback time 0. ms t BLKG Banking time. ms f O Free running frequency. Hz P TOT Power dissipation. W RTH(heatsink) Thermal resistance of the heatsink for Tamb = 0 o C and T j max = 0 o C for T amb = 0 o C and T j max = 0 o C Worst case condition A-07.TBL 7/

8 TDA7A Figure : PC Board and Components Layout for the Application Circuits of Figures, and ( : scale) S TDA 7A R R R C RT C C R9 C R D R RT C7 C C R R7 R8 C8 C C9 R0 R R GND Iy IN TEST S BLANKGND 7A-.EPS APPLICATION INFORMATION (Refer to the block diagram) Oscillator and sync gate (Clock generation) The oscillator is obtained by means of an integrator driven by a two threshold circuit that switches high or low so allowing the charge or the discharge of under constant current conditions. The Sync input pulse at the Sync gate lowers the level of the upper threshold and than it controls the period duration. A clock pulse is generated. Pin is the inverting input of the amplifier used as integrator. Pin Pin Pin is the output of the switch driven by the internal clock pulse generated by the threshold circuits. is the output of the amplifier. is the input for sync pulses (positive) Ramp generator and buffer stage A current mirror, the current intensity of which can be externally adjusted, charges one capacitor producing a linear voltage ramp. The internal clock pulse stops the increasing ramp by a very fast discharge of the capacitor a new voltage ramp is immediately allowed. 8/