TDA1675A VERTICAL DEFLECTION CIRCUIT SYNCHRONISATION CIRCUIT

Size: px

Start display at page:

Download "TDA1675A VERTICAL DEFLECTION CIRCUIT SYNCHRONISATION CIRCUIT"

Antony McDowell
5 years ago
Views:

1 TDA675A VERTICAL DEFLECTION CIRCUIT. SYNCHRONISATION CIRCUIT. ESD PROTECTED PRECISION OSCILLATOR AND RAMP GENERATOR POWER OUTPUT AMPLIFIER WITH HIGH CURRENT CAPABILITY FLYBACK GENERATOR VOLTAGE REGULATOR. PRECISION BLANKING PULSE GENERATOR THERMAL SHUT DOWN PROTECTION CRT SCREEN PROTECTION CIRCUIT WHICH BLANKS THE BEAM CURRENT IN THE EVENT OF LOSS OF VERTICAL DE- FLECTION CURRENT DESCRIPTION The TDA675A is a monolithic integrated circuit in 5-lead Multiwatt package. It is a full performance and very efficient vertical deflection circuit intended for direct drive of the yoke of 0 o colour TV picture tubes. It offers a wide range of applications also in portable CTVs, B&W TVs, monitors and displays. MULTIWATT 5 (Plastic Package) ORDER CODE : TDA675A PIN CONNECTIONS (top view) FLYBACK SUPPLY BLANKING OUTPUT AMPLIFIER INPUT (-) AMPLIFIER INPUT (+) RAMP OUTPUT RAMP GENERATOR GROUND HEIGHT ADJUSTMENT OSCILLATOR SYNC. INPUT OSCILLATOR OSCILLATOR AMPLIFIER SUPPLY AMPLIFIER OUTPUT Tab connected to Pin 8 675A-0.EPS September 99 /

2 TDA675A BLOCK DIAGRAM + +V S BLANKING OUT 2 + C f BLANK GENERATOR AND CRT PROTECTION VOLTAGE REGULATOR FLYBACK GENERATOR 5 6 R o C o OSCILLATOR RAMP GENERATOR R CLOCK PULSE R + POWER AMP. - R2 2 R e Ly Ry Iy YOKE 7 SYNC. SYNC. BUFFER STAGE THERMAL PROTECTION R a R c + C a LIN R b + C c HEIGHT R d C b R f 675A-02.EPS ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VS Supply Voltage at Pin 5 V V, V 2 Flyback Peak Voltage 65 V V 5 Sync. Input Voltage 20 V V, V 2 Power Amplifier Input Voltage V S - 0 V V Voltage at Pin V S I O Output Current (non repetitive) at t = 2ms A IO Output Peak Current at f = 50Hz t > 0µs 2 A I O Output Peak Current at f = 50Hz t 0 µs.5 A I5 Pin 5 Peak-to-peak Flyback Current at f = 50Hz, tfly.5ms A I 5 Pin 5 D.C. Current at V < V 00 ma P tot Maximum Power Dissipation at T case 60 o C 0 W T stg, T j Storage and Junction Temperature - 0, + 50 o C 675A-0.TBL THERMAL DATA Symbol Parameter Value Unit R TH(j-c) Thermal Resistance Junction-case Max. R TH(j-a) Thermal Resistance Junction-ambient Max A-02.TBL 2/

3 TDA675A DC ELECTRICAL CHARACTERISTICS (VS = 5V, Tamb = 25 o C, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Fig. I2 Pin 2 quiescent current I = ma b - I 9 Ramp generator bias current V 9 = µa b - I9 Ramp generator current V9 = 0 ; - I7 = 20µA µa b I 9 I 9 Ramp generator non linearity V 9 = 0 to 5V, - I 7 = 20µA 0.2 % b I Pin quiescent current 25 5 ma b V Quiescent output voltage V S = 5V, R a = 2.2kΩ, R b = kω V S = 5V, R a = 90Ω, R b = kω VL Output saturation voltage to ground I =.2A,. V c V H Output saturation voltage to supply - I =.2A V d V Oscillator virtual ground 0.5 V b V 7 Regulated voltage at pin 7 - I 7 = 20µA V b V 7 Regulated voltage drift with supply mv V V S voltage S = 5 to 5V 2 V b V Amplifier input (+) reference voltage...7 V b V Blanking output saturation voltage I = 0 ma V a V 5 Pin 5 saturation voltage to ground I 5 = 20 ma.5 V a V V a 675A-0.TBL Figure : DC Test Circuit. Figure a Figure b V S I 5 V 5 V S V I 2 + I I V 8V V 7 -I 9 I R a R b V 675A-0.EPS A B V V 75kΩ 5 0 V I 9 -I 7 V9 2 I 7kΩ 22kΩ 675A-0.EPS Figure c Figure d V S V S 2 2 +I V H V V L V I 8V 675A-05.EPS 8V 675A-06.EPS /

4 TDA675A AC ELECTRICAL CHARACTERISTICS (Refer to A.C. test circuit of fig. 2, Tamb = 25 o C, VS = 2V, f = 50Hz, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit I S Supply Current I Y = 2A PP 295 ma I 5 Sync Input Current Required to Sync 00 µa V Flyback Voltage Iy = 2App 50 V V Peak-to-peak Oscillator Sawtooth Voltage I 5 = 0 I5 = 00µA V0TH(L) Start Scan Level of the Input Ramp.85 V t FLY Flyback Time Iy = 2App 0.6 ms t BLANK Blanking Pulse Duration f o = 50Hz, T j = 75 o C f o = 60Hz, T j = 75 o C f o Free Running Frequency R o = 7.5kΩ, C o = 0nF, T j = 75 o C R o = 6.2kΩ, C o = 0nF, T j = 75 o C V V.7 ms ms 6 Hz Hz f Synchronization Range I 5 = 00µA, T j = 75 o C 6 Hz Tj Junction Temperature for Thermal Shut-down 5 o C VON Peak-to-peak Output Noise 5 mvpp 675A-0.TBL Figure 2 : AC Test Circuit N00 220µF 00µA t blank BLANKING OUT SYNC. IN +V S 2.kΩ 5 000µF 2 5 GND t f I y /fo V.7kΩ.7kΩ (FREQ.) t blank /fo t sync. 7.5kΩ A B Co V SERVICE SWITCH S (R ) o 0.µF 5kΩ S2 6 80kΩ 220kΩ HEIGHT kΩ TDA 675A 56kΩ 00kΩ LINEARITY GND 2 kω /fo 2.2Ω 0.22µF 20Ω V 0 V 0thL 7µF 270Ω 2.kΩ 0.82Ω I Y 2200µF R f /fo YOKE 0mH 5.9Ω R f I y 675A-07.EPS /

5 TDA675A Figure : Application Circuit for Small Scree 90 o CTV Set (R y = 5Ω ; L y = 0 mh ; I y = 0.82 A PP) N00 220µF - 5V SYNC. PULSE IN C R.7kΩ SERVICE SWITCH R 0kΩ BLANKING OUT C o +V S R o 7.5kΩ % 0nF 5% R2 5kΩ S R 50kΩ RT HEIGHT C2 5V 70µF R5 90kΩ 00kΩ C TDA 675A C5 56kΩ R6 C6 D C 2 RT2 LINEARITY 00kΩ C7 R7 90Ω 2% R9 2.2Ω 0.22µF R8 20Ω C8 2.kΩ R0 2% C9 7µF 0V 5% R 0Ω 000µF 25V R2 2.2Ω YOKE 675A-08.EPS The value depends on the characteristics of the CRT. The value shown is indicative only. TYPICAL PERFORMANCE Symbol Parameter Value Unit V S Minimum supply voltage 25 V I S Supply current 0 ma t FLY Flyback time 0.7 ms t BLKG Banking time. ms fo Free running frequency.5 Hz PTOT Power dissipation 2. W R TH(heatsink) Thermal resistance of the heatsink for Tamb = 60 o C and Tj max = 0 o C for T amb = 60 o C and T j max = 20 o C Worst case condition A-05.TBL 5/

6 TDA675A Figure : Application Circuit for 0 o CTV Set (Ry = 9.6Ω ; Ly = 2.6 mh ; Iy =.2 APP) N00 220µF - 25V SYNC. PULSE IN C R.7kΩ SERVICE SWITCH R 0kΩ BLANKING OUT C o +V S R o 7.5kΩ % 0nF 5% R2 5kΩ S R 80kΩ RT HEIGHT C2 5V 70µF R5 70kΩ 220kΩ C TDA 675A C5 56kΩ R6 C6 D C 2 RT2 LINEARITY 00kΩ C7 R7.2kΩ 2% R9 2.2Ω 0.22µF R8 20Ω C8 2.kΩ R0 2% C9 7µF 0V 5% R 0Ω 500µF 6V R2.2Ω YOKE 675A-09.EPS The value depends on the characteristics of the CRT. The value shown is indicative only. TYPICAL PERFORMANCE Symbol Parameter Value Unit VS Minimum supply voltage 22.5 V I S Supply current 85 ma t FLY Flyback time ms t BLKG Banking time. ms f O Free running frequency.5 Hz P TOT Power dissipation 2.7 W RTH(heatsink) Thermal resistance of the heatsink for Tamb = 60 o C and T j max = 0 o C for T amb = 60 o C and T j max = 20 o C Worst case condition A-06.TBL 6/

7 TDA675A Figure 5 : Application Circuit for 0 o CTV Set (Ry = 5.9Ω ; Ly = 0 mh ; Iy =.95 APP) N00 220µF - 25V SYNC. PULSE IN C R.7kΩ SERVICE SWITCH R 0kΩ BLANKING OUT C o +V S R o 7.5kΩ % 0nF 5% R2 5kΩ S R 80kΩ RT HEIGHT C2 5V 000µF R5 560kΩ 220kΩ C TDA 675A C5 56kΩ R6 C6 D C 2 RT2 LINEARITY 00kΩ C7 R7 kω 2% R9 2.2Ω 0.22µF R8 20Ω C8 2.kΩ R0 2% C9 7µF 0V 5% R 0Ω 2200µF 6V R2 0.82Ω YOKE 675A-0.EPS The value depends on the characteristics of the CRT. The value shown is indicative only. TYPICAL PERFORMANCE Symbol Parameter Value Unit VS Minimum supply voltage 2 V I S Supply current 285 ma t FLY Flyback time 0.6 ms t BLKG Banking time. ms f O Free running frequency.5 Hz P TOT Power dissipation. W RTH(heatsink) Thermal resistance of the heatsink for Tamb = 60 o C and T j max = 0 o C for T amb = 60 o C and T j max = 20 o C Worst case condition A-07.TBL 7/

8 TDA675A Figure 6 : PC Board and Components Layout for the Application Circuits of Figures, and 5 ( : scale) S R o TDA 675A R 2 C o R R C RT C C R9 C6 R D R5 RT2 C7 C C5 R6 R7 R8 C8 C2 C9 R0 R2 R GND SYNC. Iy IN TEST YOKE V S BLANKGND OUT 675A-.EPS APPLICATION INFORMATION (Refer to the block diagram) Oscillator and sync gate (Clock generation) The oscillator is obtained by means of an integrator driven by a two threshold circuit that switches R o high or low so allowing the charge or the discharge of C o under constant current conditions. The Sync input pulse at the Sync gate lowers the level of the upper threshold and than it controls the period duration. A clock pulse is generated. Pin is the inverting input of the amplifier used as integrator. Pin 6 Pin Pin 5 is the output of the switch driven by the internal clock pulse generated by the threshold circuits. is the output of the amplifier. is the input for sync pulses (positive) Ramp generator and buffer stage A current mirror, the current intensity of which can be externally adjusted, charges one capacitor producing a linear voltage ramp. The internal clock pulse stops the increasing ramp by a very fast discharge of the capacitor a new voltage ramp is immediately allowed. 8/

9 TDA675A The required value of the capacitance is obtained by means of the series of two capacitors Ca and Cb, which allow the linearity control by applying a feedback between the output of the buffer and the tapping from C a and C b. Pin 7 The resistance between pin 7 and ground defines the current mirror current and than the height of the scanning. Pin 9 is the output of the current mirror that charges the series of Ca and Cb. This pin is also the input of the buffer stage. Pin 0 is the output of the buffer stage and it is internally coupled to the inverting input of the power amplifier through R. Pin 2 Power amplifier This amplifier is a voltage-to-current power converter, the transconductance of which is externally defined by means of a negative current feedback. The output stage of the power amplifier is supplied by the main supply during the trace period, and by the flyback generator circuit during the most of the duration of the flyback time. The internal clock turns off the lower power output stage to start the flyback. The power output stage is thermally protected by sensing the junction temperature and then by putting off the current sources of the power stage. Pin 2 is the inverting input of the amplifier. An external network, R a and R b, defines the DClevel across C y so allowing a correct centering of the output voltage. The series network Rc and Cc, in conjunction with R a and R b, applies at the feedback input I2 a small part of the parabola, available across Cy, and AC feedback voltage, taken across R f. The external components R c, R a and R d, produce the linearity correction on the output scanning currentiy and their values must be optimized for each type of CRT. Pin is the non-inverting input. At this pin the non-inverting input reference voltage supplied by the voltage regulator can be measured. A capacitor must be connected to increase the performances from the noise point of view. Pin is the output of the power amplifier and it drives the yoke by a negative slope current ramply. Re and the Boucherot cell are used to stabilize the power amplifier. The supply of the power output stage is forced at this pin. During the trace time the supply voltage is obtained from the main supply voltage V S by a diode, while during the retrace time this pin is supplied from the flyback generator. Flyback generator This circuit supplies both the power amplifier output stage and the yoke during the most of the duration of the flyback time (retrace). The internal clock opens the loop of the amplifier and lets pin floating so allowing the rising of the flyback. Crossing the main supply voltage at pin, the flyback pulse front end drives the flyback generator in such a way allowing its output to reach and overcome the main supply voltage, starting from a low condition forced during the trace period. An integrated diode stops the rising of this output increase and the voltage jump is transferred by means of capacitor Cf at the supply voltage pin of the power stage (pin 2). When the current across the yoke changes its direction, the output of the flyback generator falls down to the main supply voltage and it is stopped by means of the saturated output darlington at a high level. At this time the flyback generator starts to supply the power output amplifier output stage by a diode inside the device. The flyback generator supplies the yoke too. Later, the increasing flyback current reaches the peak value and then the flyback time is completed: the trace period restarts. The output of the power amplifier (pin ) falls under the main supply voltage and the output of the flyback generator is driven for a low state so allowing the flyback capacitor Cf to restore the energy lost during the retrace. Pin 5 is the output of the flyback generator that, when driven, jumps from low to high condition. An external capacitor C f transfers the jump to pin 2 (see pin 2). Blanking generator and CRT protection This circuit is a pulse shaper and its output goes high during the blanking period or for CRT protection. The input is internally driven by the clock pulse that defines the width of the blanking time 9/

10 TDA675A when a flyback pulse has been generated. If the flyback pulse is absent (short cirucit or open cirucit of the yoke), the blanking output remains high so allowing the CRT protection. Pin is an open collector output where the blanking pulse is available. Voltage regulator The main supply voltage V S, is lowered and regulated internally to allow the required reference voltages for all the above described blocks. Pin is the main supply voltage input V S (positive). Pin 8 is the GND pin or the negative input of V S Figure 8 : 2.5 V H Output Saturation Voltage to Supply versus Output Peak Current (V) V S = 5V I Y (App) A-.EPS Figure 7 :.5 V L Output Saturation Voltage to Ground vs. Peak Output Current (V) Figure 9 : 2 P tot (W) Maximum allowable Power Dissipation vs. Ambient Temperature V S = 5V 2 6 R th = C/W R th = 8 C/W R th = 2 C/W INFINITE HEATSINK I Y (App) A-2.EPS T amb ( C) A-.EPS MOUNTING INSTRUCTIONS The power dissipated in the circuit must be removed by adding an external heatsink. Thanks to the MULTIWATT package attaching the heatsink is very simple, a screw or a compression Figure 0 : Mounting Examples spring (clip) being sufficient. Between the heatsink and the package, it is better to insert a layer of silicon grease, to optimize the thermal contact; no electrical isolation is needed between the two surfaces. 675A-5.IMG 0/

11 TDA675A PACKAGE MECHANICAL DATA : 5 PINS - PLASTIC MULTIWATT PMMUL5V.EPS Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A B C D 0.09 E F G G H H L L L L L L M M S S Dia MUL5V.TBL Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 99 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2 C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I 2 C Patent. Rights to use these components in a I 2 C system, is granted provided that the system conforms to the I 2 C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. /

12 This datasheet has been downloaded from: Datasheets for electronic components.

TDA1675A VERTICAL DEFLECTION CIRCUIT SYNCHRONISATION CIRCUIT

TDA1675A VERTICAL DEFLECTION CIRCUIT SYNCHRONISATION CIRCUIT TDA7A ERTICAL DEFLECTION CIRCUIT. SYNCHRONISATION CIRCUIT. ESD PROTECTED PRECISION OSCILLATOR AND RAMP GENERATOR POWER PUT AMPLIFIER WITH HIGH CURRENT CAPABILITY FLYBACK GENERATOR OLTAGE REGULATOR. PRECISION