WIDE-BAND code-division multiple access (W-CDMA),

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY A 123-mW W-CDMA Uplink Baseband Receiver IC With Beamforming Capability Hsi-Pin Ma, Member, IEEE, Ming-Luen Liou, and Tzi-Dar Chiueh, Senior Member, IEEE Abstract In this paper, architecture and circuit design of a beamforming baseband receiver IC for uplink W-CDMA communication systems is presented. In the proposed receiver, a four-antenna-element beamformer and a four-finger RAKE combiner are adopted to exploit both spatial diversity and path diversity receiving. To minimize the size and power consumption of the receiver, a latch-based 1024-tap complex delay line is custom designed for the matched filter in the channel estimation circuit. The receiver chip was fabricated in a m n-well CMOS single-poly quadruple-metal technology. The minimum supply voltage with the chip running at the nominal MHz clock rate is measured at 2.15 V. The chip has an area of 6 mm by 6.3 mm and a power consumption of about 123 mw. Index Terms Beamformer, diversity receiving, RAKE receiver, wide-band code-division multiple access (W-CDMA). I. INTRODUCTION WIDE-BAND code-division multiple access (W-CDMA), one of the major specifications for Third-Generation (3G) mobile communication systems, is proposed by the Third Generation Partnership Project (3GPP). This specification intends to achieve two major goals simultaneously: 1) provision of wide-area mobility, such as urban and suburban areas, hilly and mountainous areas, and indoor environments, and 2) support for a wide range of bearer services with different data rates, e.g., 144 kb/s in vehicular, 384 kb/s in outdoor low-mobility, and 2 Mb/s in indoor environments. The 3GPP W-CDMA specification adopts several techniques to achieve the aforementioned goals [1] [4]. Orthogonal variable spreading factor (OVSF) codes allow the base station to assign appropriate data rates to service different transmission requirements. A pilot channel is included to serve as a reference during the channel estimation procedure, which estimates critical parameters needed in RAKE combining and carrier synchronization. Moreover, several advanced receiving techniques that increase receiver signal-to-interference-and-noise Manuscript received May 13, 2003; revised December 15, This work was supported in part by the National Science Council, Taiwan, R.O.C., under Grant NSC E and by the MOE Program for Promoting Academic Excellence of the Universities under Grant 89E-FA Hsi-Pin Ma was with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. He is now with the Department of Electrical Engineering, National Tsing Hua University, HsinChu, Taiwan 300, R.O.C. Ming-Luen Liou was with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. He is now with MediaTek Inc., HsinChu, Taiwan 300, R.O.C. Tzi-Dar Chiueh is with the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. ( chiueh@cc.ee.ntu.edu.tw). Digital Object Identifier /JSSC ratio (SINR) can be implemented, thus achieving higher system capacity. Multi-user detection (MUD) and adaptive array antenna are two examples of the advanced CDMA receiving techniques that can be exploited. MUD [5], [6] estimates channel characteristics of each user by monitoring the respective dedicated pilot channel and uses this information to eliminate multiple-access interference (MAI). Unfortunately, great hardware complexity prevents it from wide adoption. On the other hand, adaptive array antenna techniques [7] take advantage of the spatial diversity in an antenna array and can also greatly improve receiver performance [8] [12]. However, complex matrix operations often found in conventional adaptive array antenna algorithms make them unsuitable for low-complexity hardware implementation. To this end, we will adopt a simplified adaptive array antenna technique called spatial-signature beamformer that requires much less hardware complexity [13], [14]. In this paper, a baseband receiver architecture for uplink W-CDMA systems with adaptive beamforming capability and its low-power, low-complexity VLSI implementation are presented. The proposed receiver consists of a channel estimator that tracks channel parameters for signal recovery, a RAKE combiner that gathers multipath information for better signal detection, and a carrier synchronization circuit that compensates for carrier frequency offset. In addition, a robust and low-complexity beamformer that utilizes the spatial signature [13], [14] of the desired signal is adopted to enhance system SINR performance. A low-complexity correlator-based beam searcher computes the beamformer weights using simple arithmetic operations rather than the complex matrix operations that are needed in conventional adaptive array antenna algorithms. The following is a summary of the proposed chip: baseband processor for uplink W-CDMA receiving operating at 3.84 Mchip/s; operation at MHz sampling rate (four samples per chip) at a supply voltage of 2.15 V; provision for both spatial diversity (beamforming) and path diversity (RAKE combiner); low-power latch-file memory structure for the digital matched filter in the channel estimator; low-complexity correlator-based beam searcher that supports real-time adaptive beamforming based on a four-element antenna array; special phase/frequency estimation hardware for fast carrier synchronization. The paper is organized as follows. Section II describes the 3GPP uplink baseband physical channel specifications. Sec /04$ IEEE

2 786 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 Fig. 1. Uplink frame structure for W-CDMA systems. (a) PRACH is for random access establishment. (b) PCPCH is for UE to send packetized data to BS. (c) DPCCH and DPDCH are the dedicated channels for transmission from UE to BS. tion III focuses on the architecture of the proposed W-CDMA chip. The functional simulation results are shown in Section IV. Detailed circuit design for the proposed architecture is discussed in Section V. In Section VI, the layout of the proposed chip and its measurement results are presented. Section VII then concludes this paper. II. W-CDMA UPLINK STANDARDS The 3GPP Radio Access Network (RAN) specification release 1999 is based on the CDMA scheme that uses the direct-sequence spread-spectrum technique. With a bandwidth of 5 MHz, the adopted chip rate is 3.84 Mchips/s. Furthermore, two levels of spreading, channelization and scrambling, are used in the standard. In the uplink, channelization is used to uncouple data channels assigned to a particular user by spreading each data channel with a distinct channelization code, and in order to support variable data rates, OVSF Walsh codes are chosen for this purpose. On the other hand, scrambling is aimed at distinguishing users inside the same cell, and either long codes or short codes can be used depending on whether or not advanced reception techniques are adopted [3]. Four types of uplink physical channels are defined in 3GPP W-CDMA specification release 1999 [1]: Physical Random Access Channel (PRACH), Physical Common Packet Channel (PCPCH), Dedicated Physical Data Channel (DPDCH), and Dedicated Physical Control Channel (DPCCH). PRACH and PCPCH are common channels and are shared among all user equipments (UE) in one cell. For dedicated communication between a UE and a base station (BS), two types of physical channels (DPDCH and DPCCH) are assigned by the BS to the UE upon granting its random access request. PRACH is used to carry the random access request message from the UEs and the slotted Aloha scheme is adopted. Once a BS receives a random access request from a UE, the BS will issue a random access grant message to that UE. This grant message contains essential information for the UE to commence communication with the BS through DPDCH and DPCCH. PCPCH is for transmission of short packet data, and the Digital Sense Multiple Access with Collision Detection (DSMA-CD) approach with fast acquisition indication is used in PCPCH. Fig. 1(a) and (b) illustrate the access frame structures for PRACH and PCPCH, respectively. The DPCCH is a control channel, containing a pilot signal, transport format combination indicator (TFCI, which is data rate information about the current DPDCH frame), feedback information (FBI), and transmission power control (TPC) information. The DPDCH consists of information bit stream from the upper layers, and the number of DPDCHs assigned to a particular UE can be more than one according to the services it has requested. Fig. 1(c) shows the frame structure of the two dedicated physical channels. Note that the frame structure is similar to that of the message part of PRACH and PCPCH. Therefore, a generic receiver can be designed for the reception of DPCH and the message parts of PRACH and PCPCH. The spreading factor (SF) of the DPCCH and the message parts of PRACH and PCPCH is fixed at 256, while that of the DPDCH can be set to, where is an integer from 0 to 6. In other words, the

3 MA et al.: W-CDMA UPLINK BASEBAND RECEIVER IC WITH BEAMFORMING CAPABILITY 787 Fig. 2. Proposed uplink receiver architecture for the W-CDMA system. spreading factor in DPDCH ranges from 256 to 4 and the possible DPDCH physical bit rates are 15, 30, 60, 120, 240, 480, and 960 kb/s. III. CHIP ARCHITECTURE A. Overview Fig. 2 shows the proposed uplink baseband receiver architecture for the W-CDMA communication system. Note that four omnidirectional antennas are adopted in the proposed receiver for beamforming. The proposed receiver consists of a beamformer, a beam searcher, a channel estimator, a RAKE combiner, and a carrier synchronization circuit. The beamformer gathers in-phase ( ) and quadrature-phase ( ) inputs from four antenna elements and combines them using weights calculated from the beam searcher so as to direct the effective beam to a specific direction for better reception. The channel estimator is used to generate, per symbol period, delays and phases that correspond to four most significant transmission paths in the multipath channel from the UE to the BS. The estimated information is then provided to other blocks in the receiver to facilitate signal demodulation. The RAKE combiner takes in the delays and weights estimated by the channel estimator and uses the maximal ratio combining (MRC) method [15] to generate the receiver outputs. The carrier synchronization circuit also utilizes the phase information estimated by the channel estimator, and with this phase information it employs a phase-locked loop to achieve phase and frequency synchronization. B. Configurations The proposed baseband receiver architecture can, with proper configuration, be used for the reception of signals from all four uplink physical channels mentioned in Section II. This is due to the similarity in the transmission scheme of the preamble part of PRACH and that of PCPCH, as well as that between the PRACH/PCPCH message part (data and control part) and the DPCH (DPDCH and DPCCH). During the preamble detection, since no detailed information about the channel characteristics is available, the channel estimator works alone while the beamformer and the phase de-rotator of the carrier synchronization circuit are both disabled. Moreover, the RAKE combiner is also disabled. In this configuration, the channel estimator continuously finds, in each symbol period, the most significant peak in the -channel matched filter output and passes it along to a preamble signature detector, which searches for a preamble. At the same time, the beam searcher computes moving averages in outputs of all four correlators, and derives four beamformer weights. In addition, the phase estimator in the carrier synchronization block estimates the carrier frequency offset by accumulating phase difference between peaks in consecutive preamble symbols. As soon as a random access request is identified, the aforementioned two blocks can immediately provide the correct and timely information needed in ensuing data reception. After initial channel estimation, the receiver obtains approximate parameters of the beamformer, the carrier synchronization loop, and the RAKE combiner. During reception of the PRACH/PCPCH message parts or the DPCCH/DPDCH signal, the beamformer begins to operate with the estimated weights. In addition, a phase de-rotator block is placed after the beamformer to close the carrier synchronization loop. Following beamforming and carrier phase/frequency correction, the RAKE combiner demodulates information bits in the channel (data in the PRACH/PCPCH message parts or DPDCH). Meanwhile, the channel estimator, the carrier synchronization block, and the beam searcher continuously track channel fluctuations through detecting pilot signals in the channel (control information in the PRACH/PCPCH message parts or DPCCH). The proposed beamformer architecture works best in the nondiffused case where there is a single dominant path. However, this may not always be valid. The third receiver configuration is designed with a view to tackling the case when the signal arrives in a more diffused fashion. A magnitude monitor is incorporated in the channel estimator. If the present primary path being tracked falls into a deep fade, the magnitude in the primary peak of the matched filter output falls below a pre-defined threshold, and the beamformer will be disabled. Only one antenna input is used and the channel estimator works without beamforming and the whole system still functions correctly. Since the beam searcher will always adaptively calculate the weights of the beamformer with the delays calculated by channel estimator, when a dominant path reappears, i.e., the magnitude in the primary peak of the matched filter output exceeds the threshold continuously over several symbols, the beamformer can be enabled again.

4 788 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 TABLE I SIGNAL WORD LENGTH USED IN THE PROPOSED W-CDMA RECEIVER IV. FUNCTIONAL SIMULATION A. Simulation Using Fixed-Point Arithmetic The main objective of functional simulation using fixed-point arithmetic is to determine signal word length in the receiver. With fixed-point arithmetic and truncation, the associated quantization noise will degrade the receiver performance. Hence, the criterion is to minimize the hardware complexity by choosing the smallest possible word length while keeping the overall communication performance at an acceptable level. Since it will take excessively long simulation time if the bit error rate (BER) is used as the performance index, we thus use the output signal-to-noise ratio (SNR) as a gauge of the system performance [16]. After careful examination of the simulation results (e.g., Fig. 3 shows results of using different word lengths in the matched filter input), we then decide the word lengths of several variables in the proposed W-CDMA uplink baseband receiver, which are listed in Table I. B. Performance Simulation To verify the validity of the proposed fixed-point-arithmetic receiver architecture, system performance through resimulation is evaluated. The simulation environment is established as follows. First, the 3GPP W-CDMA transmitter output signal is passed through a channel model with prescribed impairments, and then the channel output is fed to the proposed W-CDMA receiver for functional simulation. The adopted channel model is based on the two-ray and four-ray Doppler fading test channels specified in the 3GPP standard with a respective speed of 3 km/h and 120 km/h [17]. Moreover, a carrier frequency offset of 200 Hz (0.1 ppm relative to the 2-GHz RF frequency) is included in the channel model. To model the spatial characteristics of wireless channels, a vectorized channel derived from extending the original multiuser scalar channel model is also constructed and it is used in the functional verification of the proposed beam searcher and beamformer. Each user has several paths, each of which arrives at a random angle distributed with an angle spread (20 as suggested in [5] for urban cells). All users have a spreading factor of 64 (60-kb/s channel bit rate). Furthermore, imperfect power control is assumed and the power of the desired user can go as low as 10 db relative to that of the interfering users, and the input SNR used is 0 db. Following the terminology in the standard, the two slow-fading two-ray channels and the fast-fading four-ray fading channel are named type-i, type-ii, and type-iii channels, respectively. According to the standard base station testing specification [17], the required BER for a rate convolutional-coded Fig. 3. Fixed-point arithmetic simulation results in determining the input word length of the complex matched filter. (SNR) is the SNR at the receiver input. scheme with information bit rate 12.2 kb/s (equivalent to 60-kb/s uncoded channel bit rate used in the simulation) is 10. Since uncoded performance of the simulation results is reported, an uncoded BER performance between 10 and 10 is deemed acceptable. Fig. 4 shows the simulated system performance under different noise and multiple access interference (MAI) levels. The notation (B) in the legend refers to the cases when the beamformer with four antenna inputs is turned on. In Fig. 4(a), it is clear that the proposed receiver can provide a satisfactory uncoded receiver performance (BER on the order of 10 ) at SNR around 10 db (about 8-dB with a processing gain of 18 db) under the worst case type-iii channel. In addition, Fig. 4(b) exhibits how beamforming can suppress MAI and thus greatly increase the system capacity (number of allowable users). It is clear that up to about 30 users can be accommodated in the slow-fading two-ray type-i test channel when the beamformer is turned on. For the worst case type-iii test channel, approximately interfering users can be tolerated even though the desired user s power is as low as 10 db relative to that of the interfering users. V. CIRCUIT DESIGN In this section, the circuit design of the major building blocks in the proposed receiver is described. A. Channel Estimator The channel estimator in the W-CDMA baseband receiver plays a key role in signal receiving and it is the receiver block

5 MA et al.: W-CDMA UPLINK BASEBAND RECEIVER IC WITH BEAMFORMING CAPABILITY 789 combiner and the beam searcher. Second, the dump time for the corrleators in the RAKE combiner and the beam searcher also depends on the delays. Third, the values of these four legitimate peaks are used to calculate the weights in the RAKE combiner according to where is the polarity of the current pilot bit. To avoid false alarm, all peaks with magnitude less than a predetermined threshold are discarded. Moreover, for other control information in the control channel (DPCCH), such as TFCI, FBI, and TPC, the channel estimator can provide the quadrature-phase component of the largest peak found in each symbol. (1) Fig. 4. System performance simulation results under three multipath fading channels with and without beamforming. (a) BER versus SNR. (b) BER versus the number of interfering users. Type-I channel is a two-ray 3-km/h Doppler fading channel with one ray 10 db lower than the other in power; Type-II channel is a two-ray 3-km/h Doppler fading channel with two equal-power rays; type-iii channel is a four-ray 120-km/h Doppler fading channel. The curves labeled with (B) refer to the cases that the beamformer is turned on. that has the highest complexity. It consists of a complex matched filter, a magnitude calculator, and a peak detector, as shown in Fig. 5. The channel estimator provides crucial control information to the other blocks in the chip, such as the RAKE combiner, the carrier synchronization circuit, the beam searcher, and the code generator. The core of the channel estimator is a complex matched filter that detects the PN code waveform of the pilot signal in PRACH, PCPCH, or DPCCH. This complex matched filter despreads the input signal, and a peak detector then finds the four most significant peaks in the matched filter output. The values of these four peaks along with their respective delays are computed and provided to other blocks and used in several different ways. First, the delays will control the start timing of the code generator whose output codes are used in the RAKE B. Latch File and PN Multiplier Due to its large spreading factor (and thus large number of taps), the complex matched filter expends a significant amount of the chip s resources, both in layout area and power consumption. To conserve area and power, a latch-based memory structure (shown in Fig. 6) replaces the delay line in a direct-form digital filter [18]. Note that the memory block is of a two-dimensional array structure, composed of rows and columns. Rows and columns are addressed progressively by two ring counters, one for rows and one for columns. These two counters together address the set of latches to store the latest data sample. To operate under a low supply voltage and to conserve power, modified low-voltage TSPC registers based on [19] and [20] were adopted in these two ring counters. In the conventional tapped-delay-line matched filter, all data in the delay-line registers are shifted every clock cycle while the coefficients (chips in the PN code) stay fixed. In the proposed matched filter, we used a techniques proposed in [18] that moves the code instead of the data. This design has two advantages. First, the complexity is greatly reduced, because the latch cell in the latch file is about half the size of a D-type flip-flop, which is often used as a one-bit delay element. Since there are 8192 delay elements, the reduction in area is significant. Second, the power consumption is also greatly reduced. In the conventional architecture, there will be at most 8192 data transitions in each clock cycle, while there are only at most 128 data transitions in the proposed matched filter. The complex multiplier in the matched filter (PN multiplier) is designed with a view to reducing circuit complexity. Since there are only four possible values in the complex coefficient of a tap, the four possible products are first computed using four adders and the final true product is selected using several 4-to-1 multiplexers. After complex multiplication, 256 complex products, 5 bits in the real part and 5 bits in the imaginary part, need to be added. Two giant Wallace tree adders (WTA), one for the real part and one for the imaginary part, are used for this purpose. Moreover, proper pipelining registers are inserted in the two adders in order to limit the critical path delay. C. Carrier Synchronization Block Due to channel fading and local oscillator frequency mismatch, the phase/frequency of the received baseband signal must be compensated appropriately. Therefore, a carrier

6 790 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 Fig. 5. Block diagram of the channel estimator. Fig. 6. Latch file used in the complex matched filter. synchronization circuit, shown in Fig. 7, is adopted in the proposed receiver. The proposed circuit operates in two modes: acquisition and tracking. In the acquisition mode, which happens during the reception of the PRACH/PCPCH preamble part, the phasor difference between two consecutive symbols is accumulated as (2) where is the accumulated phasor difference at symbol, and is the value of the primary peak at symbol. The frequency offset estimate can be obtained by normalizing the accumulated phasor difference. During the interval when the phasor difference is being accumulated and the frequency offset estimated [computed by block (a) in Fig. 7], the carrier synchronization loop is open. Moreover, the initial frequency offset and initial phase at the instant when the loop is closed are calculated by block (b) in Fig. 7. Next, in the tracking mode, a phase detector calculating the phase of the primary peak in the matched filter output, a conventional proportional-and-integrate type loop filter averaging the phase error [Fig. 7, block (c)], and a numerical-controlled oscillator (NCO) [Fig. 7, block (d)] is adopted in this digital phase-locked loop for carrier tracking [21]. This mode is enabled during the PCPCH message part, PRACH message part, and DPCCH/DPDCH reception. Note that all registers except the one shaded in gray operate at symbol rate. The shaded register, being the phase accumulator of the NCO, operates at sample rate to output the phase of the derotating phasor. D. RAKE Combiner The RAKE combiner is responsible for the data channel ( channel, ) detection in the proposed receiver. As an important module in the CDMA communication systems, the RAKE combiner usually consists of several correlators for collecting signal components corresponding to significant multi-paths and then combines these components in a coherent fashion so as to maximize the signal to interference and noise ratio. In the proposed receiver, as shown in Fig. 8(a), four PN-code correlators with respective delays derived from the channel estimator are employed to despread the incoming sample-rate signal into four symbol-rate data. By aligning these despreaded data with the -axis and then weighted summing the aligned

7 MA et al.: W-CDMA UPLINK BASEBAND RECEIVER IC WITH BEAMFORMING CAPABILITY 791 Fig. 7. Circuit diagram for carrier synchronization. Block (a) is the phasor accumulator for estimation of the initial carrier frequency offset. Block (b) is used to calculate the initial carrier frequency offset and initial phase. Block (c) is a loop filter that averages the incoming phase error. Block (d) is the NCO. Fig. 8. Circuit diagram of (a) proposed RAKE receiver; (b) PN code correlator; (c) beam searcher; (d) beamformer. data (maximum ratio combining, MRC), the soft-decision output with the optimal SINR can be obtained [15]. However, although four RAKE fingers are provided, the actual number of fingers enabled can be adjusted according to the channel condition. The correlator circuit operates at sample rate and is shown in Fig. 8(b). In the figure, the dump signal is only high for one sample period in the symbol boundary. Thus, most of the time when the dump signal is low, the correlator accumulates correlation values for the current symbol, and the correlation value for the previous symbol is held in the output register. When the dump signal goes high, the content of the accumulator register will be dumped to the output register and the accumulator itself will be cleared, ready for the next accumulation.

8 792 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 E. Beamformer/Beam Searcher In addition to path diversity exploited by the RAKE combiner, spatial diversity can also be exploited by an antenna array with beamforming algorithms [7]. In the proposed receiver, a correlator-based beamformer/beam searcher structure is adopted. The beam searcher, as shown in Fig. 8(c), consists of four identical modules, one for each antenna. Each of them utilizes a complex pilot-pn-code despreader (correlator) synchronized with the most significant peak to estimate the magnitude and phase of the pilot signal from one antenna. Since the four antennas are only apart ( is the wavelength of the carrier), the four despreaded outputs of the pilot signal are of about the same magnitude, yet quite different phases. In a multipath fading environment, these four correlator output phasors make up the spatial signature of the vector channel from the transmitter to the four antennas in the receiver [13], [14]. Therefore, as in the RAKE combiner, these four despreaded signals can be constructively combined if they can all be aligned to a certain reference before the summation. The beamformer weight is then set to the complex conjugate of the th component in the spatial signature obtained during PRACH reception. In addition, to provide robustness against changing spatial channel profile, the beamformer weights are updated at symbol rate using moving average of the complex conjugate of the latest spatial signature estimate and are given by Fig. 9. Die photo of the proposed W-CDMA uplink baseband receiver IC. TABLE II SUMMARY OF THE W-CDMA UPLINK BASEBAND RECEIVER IC (3) where is the beamformer weight for the th antenna at symbol, and is the th component of the spatial signature at symbol. The beamformer, as shown in Fig. 8(d), then uses these weights to combine the four complex-valued baseband signals from the antenna array, effectively steering the antenna beam pattern toward the desired direction. VI. PHYSICAL DESIGN AND MEASUREMENT RESULTS A. Layout Design Before proceeding to the layout design, the area of each building block was estimated and I/O pins were assigned according to the signal flow. Moreover, several test nodes have been incorporated, making it easy to observe signals inside the chip. The proposed uplink baseband receiver IC was fabricated in a m n-well one-ploy four-metal (1P4M) CMOS technology. The die size is about mm and it is housed in a 144-pin package. The microphotograph and the summary of the chip are shown in Fig. 9 and Table II, respectively. The latch file and the PN multiplier were designed using full-custom layout in order to save die area. All other blocks were designed by a cell-based approach and the layout of these blocks were generated by an automatic place and route tool. B. Measurement Results The fabricated chip was tested using a pattern generator and a logic analyzer. At a clock rate of MHz (equivalent to 3.84 Mchip/s as specified by the 3GPP standard), the chip can function correctly under a supply voltage range from 2.15 to 3 V. The power dissipation for each supply voltage at this clock rate is measured and plotted in Fig. 10. It is found that the minimum power dissipation is mw at a supply voltage of 2.15 V. In addition, the power dissipation of the IC was measured separately for three parts: Right stands for the right half of the chip and includes the latch file, the PN multiplier, and the WTA of the matched filter; Clock stands for the clock buffer; and Left represents the rest of the chip. Table III shows a comparison of the two-dimensional latchbased matched filter with several reported digital matched filters. Due to a wide diversity in technology, frequency, supply voltage, and tap number, it is quite difficult to make a fair and exact comparison. However, using normalized power given by we find that the latch-based matched filter in the proposed WCDMA receiver IC outperforms all previous implementations. More testing on the functional performance of the chip were conducted. Input patterns with different sampling clock offsets were fed to the chip and the output signal to noise

9 MA et al.: W-CDMA UPLINK BASEBAND RECEIVER IC WITH BEAMFORMING CAPABILITY 793 TABLE III COMPARISONS BETWEEN PREVIOUS REPORTED DIGITAL MATCHED FILTERS WITH THIS WORK. Fig. 10. Dissipation power versus supply voltage. ratios recorded. Fig. 11(a) shows the measured output SNR for different sampling clock offsets (in ppm), indicating that the chip can sustain about 50-ppm clock offset while keeping the degradation in SNR below 3 db. Another measurement that used different levels of carrier frequency offset was done and Fig. 11(b) depicts the measured output SNR for different carrier frequency offsets (in ppm). It can be seen that up to 2-ppm carrier frequency offset can be tolerated, much larger than the 0.1-ppm specified in the 3GPP standard. Finally, input patterns with typical MAI arrival angle spread were fed to the IC and the computed beamformer weights were recorded. Fig. 12 depicts the antenna array gain pattern computed from the measured beamformer weights. In the figure, directions of ten interfering users and one desired user are also plotted. Obviously, the main beam points to the desired user, and the MAI from other directions is suppressed. VII. CONCLUSION In this paper, a digital beamformer receiver architecture for 3G W-CDMA uplink systems is proposed. We have integrated a real-time correlator-based beamformer, a matched-filter-based channel estimator, a four-finger RAKE combiner, and a carrier synchronization loop into a single chip. The correlator-based Fig. 11. Measured output SNR. (a) For different clock offsets. The clock rate is MHz. (b) For different frequency offsets. The carrier frequency is 2 GHz. beam searcher reduces considerable complexity when compared with other conventional direction of arrival (DOA)-based smart antenna approaches and it still achieves very good performance. Moreover, a new TSPC register and a latch-based complex matched filter greatly reduce not only the required complexity but also the power consumption. This receiver was fabricated in a m n-well CMOS 1P4M technology, and the IC was tested and shown to be functionally correct. The chip can operate at MHz from a 2.15-V power supply and it consumes 123 mw.

10 794 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 Fig. 12. Measured beam pattern in the environment of ten interfering users. ACKNOWLEDGMENT The authors greatly appreciate the Chip Implementation Center (CIC) of the National Science Council, Taiwan, R.O.C., for the fabrication and measurement of the proposed chip. They also thank the anonymous reviewers for their valuable suggestions that greatly improved this paper. REFERENCES [1] Physical Channels and Mapping of Transport Channels Onto Physical Channels (FDD), Oct GPP TSG RAN WG1. [2] Multiplexing and Channel Coding (FDD), Oct GPP TSG RAN WG1. [3] Spreading and Modulation (FDD), Oct GPP TSG RAN WG1. [4] Physical Layer Procedures (FDD), Oct GPP TSG RAN WG1. [5] S. Verdú, Multiuser Detection. Cambridge, U.K.: Cambridge Univ. Press, [6] D. Koulakiotis and A. H. Aghvami, Data detection techniques for DS/CDMA mobile systems: A review, IEEE Personal Commun., vol. 7, pp , June [7] T. S. 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Euromicro Symp. Digital System Design, 2002, pp Hsi-Pin Ma (M 98) was born in Nantou, Taiwan, R.O.C., in He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1995 and 2002, respectively. Since 2003, he has been with the Department of Electrical Engineering, National Tsing Hua University, HsinChu, Taiwan, where he is currently an Assistant Professor. His research interests include baseband signal processing of communication systems and related VLSI design. Ming-Luen Liou was born in Taipei, Taiwan, R.O.C., on February 15, He received the B.S. and the Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, in 1994 and 2001, respectively. He was in military service from 1996 to He is currently a Member of Technical Staff with MediaTek Inc., HsinChu, Taiwan. His research interests include baseband signal processing algorithm and low-power digital ASIC implementations of communication systems. Tzi-Dar Chiueh (S 87 M 90 SM 03) was born in Taipei, Taiwan, R.O.C., on July 3, He received the B.S.E.E. degree from the National Taiwan University, Taipei, Taiwan, in He received the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 1986 and 1989, respectively. Since 1989, he has been with the Department of Electrical Engineering, National Taiwan University, Taipei, where he is currently a Professor. His research interests include IC design for digital communication systems and analog neuromorphic systems.