Keywords Single electronics, tunnelling, Coulomb Blockade, tunnel junctions and Nano-Hybrid-Counter

Transcription

1 Volume 5, Issue 4, April 2015 ISSN: X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: Single Electron Transistor Made Nano-Hybrid-Counters for Advanced High Speed Computing Dr. J. Gope * Manisha Giri, Manisha Sarkhel Dept. of ECE, Camellia School of Engg. & Tech, WBUT, India Sanjay Bhadra Dept. of EE, Camellia School of Engg. & Tech, BUT, India Abstract Single Electron Transistor (SET) technology insights numerous possibilities of achieving ultra high functional density and exceptionally low power dissipation paralleled to conventional CMOS technology. In this work the authors enumerated the implementation of SET based Nano-Hybrid-Counter circuit based on logic realizations using SET. The schematic diagram along with simulation results is presented here. The novel circuit endorse excellent trade off when compared to conventional hybrid counters. Keywords Single electronics, tunnelling, Coulomb Blockade, tunnel junctions and Nano-Hybrid-Counter I. INTRODUCTION Single electronics initiated as an incipient meadow of rising interest from the point of view of both academic and industry owing to its applications to modern and future electronics [1]. Single electronics employs the transfer of single electron tunnelling properties to exemplify binary data values. The attainment of the Single Electron Devices is that it involves considerably less power than conventional technologies while operating at ample high speed [2]. Moreover, SET logic implementation rapidly pioneered as one of the innovative technologies where logic device sizes were limited only too few nano-scales and power dissipation reduced considerably. SET devices are requisite fundamentals in nanoelectronics and thus Researchers emphasized in designing SET based memory [3], logic circuits [6], electron pumps [9] etc. Since its very inception, different logic gates, flip-flops, addition, multiplication, division and also other computational elements such as sequence generator, ALU etc. using single electron devices have been implemented [3] [4] [5] [7] [8]. Here, we present the nano IC design of a Hybrid Counter retaining Single Electron Devices (SED). The unique device comprises of more than 300 tunnel junctions and operates as a Hybrid Counter using single electron transport. The letter concisely confers the basic physics of single electron devices in the subsequent section; it is followed by deliberation of specific basic circuits of SET logic gates. Lastly, a novel nano Hybrid Counter is modelled and realized with SET logic devices. II. SET ORTHODOX NOTION A. SET Edifice Fig. 1 depicts a SET encompassing two tunnel junction coupled in series known as a Coulomb Island. Electrons are permitted to enter by tunnelling in succession through one of the electrodes. The device configuration of SET is much identical to ordinary Field Effect Transistor (FET)s. The three terminals i.e. the outside terminal of each tunnel junction labelled as Source and Drain and the Gate terminal is capacitive-ly coupled to the node between the two tunnel junctions. Structurally the capacitor makes available the path of setting the electric charge on the Coulomb Island [10]. Fig. 1 SET Structural View B. Coulomb Blockade Configuration Coulomb Island promisingly is the most interesting portion in SET. The energy level of Coulomb Blockade is at much higher range compared to the tunnelling range of the electron on the source contact. Operationally, lower energy electrodes are placed entirely in the energy level of the island. Basically, at gate electrode positive voltage is applied; thereby the energy levels of the island electrodes are lowered. 2015, IJARCSSE All Rights Reserved Page 1354

2 There are three pre-conditions for Coulomb Blockade:- The elementary charge (e) is greater than the bias voltage (V bias ) divided by the self-capacitance (C) of the island, i.e. V bias <e/c. The thermal energy that lies proximity to the source contact along with the thermal energy in the island which is aptly denoted by K b T; it is required to be lower than the charging energy i.e K b T<e^2c. [11] The tunnelling resistance R t is approximated to be higher than (h/e^2) (derived from Heisenberg s Uncertainty Principle). Fig. 2 Energy Level of the Island Electrode Coulomb Blockade C. Passing of Electron through Tunnel Junction The tunnelling of electron transpires from point to point of a tunnel junction to the opposite end point of the tunnel junction. The controlling strategic is that we requires Coulombs energy E c to charge an island with an electron where E c =e^2/2c>k b.t Where, K b = Boltzmann constant=1.38*10^-34 J/K In this case coulomb energy is greater than available thermal energy and the movement of electron can be control by controlling the available energy supplied by voltage source [12 &13] as shown in Fig.3 Fig. 3 Simple Electron Tunnelling Phenomena III. MODELLING OF SET BASED HYBRID COUNTER SETs are optimized as a competent authority in the next generation ICs. It is an obvious to explore all intrinsic qualities of SETs to develop fundamental logic gates in a wide-ranging manner. In this regard numerous research attempts have been categorically reported since the last decade [14-20]. This particular endeavour is an extended future work of J. Gope et.al., [21-32] and here the authors accentuated to design unconventional hybrid counters using SETs. Conventionally a Hybrid Counter is an extraordinary counter where the output behaves as a synchronous counter and drives the clock input of another counter to get a divide by N operation. They are extensively used to acquire a symmetrical divided by N output. For instance when N is any number divisible by 2 we can obtain a symmetrical divide by N counters. SET Circuit of Hybrid Counters Fig.4 enumerates the proposed SET Hybrid Counter consisting of roughly 300 Tunnel Junctions and nearly same number of capacitors. The authors humbly admit that the design was quite complex; thus it was fascinating but challenging. Moreover, owing to circuit clarity the metaphors of input voltage and other few common peripherals was intentionally limited. The output waveform is annexed subsequently in Fig.5 Comparative Study of the Circuit The significant of this proposed design is that it has the potential of providing much more component density thereby reducing the future IC sizes. Apart of this, the proposed circuit is quite faster than any conventional CMOS based circuit. Such comparisons provide a valuable reason to adopt SET based designing of such computational tools. The power dissipation for switching a single bit is of few nw which is considerably small when compared to conventional devices. Fig. 6 and Fig.7 shows the comparison of propagation delay and fastness for the designed decision making system using conventional and Spin based gates. 2015, IJARCSSE All Rights Reserved Page 1355

3 Fig. 6 Comparative Study of Propagation Delay Fig. 7 Comparative Study of Speed IV. CONCLUSIONS The authors once again take the privilege to reveal the salient features and performance of SETs. Materialistically, it is absolutely superior equated to conventional FETs due to their nano size. Other noteworthy incentives related to CMOS circuit are low energy consumption, high sensitivity, higher operating speed and simplified operational principle. The contemporary era that stresses in supremacy includes nano dimensional, longer battery life and easy portable consumer electronics into daily life and the same can be apprehended only by SET. Moreover, it is quite simple but robust. In such circumstances SET has positioned in the premier place among other post CMOS devices. Further, the aspiring logical operation when implemented by SET creates bigger panorama in future generation logic circuit. The same is attributed here in this letter. REFERENCES [1] P.C.Pradhan et.al., Design and Simulation of SR, D and T Flip- Flops modeled with Single Electron Devices, International Symposium on Devices MEMS, Intelligent Systems & Communication (ISDMISC) [2] K.K.Likharev Single-electron devices and their applications IEEE Proc. Vol. 87, April 1999, pp [3] Cor Meenderinck, and Sorin Cotofana; Computing Division Using Single-Electron Tunneling Technology IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 4, JULY 2007 [4] N.J.Stone and H.Ahmed Silicon single electron memory cell - Appl. Phys. Lett., Vol.73, No.15, October 1998 pp [5] Debasis Samanta, A.K.De, Giriprakash HD and Subir Kumar Sarkar Design and implementation of a sequence generator using single electron device based threshold logic gates Far east journal of electronics and Communications, vol. 1, issue 3, December [6] C.P.Heij et al Single-electron inverter Appl. Phys. Lett. Vol. 78, no. 8, February 2001, pp R. E. Sorace, V. S. Reinhardt, and S. A. Vaughn, High-speed digital-to-rf converter, U.S. Patent , Sept. 16, [7] Casper Lageweg et al A Linear Threshold Gate Implementation in Single Electron Technology IEEE proc. Computer society workshop on VLSI, April 2001, pp [8] A.K.Biswas, S.K.Sarkar An arithmetic logic unit of a computer based on single electron transport system Semiconductor physics, Quantum electronics and optoelectronics Vol. 6, , IJARCSSE All Rights Reserved Page 1356

4 [9] Hansjörg Scherer et al Steps Toward a Capacitance Standard Based on Single-Electron Counting at PTB IEEE Transactions on Instrumentation And Measurement, VOL. 54, NO. 2, APRIL 2005 [10] D.V. Averin and K.K. Likharev, Single-Electronics: Correlated Transfer of Single Electronics and Cooper Pairs in Small Tunnel Junctions, in Mesoscopic Phenomena in Solids, ed by B. Altshuler, P.Lee and R. Webb. Amsterdam: Elsevien, 1991, p [11] H. Van Houten, C.W.J. Beenakker, A.A.A. Staring, Coulomb Blockade Oscillations in Semiconductor Nanostructures, in Single Charge Tunneling, ed. by H. Grabert and M.H. Devoret, New York:Plenum, 1992, p [12] L.S. Kuzmin and Yu. A. Pashkin, Single Electron Tunneling Oscillations in a Current Biased Josephson Junction, Physica B, vol , pp , Feb A. N. Korotkov, K.K. Likharev, J-Appl. Phys , [13] M. M. Dasigenis, I. Karafyllidis and A. Thanailakis A single-electron XOR gate, Microelectronics Journal Volume 32, Issue 2, February 2001, Pages [14] I.Tsimperidis, I. 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In National Conference on Smart Materials and Recent Technologies (SMART- 2007), Sri Venkateswara University, Tirupati, India, February 22-23, 2007, pp.26. [24] Jayanta Gope, et.al. Single Electron Device Based Application Specific Integrated Circuit Design for Use in Stock Market In National Conference on Advanced Computing and Computer Networks (NCACCN 2007), Vikhe Patil College of Engineering, Ahmednagar, Maharasthtra on 9-10 March [25] Jayanta Gope, et.al. Single electron device based string detector for the identification of Frame Delimiters in Data Transfer Protocols, National Conference on Digital Information Management (NCDIM 07), Thadomal Shahani Engineering College & Computer society of India, Mumbai , during 23-24th March [26] J. Gope et.al., Logic Synthesis of Contemporary European Model Traffic Control Signaling System Using Novel Nano Scaled Single Electron Tunneling Technology, The International Journal Of Science & Technoledge, Vol. 2 Issue 4, 2014, pp [27] J. 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Gope, Single Electron Transistor based Hardware designing of Linear Block Coding Technique for Error Correction in Digital Communication System, INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY, vol: 3(6): June, 2014, pp , IJARCSSE All Rights Reserved Page 1357

5 Fig. 4 Proposed Circuit Diagram of SET based Nano-Hybrid Counter Fig. 5 Output Waveform of the operation of proposed SET based Nano-Hybrid -Counter 2015, IJARCSSE All Rights Reserved Page 1358