THE FORWARD converter has been widely used in the

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1 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST Analysis and Design of an Interleaved Active-Clamping Forward Converter Yu-Kang Lo, Member, IEEE, Tsu-Shou Kao, and Jing-Yuan Lin Abstract This paper presents a new interleaved activeclamping zero-voltage-switching (ZVS) forward converter, which is mainly composed of two active-clamping forward converters. Only two switches are required, and each one is the auxiliary switch for the other. The circuit complexity and cost are thus reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve ZVS during the dead times. The duty cycles are not limited to be equal and within 50%. The complementary switchings and the resulted interleaved output inductor currents diminish the current ripple in output capacitors. Accordingly, the smaller output chokes and capacitors lower the converter volume and increase the power density. Detailed analysis and design of this new interleaved active-clamping forward converter are described. Experimental results are recorded for a prototype converter with an ac input voltage of V rms, an output voltage of 1 V, and an output current of 16 A, which operates at a switching frequency of 150 khz. Index Terms Active clamping, complementary switching, interleaved forward converter, zero-voltage switching (ZVS). I. INTRODUCTION THE FORWARD converter has been widely used in the power supply industry for its simplicity and low cost. However, there still exist several disadvantages, which render the applications of the forward converters unsuitable for higher input voltages or output power ratings. Some of the major shortcomings are listed as follows. 1) Transformer Energy Reset and the Voltage Stress on the Switching Device: A typical forward converter needs an additional auxiliary winding to complete the transformer energy reset. This additional reset winding raises the volume of the transformer. Also, the voltage stress applied to the switching device is.6 times the maximum input dc voltage [1] [3]. Other approaches for the transformer energy reset have been developed. One example is the resistor capacitor diode snubber [4] [6], which lowers the voltage stress to be under two times the maximum input dc voltage. However, the power dissipation on the resistor reduces the conversion efficiency. Another method to lessen the voltage stress problem of the switch Manuscript received July 5, 006; revised November 1, 006. This work was supported by the National Science Council, Taiwan, R.O.C., under Grant NSC E The authors are with the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 10607, Taiwan, R.O.C. ( yklo@mail.ntust.edu.tw). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TIE is to adopt the double-ended topology [7], [8]. The off voltage of the power switch is at the maximum input dc voltage. Moreover, the transformer does not need an extra demagnetizing winding. The penalties are an additional metal oxide semiconductor field-effect transistor (MOSFET), a high-side gate driver, and a maximum of 50% limitation on the duty cycle. Recently, the activeclamping scheme has been proposed to achieve the zerovoltage switching (ZVS) at a fixed switching frequency [9] [1]. The voltage stress on the power device is about 1.6 times the maximum input dc voltage. Nevertheless, an additional auxiliary switch is required to complete the energy reset process and to assist the main switch in achieving ZVS. The cost is thus higher at the same output power rating. ) Output Power Capability: In many practical conditions, higher power density and conversion efficiency are required. Generally, paralleling two or more converter modules can evenly distribute the power losses and the current stress on the switch devices []. Particularly, by using interleaved structures, the output current ripple can be effectively reduced, or equivalently, the output inductance and the capacitance can be halved under the same output rating. However, a total of four switches are required in an interleaved active-clamping forward converter. The circuit complexity and cost are high. Concerning the parallel operation, it must be ensured that the load current is equally shared in the two converter modules. Consequently, current sharing could be an extra burden [3], [4]. Due to the above statements, a new interleaved activeclamping ZVS forward converter with only two active switches is proposed in this paper. The presented topology is composed of, and is derived from, paralleling two active-clamping forward converters. The main switches of the two converters are also the auxiliary switches for each other to achieve ZVS operation. Thus, no additional auxiliary switch is needed. The transformer primaries of the two modules are connected in series, whereas the secondaries are parallel connected at the common load. Hence, the two forward converter modules are in a symbiotic form, and the current sharing is naturally realized. The switching in the proposed circuit features a fully complementary characteristic, which is different from the traditional 180 phase-shifted interleaved forward converter. In a switching period, the output inductor current ripples of the two interleaved converters are almost cancelled for any duty cycle. Accordingly, it is effective in improving the power density. Since the /$ IEEE

2 34 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 007 Fig. 1. Schematic of the proposed interleaved active-clamping ZVS forward converter. presented interleaved ZVS forward converter is a dc dc type, a rectification stage, for example, a diode bridge rectifier or a power factor corrector preregulator, is required for an offline application. To sum up, the proposed interleaved converter possesses the following advantages. No additional auxiliary switch is required to accomplish ZVS and to increase the conversion efficiency. No current sharing mechanism is required. The complexity of the control circuit is reduced. The transformer secondaries are connected in parallel, which is suitable for high-power applications. The interleaved architecture in the converter output is suitable for the low-voltage and high-current output applications. In the following contents, the operations of the proposed interleaved active-clamping ZVS forward converter will be thoroughly analyzed. The dc voltage gain and the design issues will also be derived. Finally, experimental results are presented for a prototype converter with an ac input voltage of V rms, an output voltage of 1 V, and an output current of 16 A, which operates at a switching frequency of 150 khz, to verify the theoretical analysis. II. ANALYSIS OF THE PROPOSED INTERLEAVED FORWARD CONVERTER Fig. 1 shows the schematic of the proposed interleaved active-clamping ZVS forward converter, which is derived from two active-clamping forward converter modules. Module A consists of the transformer T a, the clamping capacitor C 1,the main switch Q 1, the auxiliary switch Q, the rectifier diode D 1, the freewheeling diode D, the output capacitor C O, and the output inductor L O1. Module B consists of the transformer T b, the clamping capacitor C, the main switch Q, the auxiliary switch Q 1, the rectifier diode D 3, the freewheeling diode D 4, the output capacitor C O, and the output inductor L O. C r is equal to the parallel combination of the output capacitances of Q 1 and Q and the parasitic capacitance of the transformer primary winding [18]. The primary sides of T a and T b are series connected. The output inductors L O1 and L O are parallel connected and equally share the load current. To analyze the proposed interleaved forward converter, the following assumptions are made. The conduction losses of all the switches and diodes are neglected. The clamping capacitances C 1 and C are much larger than the resonant capacitance C r. Moreover, the steadystate clamping capacitor voltages V C1 and V C can be viewed as constant voltage sources of which the voltage levels are dependent on the input voltage V I and the duty cycle. The output capacitance C O is large enough so that the output voltage V O is a constant value. The output inductances L O1 and L O are large enough so that the currents flowing through those inductors are nearly constant. The turns ratio of the transformer windings is n = N 1 /N. The magnetizing inductances of the two transformers are equal. The resonant inductance L r is much smaller than the magnetizing inductance L m. Thus, the voltage drop across L r can be neglected. The energy stored in the resonant inductor is greater than the energy stored in the resonant capacitor to achieve ZVS operation for the active switches. The conduction times of Q 1 and Q are DT s and (1 D)T s, respectively, where D is the duty cycle of Q 1, and T s is the switching period. Also, the dead time is much smaller than any of the conduction times. The converter system is operated under the continuousconduction mode (CCM). The output inductor currents continuously flow. From the above assumptions, the voltages of the clamping capacitors C 1 and C in the steady state can be calculated. In addition, the transfer ratio of V O to V I can also be obtained. When Q 1 is turned on, the voltage across the primary winding (or the magnetizing inductor) of T a approximates the input voltage V I. On the other hand, when Q turns on, the voltage across the magnetizing inductor of T a is about V C1.From the flux balance of L m under the steady state, V C1 can be determined as V C1 = D 1 D V I. (1) Similarly, when Q 1 is turned on, the voltage across the primary magnetizing inductor of T b approximates V C. When Q 1 turns off, the voltage across the magnetizing inductor of T b is about (V I + V C1 V C ). Then, from (1) and the inductor flux balance, the steady-state value of V C can be found to be V C = V I. () Also, from the flux balance of the output inductors L O1 and L O, the voltage gain of the proposed interleaved forward converter can be obtained as V O V I = D n. (3)

3 LO et al.: ANALYSIS AND DESIGN OF AN INTERLEAVED ACTIVE-CLAMPING FORWARD CONVERTER 35 the load. The output inductor current I O is about half the load current and flows through the freewheeling diode D 4.Inthis state, the resonant capacitor voltage v Cr remains at zero, and the resonant inductor current i Lr can be expressed as i Lr (t) = V I L r + L m (t t 0 )+i Lr (t 0 ). (4) State t 1 <t<t : This state starts at T 1 when Q 1 is turned off. As shown in Fig. 3(b), D 1 is still carrying half the load current. The current through the freewheeling diode D is zero. The resonant inductor current i Lr charges the resonant capacitor C r from zero level to V I. For module B, the output inductor L O keeps discharging to supply the output power. The output inductor current I O is half the load current and flows through D 4. In this state, the resonant inductor current i Lr and the resonant capacitor voltage v Cr can be written as i Lr (t) =ω r1 C r V I sin ω r1 (t t 1 )+i Lr (t 1 )cosω r1 (t t 1 ) (5) v Cr (t) = i L r (t 1 ) sin ω r1 (t t 1 )+V I [1 cos ω r1 (t t 1 )] ω r1 C r (6) where 1 ω r1 = ( Lr + L ). (7) m Cr v Cr is equal to V I at time t = t. From (6), the time interval of this state can be expressed as t 1 = t t 1 = 1 ω r1 tan 1 [ ] ωr1 C r V I i Lr (t 1 ) C rv I i Lr (t 1 ). (8) Fig.. Key waveforms of the proposed interleaved active-clamping ZVS forward converter. The voltage gain expressed in (3) is the same as a basic forward converter operated under CCM. Thus, the output voltage can be regulated by adjusting the duty cycle when the input voltage changes. Fig. depicts the key waveforms of the proposed interleaved active-clamping ZVS forward converter, where i Q1 is the current flowing through Q 1, its body diode, and C r. There are eight states in a complete switching cycle. In the following analysis, the governing current and voltage equations are derived for each state. The conduction paths for each operating state are illustrated in Fig. 3. State 1 t 0 <t<t 1 : Q 1 is turned on, and D 1 and D 4 are conducting in state 1, as shown in Fig. 3(a). For module A, v pa approximates V I. Thus, the magnetizing current i ma linearly increases. The input power is transferred to the secondary through the transformer T a. The output inductor current I O1 is about half the load current and flows through the rectifier diode D 1. For module B, Q is turned off. v pb is equal to V C (or V I ). The magnetizing current i mb linearly decreases. The energy stored in the output inductor L O discharges to supply State 3 t <t<t 3 : As shown in Fig., this state begins at t when v Cr = V I and ends at t 3 when v Cr = V I + V C1.The conduction paths are illustrated in Fig. 3(c). For module A, the primary voltage v pa reduces to zero such that D 1 and D are both conducting. The current through D 1 is linearly decreasing, whereas the current through D is linearly increasing. The energy stored in the output inductor L O1 discharges to supply the load power. For module B, the primary voltage v pb is equal to zero such that D 3 and D 4 are both conducting. The current through D 3 is linearly increasing, and the current through D 4 is linearly decreasing. The output inductor L O keeps discharging to supply the load power. In this state, the resonant inductor current i Lr and the resonant capacitor voltage v Cr can be derived as where i Lr (t) =i Lr (t )cosω r (t t ) (9) v Cr (t) = i L r (t ) sin ω r (t T )+V I ω r C r (10) ω r = 1 Lr C r. (11)

4 36 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 007 Fig. 3. Conduction paths of (a) state 1, (b) state, (c) state 3, (d) state 4, (e) state 5, (f) state 6, (g) state 7, and (h) state 8 for the proposed forward converter during one switching period. At t 3, v Cr is equal to V I + V C1. From (10), the time duration of state 3 is given by t 3 =t 3 t = 1 [ ] sin 1 ωr C r DV I C r DV I ω r (1 D)i Lr (t ) (1 D)i Lr (t ). (1) To ensure the ZVS operation for Q,the initial energy stored in L r must be greater than the energy required to charge C r from V I to (V I + V C1 ) 1 L ri L r (t ) 1 C r [ (VI + V C1 ) VI ] (13) L r D( D)C rvi (1 D) i L r (t ). (14) State 4 t 3 <t<t 4 : After t 3, the resonant capacitor voltage v Cr is clamped at (V I + V C1 ). The resonant inductor current i Lr flows through the body diode of Q,asshownin Fig. 3(d), to charge the clamping capacitor C 1. i Lr is linearly decreasing. Q can now be turned on. Since C 1 is assumed much larger than C r, V C1 remains almost constant. For module A, i D1 is linearly decreasing and i D is linearly increasing. For module B, on the contrary, i D3 is linearly increasing and i D4 is linearly decreasing. In this state, i Lr can be written as i Lr (t) = DV I (t t 3 )+i Lr (t 3 ). (15) (1 D)L r State 5 t 4 <t<t 5 : At t 4, which is on the secondary side of module A, i D1 finally decreases to zero. I O1 flows through

5 LO et al.: ANALYSIS AND DESIGN OF AN INTERLEAVED ACTIVE-CLAMPING FORWARD CONVERTER 37 D and approximates half the load current. The output inductor L O1 discharges to supply the output power. The primary voltage v pa approximates V C1, as shown in Fig. 3(e). The magnetizing current i ma is linearly decreasing. For module B, i D4 decreases to zero. I O flows through D 3 and approximates half the load current. The primary voltage v pb becomes equal to V C1. The magnetizing current i mb is linearly increasing. The input power is delivered to the secondary through T b.the resonant capacitor voltage v Cr remains at (V I + V C1 ) in this state. The resonant inductor current i Lr can be expressed as DV I i Lr (t) = ( Lr + L ) (t t m 4 )+i Lr (t 4 ). (16) (1 D) During this state, i Lr will change its polarity and flows through Q. Thus, the ZVS operation for Q is achieved. State 6 t 5 <t<t 6 : At t 5, Q is turned off, as shown in Fig. 3(f). The resonant current i Lr flows through the resonant capacitor C r. The resonant capacitor voltage v Cr discharges from (V I + V C1 ) to V I. For module A, the primary voltage v pa is equal to V I V Cr. The secondary voltage is negative so that D 1 is off. The output inductor current I O1 approximates half the load current and flows through the freewheeling diode D. For module B, the primary voltage v pb is positive and equal to v Cr V I. D 4 is reverse-biased. The output inductor current I O is about half the load current and flows through the rectifier diode D 3. The resonant current i Lr and the voltage v Cr in this state can be expressed as i Lr (t) = ω r1c r ( D)V I sin ω r1 (t t 5 ) 1 D + i Lr (t 5 )cosω r1 (t t 5 ) (17) v Cr (t) = i L r (t 5 ) ω r1 C r sin ω r1 (t t 5 ) ( D)V I 1 D cos ω r1 (t t 5 )+ 3 D 1 D V I. (18) increasing. The resonant current i Lr and the voltage v Cr in this state can be expressed as i Lr (t) =i Lr (t 6 )cosω r (t T 6 ) (0) v Cr (t) = i L r (T 6 ) sin ω r (t t 6 )+V I. ω r C r (1) At t 7, v Cr reduces to zero. From (1), the time interval of this state can be expressed as t 67 = t 7 t 6 = 1 ω r sin 1 [ ] ωr C r V I C rv I i Lr (T 6 ) i Lr (T 6 ). () To ensure ZVS operation for Q 1, the initial energy stored in L r must be greater than the energy that is required to discharge C r from V I to 0. 1 L ri L r (t 6 ) 1 C rv I (3) L r C rvi i L r (t 6 ). (4) State 8 t 7 <t<t 8 : At t 7, v Cr decreases to zero and is clamped at zero. As shown in Fig. 3(h), the body diode of Q 1 is conducting, and Q 1 can be turned on to achieve the ZVS operation. For module A, the secondary current through D 1 is linearly increasing until i D1 = I O1. The current through D is linearly decreasing to zero. For module B, the secondary current through D 4 is linearly increasing until i D4 = I O. The current through D 3 is linearly decreasing to zero. During this state, the resonant current i Lr changes its polarity and can be expressed as i Lr (t) = V I L r (t t 8 )+i Lr (t 8 ). (5) At t 8, when Q 1 is turned on again, this state ends, and the operating state returns to state 1 to begin the next switching cycle. At T 6, v Cr is equal to V I. From (18), the time interval of this state can be expressed as t 56 = t 6 T 5 DC r V I (1 D)i Lr (T 5 ). (19) State 7 t 6 <t<t 7 : At t = t 6, v Cr is equal to V I.For module A, as shown in Fig. 3(g), the primary voltage v pa is zero. The output inductor L O1 discharges to supply the load power. On the secondary side, the current through the rectifier diode D 1 is linearly increasing, and the current through the freewheeling diode D is linearly decreasing. For module B, the primary voltage v pb is zero. The output inductor L O discharges to supply the load power. On the secondary side, the current through the rectifier diode D 3 is linearly decreasing, and the current through the freewheeling diode D 4 is linearly III. CIRCUIT DESIGN PROCEDURE It is assumed that the maximum duty cycle of the proposed interleaved active-clamping forward converter is D max.the turns ratio of the transformer is equal to n = N 1 N = V in,mind max V o + V f (6) where V f is the forward voltage drop of the rectifier diode. The maximum voltage stresses of Q 1 and Q are approximated as V DS1,max =V DS,max =V I +V C1 =V I + V ID 1 D = 1 D. (7) Generally, the duty cycle is adjusted to be smaller than 50% to limit the voltage stresses on the switches. The peak currents of Q 1 and Q are equal to the peak of i Lr, which can be V I

6 38 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 007 expressed as the sum of its dc component and the ripple current. Taking Fig. 3(a), for example, in state 1, half the output power is supplied by the input dc source. The dc component of i Lr can be determined by dividing the average input dc current by the duty cycle. The ripple can be calculated from (4). By neglecting L r in (4), the peak currents of Q 1 and Q are approximately given as 1 I Q1,peak = I Q,peak I O,maxV O + V I,min D max T s (8) ηv I D max L m where η is the conversion efficiency. The maximum voltage stresses of the rectifier diodes (D 1 and D 3 ) and the freewheeling diodes (D and D 4 ) are respectively equal to V D1,stress = V D3,stress = V C 1 n V ID (1 D)n = V o (9) 1 D V D,stress = V D4,stress = V I n. (30) The peak diode currents can be expressed as I D1,peak = I D,peak = I D3,peak = I D4,peak 1 I O,max. (31) The root-mean-square (rms) currents of the diodes can be respectively expressed as I D1,rms = I D4,rms 1 I O,max Dmax (3) I D,rms = I D3,rms 1 I O,max 1 Dmax. (33) To ensure the ZVS operation for Q 1 and Q, the resonant inductance L r must be the larger of the results of (14) and (4). Since usually i Lr (t 6 ) is smaller than i Lr (t ),theresult of (4) is adopted to design the minimum L r, which can be expressed as L r,min = C rvi i L r (T 6 ). (34) The ripple voltage of the clamping capacitor is defined to be smaller than 10% of the steady-state voltage. Referring to Fig. 3(a), during state 1, an average current of i mb (T 1 )/ discharges C. Thus, the ripple voltage of V C is V C = i mb(t 1 ) (t 1 t 0 ). (35) C v pb approximates V C in state 1. From the volt-second characteristic of L m, the following equation can be derived: V C (t 1 t 0 )=L m i mb (t 1 ). (36) By dividing (35) by (36), and substituting the ripple voltage ratio of 10%, the required clamping capacitance C can be expressed as C 5D T s L m. (37) Fig. 4. Implemented interleaved active-clamping forward converter. Similarly, C 1 is charged during about half period of state 5. Thus, the required clamping capacitance C 1 is approximately given as C 1 5(1 D) T s L m. (38) The output inductance can be determined from the specified current ripples L O1 = V O(1 D min )T s i O1 (39) L O = V OD max T s i O. (40) From t to t 4, when both L O1 and L O discharge to supply the load power, the maximum ripple voltage will be imposed on the output capacitor C O. Thus, C O can be calculated from the specified output voltage ripple. C O = V O(t 4 t )T s L O1 V O. (41) IV. EXPERIMENTAL RESULTS In order to verify the theoretical analysis, a 00-W prototype was built and tested in the laboratory. The implementation of the proposed interleaved active-clamping ZVS forward converter circuit is shown in Fig. 4, assuming that the filter capacitor following the full-bridge diode rectifier is large enough. The experimental results are obtained with the following parameters: input ac voltage range V rms ; input dc voltage V I = V; output dc voltage V O =1V; rated output current 16 A; switching frequency f s = 150 khz; maximum duty cycle D max =0.5; turns ratio n = N 1 /N =65/13 = 5; clamping capacitances C 1 = C =0.33 µf; resonant frequency f r =6MHz; output inductances L O1 = L O =40µH; output capacitance C O = 330 µf; conversion efficiency η>0.8.

7 LO et al.: ANALYSIS AND DESIGN OF AN INTERLEAVED ACTIVE-CLAMPING FORWARD CONVERTER 39 Fig. 5. ZVS operations for Q 1 and Q. v GS1 /v GS :10V/div.v DS1 /v DS : 00 V/div. Time: 1 µs/div. Fig. 7. Waveforms of the gate signals and the secondary diode currents for (a) module A and (b) module B. v GS1 /v GS :10V/div.i D1 /i D /i D3 /i D4 : 10 A/div. Time: µs/div. Fig. 6. Waveforms of v GS1, i Lr, i Q1,andi Q for (a) I O =8 Aand (b) I O =16A. v GS1 :0V/div.i Lr /i Q1 /i Q :5A/div.Time:µs/div. An EI-40 core with A e =1.48 cm and A w =1.57 cm is used for the isolation transformers T a and T b. For the proposed interleaved active-clamping forward converter, the ZVS operations of the two switches are mainly guaran- teed by the required enough energy provided by the reflected load current. Therefore, the energies stored in the magnetizing inductors can be ignored, and L m can be arbitrarily designed. In the implemented prototype converter, L m is equal to 6 mh. Also, to ensure the ZVS operations, a 50-ns dead time is inserted between the gate signals of Q 1 and Q. The C OSS of an 11N80C3 MOSFET is about 40 pf at a 400-V drain-to-source voltage. Therefore, the equivalent resonant capacitance C r, including the output capacitances of Q 1 and Q and the parasitic capacitance across the transformer primary winding, is about 100 pf. The resonant inductance L r is about 9 µh. The output voltage is sensed and scaled to track a reference voltage. The voltage difference is sent to a compensated error amplifier (EA). Then, the output command voltage of the EA is compared with a highfrequency carrier sawtooth wave to produce the gate signals for Q 1 and Q. Fig. 5 shows the experimental waveforms of the gate-tosource and drain-to-source voltages of Q 1 and Q for the full load. It is seen that before Q 1 and Q are turned on, the drainto-source voltages v DS1 and v DS are zero. Therefore, ZVS operations for Q 1 and Q are achieved. Fig. 6 illustrates the

8 330 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 007 Fig. 10. Transient of the output voltage during a step input voltage change. V I : 100 V/div. V O : 500 mv/div. Time: 100 ms/div. Fig. 8. Waveforms of v GS1 and output inductor currents for (a) I O =1A and (b) I O =16A. v GS1 :10V/div.i O1 /i O :5A/div.Time:µs/div. Fig. 11. (a) Voltage stresses of Q 1 and Q. (b) RMS current ratings of the secondary diodes at different duty cycles. Fig. 9. Transient of the output voltage during a step load change. I O :5A/div. V O : V/div. Time: ms/div. experimental results of the gate signal v GS1, the primary-side current i Lr, and the switch currents i Q1 and i Q at half load and full load. Before Q 1 is turned on, the primary-side current i Lr is equal to the Q current i Q. The negative i Lr discharges the output capacitor C r across Q 1 in order to achieve the ZVS operation in the dead time. After Q 1 is turned on, the primary current i Lr is equal to the Q 1 current i Q1. Fig. 7(a) illustrates the gate signal v GS1 and the secondary-side currents at the full load. The secondary-side current i D1 is equal to the output inductor current I O1 when Q 1 is turned on. As Q 1 turns off, the freewheeling diode current i D is equal to I O1.Fig.7(b) depicts the gate signal v GS and the secondary-side currents at the full load. The secondary-side current i D3 is equal to the output inductor current I O when Q is turned on. As Q turns off, the freewheeling diode current i D4 is equal to I O.Fig.8 indicates that the output inductors equally share the load current at different loads. Also, the interleaved operation helps the reduction of the output capacitor ripple current. Transients of the output voltage during a step load change and a step input voltage change are respectively recorded in

9 LO et al.: ANALYSIS AND DESIGN OF AN INTERLEAVED ACTIVE-CLAMPING FORWARD CONVERTER 331 Fig. 1. Measured system efficiencies. Figs. 9 and 10. It is observed that as I O changes from 8 to 16 A and then back to 8 A, and when V I changes from 190 to 10 V and then back to 190 V, V O can still be stabilized and regulated. Fig. 11(a) shows the voltage stresses of Q 1 and Q for different duty cycles at an input ac voltage of 135 V rms. From (7), as the duty cycle increases over 0.5, Q 1 and Q suffer a dramatically growing voltage stress. It seems that a reasonable value for the maximum duty cycle is about 70%, at which the maximum drain-to-source voltage is around 600 V. Fig. 11(b) indicates the rms currents of the secondary diodes at different duty cycles. From (3) and (33), these diodes bear the same rms current rating at a 50% duty cycle. Fig. 1 shows the measured efficiencies of the proposed interleaved active-clamping ZVS forward converter at different load levels. The average efficiency when the system is active is above 86%. At the rated full load, the conversion efficiency is about 84%. V. C ONCLUSION This paper presents a new interleaved active-clamping ZVS forward converter, which is basically composed of two activeclamping forward converters. Only two active switches are utilized to fulfill the complementary ZVS switching. The complexity and cost of the power circuit and controller are greatly lowered. Furthermore, the two modules of the proposed interleaved topology automatically evenly share the load current. The duty cycle can be adjusted within a range from 0% to 70%, considering a reasonable voltage stress of the switch. Thus, the ranges of the line and load variations for a regulated output are extended. The output current ripples can be lessened due to the interleaved operations. The sizes of the output chokes and capacitor can be reduced. Operating modes in a complete switching cycle are described, and key equations are derived. Also, the design procedures are formulated and justified. The experimental results of a 00-W prototype are recorded to verify the theoretical analysis. The average activemode efficiency is above 86%. For a universal ac input, it is suggested that the maximum duty cycle is within 70% to limit the voltage stress of the switch. The proposed new interleaved active-clamping forward converter is particularly suitable for the applications where low-voltage and highcurrent outputs are required, for example, the adapters, the liquid-crystal-display television power supplies, and the leadacid battery chargers. REFERENCES [1] F. D. Tan, The forward converter: From the classic to the contemporary, in Proc. 17th Annu. IEEE Appl. Power Electron. Conf. and Expo., 00, pp [] A. K. S. Bhat and F. D. Tan, A unified approach to characterization of PWM and quasi-pwm switching converter: Topological constraints, classification, and synthesis, IEEE Trans. Power Electron., vol. 6, no. 4, pp , Oct [3] S. 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10 33 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 007 Yu-Kang Lo (M 96) was born in Chia-Yi, Taiwan, R.O.C., in He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1991 and 1995, respectively. Since 1995, he has been with the faculty of the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei, where he is currently an Associate Professor and in charge of the Power Electronics Laboratory. His research interests include the design and analysis of a variety of switching-mode power converters and power factor correctors. Dr. Lo is a member of the IEEE Power Electronics and Industrial Electronics Societies. Jing-Yuan Lin was born in Kao-Hsiung, Taiwan, R.O.C., in He received the M.S. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 004. He is currently working toward the Ph.D. degree in the Department of Electronic Engineering, National Taiwan University of Science and Technology. His research interests include the design and analysis of zero-voltage-switching DC/DC converters and power factor correction techniques. Tsu-Shou Kao was born in Kao-Hsiung, Taiwan, R.O.C., in He received the B.S. and M.S. degrees from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 001 and 004, respectively. He is currently working toward the Ph.D. degree at the same university. He was an EMI research and testing Engineer in Taiwan from 001 to 003. His research fields are EMI filter design, EMI measurement automation, and analysis of switching power supplies.