Rev. A ( /10) By: AY, SA, JB (OPAL-RT)

Transcription

1 Rev. A ( /10) By: AY, SA, JB (OPAL-RT) OPAL-RT Technologies reserves all rights in this document and in the information contained herein. Reproduction, use or disclosure to third parties without express authority is strictly forbidden.

2 A. Solar Power Conditioner Using a Zigzag-Connected Chopper Converter (Public) 1) Circuit 2) Time step Requirement 3) Test Results and Accuracy 4) Possible Solutions 5) Typical Model Separation 6) Real time simulation performance of the conditioner system 7) References Copyright (C) OPAL-RT Technologies 2

3 HIL Simulator of Solar Power Conditioner Copyright (C) OPAL-RT Technologies 3

4 Solar Power Conditioner Using a Zigzag-Connected Chopper Converter Copyright (C) OPAL-RT Technologies 4

5 Refer to reference (1) Copyright (C) OPAL-RT Technologies 5

6 The circuit was simulated: With PLECS With Simulink, SimPowerSystems (SPS) With Simulink, SimPowerSystems, with ARTEMIS, and TSB blocks for power converters Compared Simulation accuracy and Speed Copyright (C) OPAL-RT Technologies 6

7 The simulation of PLECS, SPS, and TSB models showed that the waveforms exactly the same at very small time-step (1 us) Results are given on the next 3 slides. Therefore, in following tests, the model SPS at 1 us was taken as reference for the comparison. Copyright (C) OPAL-RT Technologies 7

8 Copyright (C) OPAL-RT Technologies 8

9 Copyright (C) OPAL-RT Technologies 9

10 Copyright (C) OPAL-RT Technologies 10

11 Copyright (C) OPAL-RT Technologies 11

12 Solar Power Conditioner Using a Zigzag-Connected Chopper Converter Copyright (C) OPAL-RT Technologies 12

13 The following tests were made on the circuit: SPS: at 1 us & 10 us TSB: at 1 us & 10 us PLECS: at 1 us & 10 us Copyright (C) OPAL-RT Technologies 13

14 If the (fixed) time step is increased then: both SPS and PLECS models loose their accuracy SPS-TSB model retains very good accuracy This is understandable because the simulation of switching converters in the circuit requires the use of interpolation when fixed step is used. And Interpolation is available only in OPAL-RT s TSB OPAL-RT studies show the following figures: With PLECS or SPS (no interpolation), the required step size needed for good accuracy is 1 to 2 % or the PWM period With TSB (with interpolation), the required step size is higher, % of PWM period 25 to 50 us is usually needed for other power system components Example PV conversion system switching at 20 khz (PWM cycle of 50 us), the required time step is: PLECS or SPS: 0.5 to 1 us OPAL-RT TSB: 5 to 10 us Solutions: Either decrease the time step to a very low value FPGA implementation Or increase the time step to a reasonable value CPU implementation using TSB converter models Copyright (C) OPAL-RT Technologies 14

15 Copyright (C) OPAL-RT Technologies 15

16 Copyright (C) OPAL-RT Technologies 16

17 Copyright (C) OPAL-RT Technologies 17

18 Solar Power Conditioner Using a Zigzag-Connected Chopper Converter Copyright (C) OPAL-RT Technologies 18

19 Bad results with non-characteristic unreal harmonics when no interpolation is used(plecs& SPS) Incorrect steady state results without interpolation(plecs& SPS) Good results when TSB blocks are used, because of interpolation of switching goodsteadystateresultswithtsb Bad staircase relation between Duty Cycle and steady-state output without interpolation (PLECS, SPS) and good linear relation with interpolation(tsb) Because TSB uses interpolation, it is able and does simulate dead-time effect(impossible with PLECS, or SPS) Copyright (C) OPAL-RT Technologies 19

20 100 V upper IG B T 1 m H 0.1 Ω lower IG BT load current The load current should be linearly dependent upon the chopper duty-cycle 150 Variation of Duty Cycle with step 0.1µs Load Current Vs Duty Cycle Load Current (A) TSB 0.1us PLECS 0.1us SPS 0.1us duty Cycle (%) Copyright (C) OPAL-RT Technologies 20

21 500 Variation of Duty Cycle with step 1µs Load Current Vs Duty Cycle 400 Load Current (A) TSB 1us 100 PLECS 1us SPS 1us duty Cycle (%) Load Current (A) Variation of Duty Cycle with step 10µs Load Current Vs Duty Cycle SPS_TSB_10us PLECS 10 SPS 10us Observation steady state results are totally incorrect & not acceptable without interpolation (PLECS or SPS), resulting in this staircase shape when duty is increased slowly TSB 10us PLECS 10us SPS 10us duty Cycle (%) Copyright (C) OPAL-RT Technologies 21

22 Solar Power Conditioner Using a Zigzag-Connected Chopper Converter Copyright (C) OPAL-RT Technologies 22

23 Mixed Simulation Targets Converters on FPGA, with OPAL- RT s converter model for FPGA Power component on CPU with PLECS or SPS All-CPU Simulation Converters model one CPU with OPAL-RT TSB Power component on a second CPU with PLECS or SPS FPGA CPU CPU 1 CPU 2 Copyright (C) OPAL-RT Technologies 23

24 Solar Power Conditioner Using a Zigzag-Connected Chopper Converter Copyright (C) OPAL-RT Technologies 24

25 Real time simulation performance of the PV conditioner developed in Matlab using OPAL-RT software platform This real time simulation ran on a dual-xeon-based, 3.33 GHz and RT-LAB simulator with a time step of 10µs. The overall system was run using two CPUs core out of 12 processor cores available. The processors allocation and Real-Time Performance are summarized in Table bellow. CPUs Descript ions CPU 1: (10 µs) CPU 2: (10us) Components Content SS_PV_conditioner (complete system in slide 5) SM_PV_conditioner (controller) Model Calculation Time 2.5 µs 1 µs Minimu m time step Accelera tion factor 5 µs 23 Copyright (C) OPAL-RT Technologies 25

26 Real time simulation performance of the PV conditioner developed in PLECS A PLECS circuit cannot contain more than 1024 = 2 10 possible topologies[2] which is equivalent to 10 switches per PLECS circuit. The solution of this problem is to divide the system into a number of PLECS sub-circuits in order to reduce the number of switches to less than 10 switches per PLECS. The other solution is to increase the possible topologies by PLECS Company. The PV conditioner given in slide 5 was separated into two PLECS circuits. Each circuit contains one of the two phases of the PV conditioner. This separation introduces some delays to connect the two PLECS circuits which can in some cases, affect the accuracy and the stability of the system depending on the number of delays introduced to separate the system. Copyright (C) OPAL-RT Technologies 26

27 Real time simulation performance of the PV conditioner developed in Matlab using PLECS This real time simulation ran on a dual-xeon-based, 3.33 GHz and RT-LAB simulator with a time step of 10µs. The overall system was run using two CPUs core out of 12 processor cores available. The processors allocation and Real-Time Performance are summarized in Table bellow. CPUs Descript ions CPU 1: (10 µs) CPU 2: (10us) Components Content SS_PV_conditioner (complete system in slide 5) SM_PV_conditioner (controller) Model Calculation Time 2.5 µs 1 µs Minimu m time step Accelera tion factor 5 µs 14 Copyright (C) OPAL-RT Technologies 27

28 1) Hideaki Fujita, A High-Efficiency Solar Power Conditioner Using a Zigzag-Connected Chopper Converter, The 2010 International Power Electronics Conference, Tokyo Institute of Technology, Tokyo, Japan. 2) PLECS Manual: Copyright (C) OPAL-RT Technologies 28