FPGA-based PID Controller Using SOPC Technology for DC Motor Speed Control

Transcription

1 People s Democratic Republic of Algeria Ministry of Higher Education and Scientific Research University M Hamed BOUGARA Boumerdes Institute of Electrical and Electronic Engineering Department of Electronics Final Year Project Report Presented in Partial Fulfilment of the Requirements for the Degree of MASTER In Electrical and Electronic Engineering Option: Computer Engineering Title: FPGA-based PID Controller Using SOPC Technology for DC Motor Speed Control Presented by: - OUAZENE Ferhat - ARKOUB Syfax Supervisor: Dr. MAACHE Ahmed Registration Number:.../2015

2 Dedications I dedicate this little project to the memory of my father (May his soul rest in peace), La Mamiche To my brothers and my unique sister including all my little nephews and nieces. I also want to thank my family and all my dear friends, especially the Salahifs and Chniq teams. Ferhat I

3 I dedicate this work to My beloved parents, My brothers, my family and all my friends especially Salahifs & Tiger Prod, I will never forget all their support. All who know me, encourage me, and all who were behind my career Syfax II

4 Acknowledgement First of all, this kind of work is never the product of one person s effort. Therefore, we would like to express our deepest gratitude to all those who were supportive and helped us achieve this work, All our teachers who have been there for five years especially Mr. Maache for his guidance and who has been enduring along the way. III

5 ABSTRACT This project is about designing and implementing a DC motor speed controller using Proportional Integral Derivative (PID) algorithm. The controller was implemented on a Field Programmable Gate Array (FPGA) based on System-On- Programmable-Chip (SOPC) technology. The main objective of this project is to control the speed of DC motor to reach a set point. The PID controller attempts to correct the error between a measured process variable and the desired set point by calculating and then outputting a corrective action that can adjust the process accordingly using Pulse Width Modulation (PWM) technique. The system was divided into hardware and software sections. SOPC Builder has been used to design and implement the system-on-chip hardware system that goes inside the FPGA (DE2 Board). The latter employs a NIOS II processor linked to a PWM hardware block. The processor calculates the error between the current and set point speeds and generates a PWM output signal with a specific duty cycle using C software. Finally, the PID controller successfully achieved its target by driving the motor to any set point with an average steady state error of 3.25% and a settling time of seconds. IV

6 Table of Contents Dedications... I Acknowledgement... III Abstract... IV Table of Contents... V List of Figures... VII List of Tables... IX INTRODUCTION... 1 Chapter 1: THEORETICAL BACKGROUND 1.1 Introduction to FPGA FPGA basics FPGA based control system Advantages of FPGA The Altera DE2 development board Features Altera Quartus II NIOS II Embedded System Altera s SOPC builder Controller Design Overview The PID Controller Pulse Width Modulation H-Bridge Chapter 2: The DC MOTOR 2.1 Introduction DC motor Principle of Operation Speed control of a DC motor Our DC Motor System transfer function PID Controller parameters V

7 Chapter 3: HARDWARE & SOFTWARE DESIGN 3.1 Hardware Design On-chip Hardware Design SOPC System VHDL Hardware Blocks ADC block Seven Segment display block Clock Dividers PWM block Off-Chip Hardware Design Software Design PID Algorithm Chapter 4: SIMULATION & IMPLEMENTATION RESULTS 4.1 Simulation Results Simulink Model Implementation Results Open loop results Closed loop results Chapter 5: CONCLUSION 5.1 Conclusion Future Work APPENDIX A VI

8 List of Figures Figure 1.1: Digital Logic Technologies... 3 Figure 1.2: Internal structure of a typical FPGA... 3 Figure 1.3: The Altera DE2 features... 5 Figure 1.4: A NIOS II system implemented on the DE2 board... 7 Figure 1.5: Altera SOPC Builder... 8 Figure 1.6: Block diagram of the complete system... 9 Figure 1.7: Digital PID Controller... 9 Figure 1.8: Closed-loop PID controller Figure 1.9: PWM output at a 10%, 50%, and 90% duty cycles Figure 1.10: The H-Bridge circuit Figure 2.1: DC motor components Figure 2.2: Part of a Multi-polar DC Motor Figure 2.3: The DC motor used in the project Figure 2.4: Schematic representation of the considered DC Motor Figure 2.5: The motor response for a 10V step input Figure 2.6: Output voltage measurement connection diagram Figure 2.7: The plot of the output voltage versus the input voltage Figure 2.8: The plot of angular speed in RPMs versus the output voltage Figure 2.9: The performance and robustness parameters set by PIDtool Figure 2.10: The tuned step response using Matlab Figure 2.11: The corresponding PID controller parameters Figure 3.1: NIOS II System Block using the Altera SOPC builder Figure 3.2: The ADC block Figure 3.3: The Seven Segment display Block Figure 3.4: The Clock Divider block for Seven Segment Figure 3.5: PWM System Schematic Figure 3.6: The PWM block Figure 3.7: The PWM State Diagram Figure 3.8: On-Chip Hardware Circuit VII

9 Figure 3.9: Complete Hardware System Figure 3.10: The software flow diagram of the PID Algorithm Figure 4.1: PID Speed Controller Simulink Model Figure 4.2: Open/closed loop system s step response Figure 4.3: Experimental setup of the system Figure 4.4: Measured Speed (rpm) versus Time (sec) Figure 4.5: Calculated speed error (% of set speed) versus Time (sec) VIII

10 List of Tables Table 2.1: The output values corresponding to the interval {0.166; 0.996} Table 2.2: The motor s output voltage versus the input voltage Table 2.3: The output voltage versus the angular speed in RPMs Table 4.1: Implementation results on open loop system Table 4.2: Implementation results on closed loop system IX

11 INTRODUCTION One of the ways of designing a digital speed control system for DC motor is based on software. In order to run that software microprocessor, PLC, DSP can be used. These mentioned software based techniques employ memory processor interaction. The implementation of speed controlling using microprocessor and DSPs is old and well known. When the system size and complexity increases; Application Specific Integrated Circuits are utilized. The ASIC must be fabricated on a manufacturing line, a process that takes several months, before it can be used or even tested. FPGAs provide an alternative way to quickly prototype hardware controllers using hardware blocks or soft/hard processors. FPGAs are configurable ICs used to implement logic functions. Early generation of FPGAs were most often used as glue logic, which is the logic needed to connect the major components of a system. They were often used in prototypes because they could be programmed and inserted into the board in few minutes. In order to control the speed of a DC motor, a Pulse Width Modulation signal applied to the H-bridge, which in turn control the power delivered to the motor. When the duty cycle is set to 100%, the motor will be running at full speed. The speed of the motor will decrease according to the PWM duty cycle. In order to monitor the actual rotation speed, a taco-generator is used. The taco generates a voltage output signal that is connected to an input-capture subsystem programmed on the FPGA board via an ADC converter. The microprocessor SOPC does the necessary calculations in order to determine the speed of the motor. Without compensation, the system described above is an open-loop controller. This means that the system will not be very accurate and be susceptible to disturbances. In order to correct this, a closed-loop control system needs to be programmed. A closed-loop control system monitors the process output (speed in this project) and actively adjusts the PWM signal to reduce or eliminate error. This control system can be implemented using the classical Proportional-Integral-Derivative (PID) controller due to its simplicity, robustness, effectiveness and applicability for a broad class of systems. 1

12 It is estimated that PID controllers are still employed in more than 95% of industrial processes [1]. The PID is used extensively in the field of servo motor control, robotics, temperature control, and power electronics. It has a long history of development and very mature tuning rules. Overall, the PID is an important tool for the embedded real time digital control designer. They are usually implemented either in hardware using analog components or in software using computer-based systems. In this project, NIOS II Embedded Design Suites were used to create the C-based controller, which is programmed into the DE2 Board. The emergence of FPGAs and hardware description languages (HDL) allows for added dimensions of digital PID controllers, parallelism, and programmable bit widths [2]. Today high end FPGAs can hold several millions gates and have a flexible architecture, which allows the implementation of many complex systems that requires parallel execution. These systems may range from pattern recognition to security algorithms. The software developed on a NIOS II processor provides the user interface through on board peripherals like switches and seven segment displays, so that the user can change the set speed of the motor as well view the data display on seven segment display. The organization of this report is given as follows: In Chapter 1, a theoretical background is introduced. In Chapter 2, an introduction of DC motor is given. In Chapter 3, functional modules of an FPGA based PID controller for DC motor speed control system are explained. In section 4, the implementation and experimental results are discussed. Conclusions and future work are described in the last part. 2

13 Chapter one Theoretical Background

14 Chapter 1 THEORETICAL BACKGROUND 1.1 Introduction to FPGA: FPGA basics: Field Programmable Gate Array (FPGA) can be considered as an array of Configurable Logic Blocks (CLBs) that can be connected together through a vast interconnection matrix to form complex digital circuits [3]. It is an important part of the digital reconfigurable technology as shown in Figure 1.1. Figure 1.1: Digital Logic Technologies [4] Figure 1.2 shows a basic FPGA internal architecture: Figure 1..2: Internal structure of a typical FPGA [3] With current high-end devices exceeding 2000 pins and topping billions of transistors, the complexity of these devices is such that it would be impossible to program them without the assistance of high-level design tools. 3

15 Chapter 1 THEORETICAL BACKGROUND FPGAs have traditionally found use in high-speed custom digital applications where designs tend to be more constrained by performance rather than cost. This has led to the more recent widespread use of FPGAs in common embedded applications [3] FPGA based control system: Modern FPGA devices offer a multitude of resources. Nowadays, the whole complex digital system can reside into the FPGA, leading to the concept of System On a Programmable Chip (SOPC). However, the main advantage FPGAs offer is the possibility to implement algorithms directly into hardware, maintaining the parallelism of the algorithm in the implementation and thus minimizing the execution time. Consequently, the FPGA utilization in industrial control applications became the subject of intensive research [5] Advantages of FPGA: An FPGA is a digital IC that can be programmed to do any type of digital function. There are two main advantages of an FPGA over a microprocessor chip for controller applications: New FPGAs can implement very large hardware designs (VHDL, Verilog, and Schematic) with the ability of being reconfigurable again. They also support hard/soft processors inside them in addition to other hardware peripherals, which are provided as Intellectual Property (IP) blocks to form what is known as System on Programmable Chip (SOPC).These IP blocks are added only if they are needed in the system. The embedded processors are then programmed in Assembly or C like any other microcontroller. FPGAs are programmed using support software and a download cable connected to a computer. Once they are programmed, they can be disconnected from the computer and will retain their functionality until the power is removed from the chip. 4

16 Chapter 1 THEORETICAL BACKGROUND 1.2 The Altera DE2 development board: Features: The DE2 development board contains the following features [6] (see Figure1.3): Altera Cyclone II 2C35 FPGA device with logic elements 512-Kbyte SRAM 8-Mbyte SDRAM 4 pushbutton switches 18 toggle switches 18 red user LEDs 9 green user LEDs 50-MHz oscillator and 27-MHz oscillator for clock sources Two 40-pin Expansion Headers with diode protection Figure 1.3: The Altera DE2 features [6] 5

17 Chapter 1 THEORETICAL BACKGROUND 1.3 Altera Quartus II: Altera Quartus II is the software used to create projects for analysis of hardware designs with the following features: VHDL and Verilog hardware description language (HDL) input Block schematic entry Pin assignment editor Programmer tool Mega functions IP design blocks SOPC Builder Projects can have of a mixture of Verilog and VHDL. For this project, VHDL is used due to our familiarity with this language. Quartus II comes with a range of building blocks of pre-made HDL design blocks referred to as IP cores. Quartus II 9.1sp2 web edition software is used throughout this project. 1.4 NIOS II Embedded System: Altera s NIOS II is a 32-bit soft processor defined in HDL, which can be implemented in Altera s FPGAs using Quartus II. To build a useful system it is necessary to add other functional units such as memories, input/output interfaces, timers, and communications interfaces using Altera s SOPC builder. The NIOS II processor and the interfaces needed to connect to other chips on the DE2 board are implemented in the Cyclone II chip. These components are interconnected through an interconnection network called the Avalon Bus. The memory blocks can be used to provide an on-chip memory for the NIOS II processor. The on board SRAM, SDRAM and Flash memory chips are accessed through their appropriate interfaces. Parallel and serial input/output interfaces provide typical I/O ports used in computer systems. A special JTAG UART interface module is used to connect to the host computer through USB. A JTAG Debug module is used to debug the NIOS II system by downloading programs, starting/stopping execution, setting breakpoints, and collecting real-time execution data. A typical NIOS II system is shown in Figure 1.4: 6

18 Chapter 1 THEORETICAL BACKGROUND Figure 1.4: A NIOS II system implemented on the DE2 board [7] 1.5 Altera s SOPC builder: SOPC builder is a tool used in conjunction with the Quartus II software to implement a system that uses the NIOS II processor on an Altera FPGA device. 7

19 Chapter 1 THEORETICAL BACKGROUND Figure 1.5: Altera SOPC Builder [8] SOPC builder has a library of common components and IP blocks including memory controllers, interfaces and peripherals. It allows the user to easily create a system based on the NIOS II processor, by simply selecting the desired functional units and specifying their parameters from the library and are automatically connected through the Avalon bus interconnect fabric. These parameters include things like: bit width, processor speed/features, memory size, etc 1.6 Controller Design Overview: The aim of this project is to implement a digital Proportional-Integral- Derivative (PID) speed controller for an existing DC motor using an FPGA. This system is implemented as a closed-loop controller. The motor will be driven using a PWM signal, which is used to test the performance of the controller. Figure 1.6 shows the block diagram of the complete system: 8

20 Chapter 1 THEORETICAL BACKGROUND Figure 1.6: Block diagram of the complete system The PID Controller: PID Control is a feedback algorithm that is used in control systems. It utilizes a control loop to update the control algorithm to minimize the error between the desired and the measured point of interest for different applications [9]. There are several conventional and numeric controller types like Proportional Integral (PI), Proportional Integral Derivative (PID) and Fuzzy Logic Controller (FLC). In industry, 95% of controllers are PID type because of its simplicity, applicability and ease of use [10]. At the same time PID controller has some disadvantages namely; the undesirable speed overshoot and the sluggish response due to sudden change in load torque and the sensitivity to controller gains K I and K P. The performance of this controller depends on the accuracy of system models and parameters. Figure 1.7: Digital PID Controller 9

21 Chapter 1 THEORETICAL BACKGROUND The general transfer function of the PID controller output looks like the following: = + + (1.1) Where: E: Error signal Kp: Proportional Constant Ki: Integral Constant Kd: Derivative Constant Figure 1.7 shows a closed-loop PID speed controller. P Reference Speed + _ E I U PWM Motor System Y Measured Speed D Feedback Sensor 1.7 Pulse Width Modulation: Figure 1.8: Closed-loop PID controller PWM signals are pulse trains with fixed frequency and magnitude. However, the width of the pulses (duty cycle) changes from pulse to pulse according to a modulating signal. The PWM signal is still digital because, at any given instant of time, the full DC supply is either fully ON or fully OFF. The voltage or current source is supplied to the analog load by means of a repeating series of on and off pulses. Figure 1.8 shows three different PWM signals with PWM output at a 10%, 50%, and 90% duty cycles, respectively. These three PWM outputs encode three different analog signal values, at 10%, 50%, and 90% of the full strength of the DC voltage [11]. 10

22 Chapter 1 THEORETICAL BACKGROUND 1.8 H-Bridge Figure 1.9: PWM output at a 10%, 50%, and 90% duty cycles [11] The H-Bridge is a very practical way to use when driving a motor. It is named so because it has four switching elements at the "corners" of the H and the motor forms the cross bar. To power the motor, we turn ON two switches that are diagonally opposed. In figure 1.9, imagine that the high side left and low side right switches are turned ON. The current flow is shown in green [12]. Figure 1.10: The H-Bridge circuit [12] The H-Bridge chosen to work with in this project is the L293D H-Bridge [13]. (See Appendix A Figure A.1) 11

23 Chapter two DC Motor

24 Chapter 2 DC MOTOR 2.1 Introduction: Motors are very popular devices that are used in all houses, computers and cars. The principle of controlling motors is not different from AC motors to DC motors. DC motors are rarely used in ordinary applications because all electric supply companies provide alternating current. However, for special applications such as in mines and electric trains, it is advantageous to convert alternating current into direct current in order to use DC motors [14]. The reason is that the speed/torque characteristics of DC motors are much more superior to that of AC motors. Therefore, it is not surprising to note that for industrial drives, DC motors are as popular as threephase induction motors. 2.2 DC motor: The DC motor uses the principles of magnetism to turn. It contains two magnets surrounding a large coil of wire. When electric current flows through the wire, it creates a magnetic field that fights against the surrounding magnets. Thus the motor turns. Figure 2.1: DC motor components [15] Principle of Operation: In any electric motor, operation is based on simple electromagnetism. A currentcarrying conductor generates a magnetic field; when this is placed in an external magnetic field, it will experience a force proportional to the current in the conductor, and to the strength of the external magnetic field. Opposite (North and South) 12

25 Chapter 2 DC MOTOR polarities attract, while like polarities (North and North, South and South) repel. The internal configuration of a DC motor is designed to harness the magnetic interaction between a current-carrying conductor and an external magnetic field to generate rotational motion. Figure 2.2: Part of a Multi-polar DC Motor [14] Speed control of a DC motor: There are four ways to vary the speed of DC motors: By using mechanical gears to achieve the desired speed. This method is generally beyond the capability of most home workshops. Reducing the motor voltage with a series resistor. However, this is inefficient (energy wasted in resistor) and reduces torque. Using a transistor to continuously vary the voltage to the motor. This works well but a substantial amount of heat is dissipated in the power transistor. By applying the full supply voltage to the motor in bursts or pulses, eliminating the voltage losses in the series resistor or transistor. This is called Pulse Width Modulation (PWM) and it is the method to be implemented in this project. It is a very efficient way of providing intermediate amounts of electrical power between fully ON and fully OFF. Short pulses means the motor runs slowly; longer pulses make the motor run faster. 13

26 Chapter 2 DC MOTOR 2.3 Our DC Motor: DC motor used in this project is shown in Figure2.3. Figure2.4 represents the electric circuit of the armature and the free body diagram of the rotor in DC motor. Figure 2.3: The DC motor used in this project Figure 2.4: Schematic representation of the considered DC Motor [17] Unfortunately, this kind of motors is sold without its datasheet and we could not find it on the Internet either since there was no reference number on it. Consequently, a system identification technique is used to get the motor s transfer function System transfer function: A step input of 10V was applied to the motor. Its corresponding response is displayed in Figure

27 Chapter 2 DC MOTOR Figure 2.5: The motor response for a 10V step input From the step response, it can be seen that it is a first order system that has a general transfer function of the form: Where: H s = Kg τs+1 Kg: is the voltage gain 2.1 τ: is the time where the output voltage reaches 63% of its steady state value. Now we take the results shown by this graph between (0.166) to (0.996) sec to find τ in the following table: 15

28 Chapter 2 DC MOTOR Time (sec) V out (V) 0,166 0, ,167 0, ,168 0, ,169 0, ,17 0, ,171 0, ,172 0, ,173 0, ,174 0, ,175 0, ,176 0, ,177 0, ,178 0, ,179 0, ,18 0, ,181 0, ,182 1, ,183 1,14525 Time (sec) V out (V) 0,184 1, ,185 1, ,186 1, ,187 1,4159 0,188 1, ,189 1, ,19 1, ,191 1, ,192 1, ,193 1, ,194 1,8566 0,195 1,8808 0,196 1, ,197 1, ,198 1, ,199 1, ,996 2,71951 Table2.1: The output values corresponding to the interval {0.166; 0.996} By taking a close look at the graph, it can be noticed that there is a remarkable time delay before the output starts rising. This is taken as time T 0 whose value is given in the table above: T 0 = sec Another look to the graph shows the output voltage steady state distinguished by a late time which gives an almost steady value as shown in the table: At time t = 0.996sec, the output voltage V out (steady state) = V Up to now, we can calculate the 63% value of the steady state voltage and then deduce the value of τ from the above table: 16

29 Chapter 2 DC MOTOR V out (63%) = V out (steady state) * 0.63 (2.2) = * 0.63 V out (63%) = 1.72 V From the table, it can be seen that the time when the output voltage equals V out (63%) is: T = sec Due to the time delay in the beginning of the graph, we can find the exact time to rise from 0% to 63% of the steady state τ by subtracting that delay from T: τ = T - T 0 (2.3) = τ = sec = 25 msec Up to now, the only unknown parameter in the DC motor s transfer function is Kg, which represents the voltage gain. First, several measurements were performed of the motor s output voltage (representing its speed) by applying a step input signal of different amplitude each time as seen in Figure 2.6. Figure 2.6: Output voltage measurement connection diagram Both the input and output voltages were measured in Volts. The results obtained from this experiment are shown next: Vin (V) Vout (V) 0 0 0,39 0,67 0,98 1,21 1,48 1,78 2,16 2,44 2,77 3,04 3,32 Table2.2: The motor s output voltage versus the input voltage 17

30 Chapter 2 DC MOTOR The following Figure shows a graphical plot of the output voltage versus the input voltage: Figure 2.7: The plot of the output voltage versus the input voltage From the above graph, it can clearly be seen that the output voltage signal is proportional to the input voltage signal. This means that the slope of this graph representation is the gain of our DC motor:. Kg= Vout Vin =. Vout Vin Kg = Finally, the transfer function of the DC motor used in this project is: H s = s Simultaneously with the previous measurements, we also measured the angular speed of the motor for each input in RPMs (Revolutions Per Minute) which is also expected to be proportional to the output voltage since it is the Tachometer s representation of the motor s speed. The results are shown in the table (2.3). 18

31 Chapter 2 DC MOTOR Vout (V) 0 0 0,39 0,67 0,98 1,21 1,48 1,78 2,16 2,44 2,77 3,04 3,32 W(RPMs) Table 2.3: The output voltage versus the angular speed in RPMs The following Figure shows a plot of the angular speed versus the output voltage: 3000 Measured Speed (RPM) ,39 0,67 0,98 1,21 1,48 1,78 2,16 2,44 2,77 3,04 3,32 Output voltage (V) Figure 2.8: The plot of angular speed in RPMs versus the output voltage As a result, the above graph is almost a straight line. The angular speed is proportional to the output voltage just as it was expected to be. The relationship between these two values Vout and W is given by the following equation: Vout = K W (2.6) Where: Vout: is the output voltage motor. K: is speed constant. W: is the angular speed of the motor in RPMs. The speed constant K can easily be calculated as shown below:. K= Vout W = Vout W K= (V/rpm)

32 Chapter 2 DC MOTOR PID Controller Parameters: After finding the transfer function of the motor, Matlab is used to get the PID controller parameters in order to control the speed of the motor. This was performed using PIDtool, which allows tuning the system response into the desired performance and robustness parameters. These include an overshoot of around 5% and a reasonable rise and settling times as follows: Figure 2.9: The performance and robustness parameters set by PIDtool Figure 2.10 shows the tuned step response to fit the above desired performances parameters. Figure 2.10: The tuned step response using Matlab 20

33 Chapter 2 DC MOTOR When the desired performance requirements were satisfied, the PID controller parameter values are obtained using PIDtool as shown below: Figure 2.11: The corresponding PID Controller parameters 21

34 Chapter three Hardware & Software design

35 Chapter 3 HARDWARE AND SOFTWARE DESIGN 3.1 Hardware Design On-chip Hardware Design: SOPC System: The SOPC builder is used to design the PID System needed in our project. This system is shown in Figure 3.1 bellow: Figure 3.1: NIOS II System Block using the Altera SOPC builder To implement the previous system, the following functional units are instantiated: - NIOS II processor, standard 32-bit - On-chip memory: 32-Kbyte memory arranged in 32-bit words inside the Cyclone II chip - Three parallel I/O interfaces: Two for the input Speeds and one output for the PWM. - JTAG UART interface for communication with the host computer To achieve the desired operation, the NIOS II processor executes a program stored in the on-chip memory. Continuous operation is required, such that as the input switches are changed the output PWM data changes accordingly. Next, the Cyclone II pins are assigned to realize the connections between the parallel interfaces and the actual I/O devices. Then, the FPGA is configured with the designed system. Finally, the NIOS II IDE is used to write, compile, download, and execute the PID C program. In short, the project workflow consisted of performing the following tasks: 22

36 Chapter 3 HARDWARE AND SOFTWARE DESIGN Using the SOPC Builder to design a NIOS II-based system Integrating the designed NIOS II system into a Quartus II project Implementing the designed system on the DE2 board Running the C application program that implement the PID controller on the NIOS II processor VHDL Hardware Blocks: The rest of the hardware blocks inside the FPGA are described in VHDL, and implemented on the FPGA using Quartus II 9.1sp2. This should allow the user to input a desired speed (in RPMs) and be able to monitor the actual speed of the DC motor. During the design process, we designed and created a number of blocks to ease and simplify the system integration task ADC block: The ADC block s role is to control the ADC hardware chip by starting the conversion of the analog speed of the motor to an 8-bit digital data. Then, this block reads the digital value and simultaneously feed it to the seven-segment display block and the PID block. As seen in Figure 3.2, the ADC block has the following signals: ADC_clk is the sampling rate (the frequency at which the ADC does the conversion). EOC (End of Conversion) pulse allows the processor to read the new converted data. It goes high at the end of the conversion. This enables the START signal to receive another data. Figure 3.2: The ADC block 23

37 Chapter 3 HARDWARE AND SOFTWARE DESIGN Seven Segment display block: The main purpose of this block is to display the measured speed of the motor in RPMs as a 4-digit decimal number. The data to display is supplied by the ADC block and goes from 0000 to 2550 RPMs. Figure 3.3: The Seven Segment display Block Clock Dividers: In this project, we mainly worked with the 50MHz internal clock of the FPGA. So whenever a lower frequency is needed, a clock divider is used. It consists of counters to bring down the frequency value to the desired one. This is mainly needed for the seven segment display block, which needs a lower frequency so that the human eye can observe the results being displayed. Figure 3.4: The Clock Divider block for Seven Segment 24

38 Chapter 3 HARDWARE AND SOFTWARE DESIGN PWM block: In this project, a pulse width modulation device (PWMD) is implemented within the FPGA to control the speed of a DC motor. Figure 3.5: PWM System Schematic The modulating signal is in 8-bit digital format. With 50 MHz system clock, a minimum pulse width of 20 ns for the clock period is obtained. Therefore, 20x256=5120 ns is the period necessary to represent all 256 levels of the signal. Hence, the maximum PWM frequency is about 195 KHz. Therefore, in order to generate a PWM signal at this frequency for an 8-bit command signal, the data inside the internal counter of the PWM is compared with the command signal. If the command signal is larger, the PWM output is set to one; otherwise, it is set to zero. Figure 3.6: The PWM block The PWM block is implemented in VHDL. It takes the command data from the PID output and generates a set of pulses to enable the H-Bridge driving the motor. The duty cycle of those pulses depends on the data received from the PID. The comparator compares between the command signal and the internal counter data. If the latter is less than the PID command 25

39 Chapter 3 HARDWARE AND SOFTWARE DESIGN the output will be 1, otherwise it will be 0. In the following Figure, the generation of PWM signal is illustrated as a state flow diagram. Start Initialize PWM internal Counter Read PID command Increment Counter Is Counter > PID Command? No Yes Reset PWM output Set PWM output Send out PWM output End Figure 3.7: The PWM State Diagram All the above hardware blocks are then integrated together to give the On-Chip Hardware subsystem in one Quartus II project. Figure 3.8 illustrates the interconnections between the different blocks 26

40 Chapter 3 HARDWARE AND SOFTWARE DESIGN Figure 3.8: On-Chip Hardware Circuit 27

41 Chapter 3 HARDWARE AND SOFTWARE DESIGN Off-Chip Hardware Design: To be able to implement analog to digital conversion of the measured speed corresponding to the voltage generated by the taco-generator, the ADC0808 [18] 8-bit A/D converter is used (See Appendix A Figure A.2). We have designed a circuit and programmed the chip so that when the analog signal is given as input, the equivalent digital value is sent to the FPGA development board via the GPIO ports. Since the ADC it is an 8-bit converter, Vref (+) = 3.30V and Vref (-) is connected to ground: 0V is represented by (0 in decimal) 3.30V is represented by (255 in decimal) maximum speed. To convert a value of speed X (in volts) to digital D, the following formula is used: = 255 (3.1) 3.30 The motor speed is varying from 0 to around 2560 RPM and the digital data is varying from 0 to 255. Hence, in order to display the speed value, we multiplied whatever measured speed by a factor of 10and then displayed it accordingly. Finally, all the hardware chips are placed on the breadboard and connected to the FPGA according to the schematic shown in Figure

42 Chapter 3 HARDWARE AND SOFTWARE DESIGN Figure 3.9: Complete Hardware System 29

43 Chapter 3 HARDWARE AND SOFTWARE DESIGN 3.2 Software Design: PID Algorithm: The PID parameter values were identified in Chapter (2). P depends on the present error, I on the accumulation of past error, and D is a prediction of future error, based on current rate of change. Once the current speed is measured, this value is subtracted with the set speed value, which is set using the switches, to calculate the tracking error. The weighted sum of these three actions is used to compute the PWM command signal to adjust the process. A new measured value of the speed will be obtained. This new output will be sent back to the controller again to find the new error signal (E). The controller takes this new error signal and computes its derivative and integral again, this process goes on and on until the error signal (E) is almost equal to zero. The above process is implemented in C code and executed on the NIOS II processor in the FPGA. Figure 3.10 shows the software flow diagram of the PID Controller Algorithm: 30

44 Chapter 3 HARDWARE AND SOFTWARE DESIGN Start Initialize all the signals (Kp, Ki, Kd, error, pre_error, output, epsilon, dt, integral I, derivative D, old_output) Get the input for PID Capture old error and old output Calculate error Calculate P, I &D outputs Calculate the new output Output<Min Check Output Output>Max Output = Min Min<output<Max Output = Max Send output to port (PWM Signal) End Figure 3.10: The software flow diagram of the PID Algorithm 31

45 Chapter Four Simulation & Implementation Results

46 Chapter 4 SIMULATION & IMPLEMENTATION RESULTS 4.1 Simulation Results: Simulink Model: Simulink was used during this work in order to simulate PID controller on the motor model obtained earlier. The Simulink model is shown in Figure 4.1: Figure 4.1: PID Speed Controller Simulink Model The previous graph contains two systems: an open loop system and a closed loop system using PID. The scope shown in the circuit illustrates the step signal and both its responses. In order to show the difference between the step response of the motor when the speed is being regulated and when it is not, a step signal is given to each system and their responses were plotted using Matlab. First, a step signal of 1V amplitude shown in red on Figure 4.2 was given to the open loop system and its response is drawn in green. After that, the same previous input step was tried on the closed loop system where the speed is repeatedly regulated. The response using PID controller is plotted in blue. Both responses of the open and closed loop systems are plotted together in order to compare and notice the difference that the PID brings to the system. 32

47 Chapter 4 SIMULATION & IMPLEMENTATION RESULTS Figure 4.2: Open/closed loop system s step response 4.2 Implementation Results: The experimental work was carried out to evaluate the performance of the PID controller. To verify the performance of the controller design on hardware, the On-Chip System is compiled and implemented into the DE2 Board including the NIOS II processor. The NIOS II IDE is then used to compile, load, and execute the PID C code. Three input switches S1, S2 and S3 are used to set the target speeds of 1000 rpm, 1800 rpm, and 2550 rpm respectively without considering the 0 rpm speed which is when no switch or more than one are enabled. Once this is done, the ADC is triggered to sample and convert the speed data. The PID controller C implementation (continuously running on the NIOS II) then calculates the PID control output. This value is sent to the motor through the PWM block. Once the current speed equals the set speed, the motor starts running at that set speed. Meanwhile, the instantaneous motor speed is displayed on four seven-segment digits. To set a new target speed, the above procedure is repeated by changing the switches positions. For purposes of comparison and showing the efficiency of the PID effect on the motor s speed, two cases are evaluated to show the role of the controller: open-loop and close-loop systems. Figure 4.3 shows the experimental setup of the system showing the FPGA board, ADC, H-bridge, and the DC motor. 33

48 Chapter 4 SIMULATION & IMPLEMENTATION IMPLEME RESULTS Figure 4.3: Experimental setup of the system Open-loop loop results In this case, the motor is directly connected to the driver without using the PID (Open loop system). As the set speed is varied, it is observed that the current speed, which is displayed, on the seven segment display is different from the set speed value. Table shows the results obtained from the performed tests: Switches Reference Speed (rpm) Measured Speed (rpm) No/more than one switch 0 0 Switch Switch Switch Table 4.1:.1: Implementation results on open loop system For a reference speed of 0 rpm and 2550 rpm, there was no problem with the results because the PWM signal is either permanently reset preventing the motor from any voltage supplying or permanently set giving the maximum voltage to the motor and hence running at the max speed. But the results obtained from a set speed of 1000 rpm or 1800 rpm were not satisfying since there was around aroun 50% error in the measured speed. 34

49 Chapter 4 SIMULATION & IMPLEMENTATION RESULTS Closed-loop results: In the second case, the digital PID controller successfully implemented using the FPGA and its performance is verified and tested on a DC motor speed control. To be able to perform a comparison with the first case, we repeated the same tests as before with the exact same speed values to see the effect of the PID on the system. Table 4.2 shows the obtained results: Switches Reference Speed (rpm) Measured Speed (rpm) No/more than one switch 0 0 Switch /- Steady State error Switch /- Steady State error Switch Table 4.2: Implementation results on closed loop system To show the way the speed is continuously fixed, the motor was given a set speed of 1000 rpm. The speed values were printed during seconds using the C code executed on the NIOS II processor and then plotted as shown in Figure 4.4: 1400,000 Measured Speed (rpm) 1200, , , , , ,000 0, ,025 0,051 0,076 0,102 0,127 0,153 0,178 0,203 0,229 0,254 0,280 0,305 0,331 0,356 0,381 0,407 0,432 0,458 0,483 0,509 0,534 0,559 0,585 0,610 0,636 0,661 0,687 0,712 Time (sec) Figure 4.4: Measured Speed (rpm) versus Time (sec) The test results showed that the PID controller successfully reached target speed and maintained it thereafter. The experimental settling time is found to be as expected when the PID values were found in chapter-2 which is equal to sec. After the settling time, the speed is rising and dropping with a small steady state error. This is due to the continuous adjustment performed by the PID controller through the PWM digital signal. 35

50 Chapter 4 SIMULATION & IMPLEMENTATION RESULTS For every speed value recorded in the above graph, we calculated its corresponding error as a percentage of the set speed. These error values are then plotted. The results are shown in Figure 4.5: Calculated speed error (%) ,025 0,051 0,076 0,102 0,127 0,153 0,178 0,203 0,229 0,254 0,280 0,305 0,331 0,356 0,381 0,407 0,432 0,458 0,483 0,509 0,534 0,559 0,585 0,610 0,636 0,661 0,687 0,712 Time (sec) Figure 4.5: Calculated speed error (% of set speed) versus Time (sec) In order to get the Steady state error, the average of the absolute error values corresponding to each speed recorded earlier (303 values) is calculated as illustrated next: _ _ = _ _ = 3.25 % It can be clearly seen that this error is very reasonable and the PID controller performed well in regulating the speed according to the desired performance conditions which were set when it was first designed (rise time, settling time, etc ). 36

51 Chapter Five Conclusion

52 Chapter 5 CONCLUSION 5.1 Conclusion In this report, a speed control implementation for DC motor based on SOPC technology was proposed. The aim of this work was to control the speed of a DC motor by FPGA platform using PID controller. The speed control of the DC motor is achieved by controlling the Pulse Width Modulation with the help of the PID controller. This was successfully completed by getting the right parameters (Kp, Ki, Kd) of the controller to set the speed of the motor with an accuracy of plus or minus 3.25% for speed values varying from 0 rpm to 2550 rpm and a settling time of seconds. The design of the project demonstrated how a library of VHDL entities can be built up to form the basic building blocks of digital hardware circuit. Instantiating these blocks in Quartus schematic editor proved to be a very intuitive method of designing such a system. The SOPC Builder also proved to be a valuable tool for the system design and allowed ease and effectiveness in the PID implementation. The use of the FPGA turned out to be very practical since its can implement large hardware which is reconfigurable again. They also support hard/soft processors inside them in addition to other hardware peripherals to form what is called a System On Programmable Chip with only the blocks needed by the system. The software part of the PID controller was successfully implemented by executing a C code on the SOPC system using the NIOS II processor. 37

53 Chapter 5 CONCLUSION 5.2 Future work For future work, the use another analog to digital converter with higher resolution than 8-bit digital data can improve performance. Since the ADC used in this project was giving data from 0 to 255 and the speed was varying between 0 rpm to 2550 making each bit change in the digital data rise the speed with a 10 rpm speed value. An ADC of 10-bits digital data or more would certainly provide more accuracy in the measured speed and hence less steady state error. Another approach worth trying is to implement other types of controllers such as MPC (Model-Based Predictive Control). A comparison can be done between the PID type controller and this type in order to judge their effectiveness, especially for SOPC and FPGA implementation. 38

54 Appendix A The L293D H-bridge s was used in our project. Figure A.1 shows its block diagram and top view: Figure A.1: Block diagram and Top view of L293D H-Bridge [13] The ADC Bit A/D Converters with 8-Channel Multiplexer was also used to convert the analog data into digital. Figure A.2 represents the top view of the ADC0808: Figure A.2: Top view of ADC0808 H-Bridge [18]

55 REFERENCES [1] K.J. Astrom and T. H. Hagglund, New Tuning Methods for PID Controllers, Proc. of 3rd European Conference, pp , [2] Shouling He and Xuping Xu, Hardware/Software Co design Approach for an ADALINE Based Adaptive Control System, Journal of Computers, vol. 3, no.2, pp , Academy publisher, February [3] Altium Designer training module, FPGA Design Basics, February [4] ECE Users pages, visited 16/05/2015 [5] Bogdan Alecsa, Marcian N. Cirstea, Simulink Modeling and Design of an Efficient Hardware-constrained FPGA-based PMSM Speed Controller, Senior Member, IEEE, Alexandru Onea, [6] Altera DE2 user manual, [7] Altera corporation, Introduction to the Altera SOPC Builder, [8] SOPC, Hello from NIOS II, visited 13/05/2015 [9] Ranjay Krishna, Tachometer and Motor Controller, Cornel l University '13, April [10] Manoj Kushwah and Prof. Ashis Patra, Tuning PID Controller for Speed Control of DC Motor Using Soft Computing Techniques, Electrical Engineering Dept, Madhav Institute of Technology and Science, Gwalior, India, [11] Basil Hamed and Moayed Al-Mobaied, Fuzzy PID Controllers Using FPGA Technique for Real Time DC Motor Speed Control, Electrical Engineering Department, Islamic University of Gaza, Gaza, Palestine, [12] Chuck McManis, H-Bridges: Theory and Practice, December [13] Datasheet, L293D H-bridge, SGS-THOMSON Microelectronics, [14] V. K. Mehta, Rohit Mehta Objective Electrical Technology, Google ebook, [15] 02/06/2015 [16] -motors-dc-motor-types 16/05/2015 [17] ctms.engin.umich.edu 16/05/2015 [18] Datasheet, ADC0808/ADC Bit µp Compatible A/D Converters with 8- Channel Multiplexer. Texas Instruments Incorporated, 2014.