Front-end electronic readout system for the Belle II imaging Time-Of- Propagation detector

Transcription

1 Front-end electronic readout system for the Belle II imaging Time-Of- Propagation detector Dmitri Kotchetkov a,*, Matthew Andrew a, Vishal Bhardwaj b, Thomas Browder a, Julien Cercillieux a, Ryan Conrad c, Istvan Danko d, Shawn Dubey a, James Fast c, Bryan Fulsom c, Oskar Hartbrich a, Christopher Ketter a, Brian Kirby a, Alyssa Loos b, Luca Macchiarulo a, Boštjan Maček a, Kurtis Nishimura a, Milind Purohit b, Carl Rosenfeld b, Ziru Sang a, Vladimir Savinov d, Gary Varner a, Gerard Visser e, Tobias Weber a, Lynn Wood c a. Department of Physics and Astronomy, University of Hawaii at Manoa, 2505 Correa Road, Honolulu, HI 96822, USA b. Department of Physics and Astronomy, University of South Carolina, 712 Main Street, Columbia, SC 29208, USA c. Pacific Northwest National Laboratory, 902 Battelle Boulevard, Richland, WA 99354, USA d. Department of Physics and Astronomy, University of Pittsburgh, 3941 O Hara Street, Pittsburgh, PA 15260, USA e. Center for Exploration of Energy and Matter, Indiana University, 2401 North Milo B. Sampson Lane, Bloomington, IN 47408, USA * Corresponding author. address: kotchet@hawaii.edu Abstract The imaging Time-Of-Propagation (itop) detector is a Cherenkov particle identification detector constructed from quartz bars for the Belle II experiment at the SuperKEKB e + e collider. The purpose of the detector is to identify, with high precision, charged hadrons produced in e + e collisions. Belle II particle identification requires detector timing resolution below 50 picoseconds. A novel front-end electronic system was designed, built, and integrated to acquire data from the 8192 channels of the microchannel plate photomultiplier tubes in the itop detector. Sampling of the analog signals is done by switched-capacitor array application-specific integration circuits. The processes of triggering, digitization of windows of interest, readout, and data transfer to the Belle II data acquisition system are managed by Xilinx Zynq-7000 programmable system on a chip devices. Keywords: super B-factory, Belle II particle identification, front-end electronics, Cherenkov radiation, signal sampling, system on a chip 1

2 1. Introduction The Belle II experiment [1] at the SuperKEKB electron-positron collider (High Energy Accelerator Research Organization, KEK, Tsukuba, Japan) is an upgrade of the Belle experiment [2-3] that studied CP-violation and rare physics processes at the Υ(4S) and Υ(5S) resonances and completed data taking in SuperKEKB will collide 7 GeV electron beams with 4 GeV positron beams, with a design instantaneous luminosity of 8 x cm -1 s -1 and a goal of integrating 50 ab -1 of data. Such large data samples will allow measurements of rare B and D meson decays, including those that are suppressed or forbidden by the Standard Model of particle physics. Belle II will also allow unprecedented sensitivity to lepton flavor violating decays of the τ lepton. In addition to searches for new physics, such data samples can lead to a substantial reduction of uncertainties for the processes that were already measured by Belle. To detect rare processes, as well as to maximize the signal to background ratios in the events of interest, requires improved particle identification capabilities. In particular, it is expected that several, rare and previously unobserved, physics phenomena can be explored at SuperKEKB if separation of kaons from pions in the transverse momentum range from 1 GeV/c to 4 GeV/c can be accomplished with 85-90% efficiency while the misidentification rate is maintained below 5% [1, 4]. Improved particle identification performance is also needed for Belle II to minimize the effects of beam backgrounds expected from SuperKEKB. To meet such particle identification requirements in the barrel region of Belle II, a novel Cherenkov detector the imaging Time-Of- Propagation (itop) detector [5-8] was built (Fig. 1). 2. Particle identification with the itop At Belle II, the itop is placed between the Electromagnetic Calorimeter and the Central Drift Chamber (Fig. 2). The itop barrel is divided into 16 modules (Fig. 3). In each module (Fig. 4) the active detection element is a quartz (fused silica) bar that has a thickness of 20 mm and a width of 450 mm (Fig. 5). The bar is glued from two identical 1250 x 450 x 20 mm 3 pieces with a total length of 2500 mm. An internal focusing spherical mirror with a radius of curvature on the spherical surface of 6500 mm is glued to one end of the bar. The mirror has a length of 100 mm and a thickness of 20 mm. A quartz prism is glued to the other end of the bar. The prism has a length of 100 mm, a width of 456 mm, a thickness at the end of the bar of 20 mm, and a prism angle of degrees. When a charged particle passes through the quartz bar, a cone of Cherenkov photons is created. Each of the photons undergoes repeated total internal reflection. As it was demonstrated in Geant4 [9-11] simulations prior to the itop construction, after multiple internal reflections from the surfaces of the bar the photon enters the outer surface of the prism (Fig. 6). The total time of propagation of the photon in the quartz bar, in the spherical mirror, and in the prism is measured. This time measurement is done with respect to a reference time, normally that of the electron-positron collision. The Cherenkov photon emission angle depends on the speed of a charged particle moving through the detector material. For a given momentum, each hadron species (e.g. pions, kaons, protons) emits photons with a characteristic Cherenkov angle. These photons thus arrive at different locations on the outer surface of the prism. There are two groups of photons: those that, after their emission, propagate toward the prism, and those that, after the emission, initially 2

3 propagate toward the focusing spherical mirror. The photons that propagate to the spherical mirror get reflected by the mirror and then propagate toward the prism. The focusing spherical mirror reduces the effects of chromatic dispersion. With a knowledge of the charged particle momentum and of the location of the impact point on the quartz bar, measured by the Central Drift Chamber, the reconstruction algorithm can determine the species of the particle, using the measured x and y positions of the Cherenkov photons and the measured photon propagation times. A single normally incident charged hadron, either kaon or pion, with a momentum of 1 GeV/c to 2 GeV/c produces about Cherenkov photons in one itop bar. Two rows of Hamamatsu R M16(N) microchannel plate photomultiplier tubes (MCP-PMTs) [12, 13] (Fig. 7) are coupled to the outer surface of the prism to collect the Cherenkov photons. Each row contains 16 MCP-PMTs. Every MCP-PMT has a 4 x 4 pixel matrix, thus each photon generated in the quartz bar can be detected by one of 512 available pixels; the lateral dimensions of each pixel are x mm 2. Such a detection scheme allows determination of two coordinates of each photon arriving at the outer surface of the prism. 3. Subdetector Readout Modules The anode voltages from every MCP-PMT channel are amplified, sampled, selectively converted to digital form, and, finally, read out from the itop to the Belle II data acquisition system. The 8192-channel itop front-end electronic (FEE) readout system is organized as an ensemble of 64 compact standalone Subdetector Readout Modules (SRMs). One SRM (Fig. 8) is capable of reading out signals from 128 MCP-PMT anodes. The key element of the itop FEE readout system is an 8-channel custom-designed waveform sampling application-specific integrated circuit (ASIC), named the Ice Ray Sampler version X (Fig. 9) and abbreviated IRSX. This name is derived from earlier waveform sampler designs for neutrino detection experiments in Antarctica [14, 15]. The electronic readout of the 16-module itop is done in a way that every 512-channel itop module is served by four SRMs. One SRM contains 16 IRSX ASICs. Mechanically, the SRM is a board stack with five boards: one Standard Control Read-Out Data (SCROD) board and four identical ASIC carrier boards. The ASIC carrier board hosts four 8-channel IRSX chips, thus reads out the signals from 32 MCP-PMT anodes. The overall itop electronic readout scheme is shown in Fig. 13. Table 1 lists the itop readout components and channel counts. 4. Analog signal sampling The IRSX is an 8-channel multi-gigasample per second waveform sampler. It is fabricated in a 0.25 µm complementary metal-oxide-semiconductor process by the Taiwan Semiconductor Manufacturing Company (TSMC) and can work with input signals in a range from 0 V to 2.5 V. Each IRSX channel uses one switched capacitor array (SCA). SCA-based devices [16] have been used in a number of high energy physics readout systems, since they allow large-scale, low-power, wide dynamic range transient signal acquisition. The basic unit of the SCA is a sample and hold analog storage cell, a circuit that has a 14 ff capacitor and a comparator. When an analog switch for the input signal is closed, the input signal is stored in the capacitor (Fig. 9). 3

4 The charge is held in the capacitor until the charge is overwritten or until a discharge occurs through a leakage current. The sampling capacitor is connected to the storage array and the comparator through a two-stage transfer. The SCA (one per IRSX channel) consists of 16 rows and 32 columns of windows, each having 64 storage cells (Fig. 10). Thus, there are 32,768 analog storage cells available for each channel sampling buffer, or 262,144 (8 x 32,768) cells for one ASIC. Analog sampling is carried out continuously with an operational speed of GSa/s while signal digitization and readout are done only when a trigger is received. The IRSX design also allows for digitization and readout with self-triggering. For that mode of operation, each channel has its own comparator circuit. The trigger fires when an input signal exceeds a positive threshold voltage. The threshold voltage for each channel is set by an on-die digital-to-analog converter (DAC). During itop operation, the signal digitization and readout are activated by external triggers from the Belle II Global Decision Logic system, which in its turn receives ASIC trigger bits prior to issuing the decision for the itop to digitize and read out stored waveforms. The latency of the Belle II Global Decision Logic system is 5 µs. After a trigger arrives, Wilkinson analog-to-digital conversion (ADC) of the waveform samples (Fig. 11) is performed in parallel on the 64 samples corresponding to a single read address, on all 8 channels simultaneously. This high degree of parallel processing compensates for the relatively long conversion time required when using the Wilkinson technique; for Belle II operation the conversion time is set to about 4 µs. Receipt of a trigger blocks writing (in external firmware) so that the stored voltage values are not overwritten until digitization is completed. A common voltage ramp is connected to the positive input of the comparator in every storage cell selected for conversion. For itop operation, the minimum ramp voltage is set to 0.5 V, while the maximum ramp voltage is set to 2.0 V. At the start of a conversion, the voltage ramp increases linearly from the minimum voltage up to the maximum voltage, during which time an 11-bit Gray code counter is incremented. For a given storage cell, when the voltage ramp level exceeds that of the stored sample voltage, the comparator changes state and latches the Gray code value. In addition, the phase of the Gray code counter clock is latched to provide a 12th bit of ADC resolution. By this method, the voltage ramp and comparator convert the stored voltage into a time interval, and the latched Gray code converts this time into an ADC output. With a 12-bit ADC range, corresponding to the 1.5 V range of the voltage ramp, one ADC least-significant bit corresponds to about 0.4 mv. The Wilkinson ramp, the comparators, and the digital counter are internal to the IRSX ASIC. Before becoming an IRSX input signal, the MCP-PMT anode signal is terminated with a 69.8-ohm terminating resistor, alternating current (AC) coupled with a capacitor, and then amplified. A pedestal voltage is applied after AC-coupling of the input signal. This is needed to make a direct current offset, because the digitization is performed only with positive voltages. The control of the data digitization and readout is done by one Xilinx Zynq-7000 Z-7030 system on a chip (SoC). The Z-7030 SoC is programmed to address all windows, from 0 to 509, sequentially in every event, keeping windows 510 and 511 as scratch windows. The IRSX sampling speed is set by an adjustable control voltage. 4

5 5. ASIC carrier board Four IRSX chips are mounted on every ASIC carrier board (Figs. 14 and 15); a pair of ASICs is mounted on each surface of the board. Two spring loaded pogo pin assemblies 1 are installed at one of the edges of the carrier board. The pogo pins (one for each MCP-PMT anode) pick up the anode signals for amplification and further sampling and digitization by the IRSX ASICs. Each anode signal is amplified by a two-stage amplification chain before the signal becomes the input signal of the IRSX channel; in total, there are 64 operational amplifiers mounted on each carrier board for this purpose. The amplification chain transimpedance gain is equal to 11.4 kiloohms. Such a gain allows sampling MCP-PMT single photon signals with a photomultiplier gain of no less than 2 x 10 5 and with a detection efficiency, defined as the ratio of the number of detected photons over the number of incident photons, of no less than 70%. The ASIC carrier board has one Z-7030 SoC that provides necessary configuration settings and writes s±trobes to all four IRSX chips. In addition, the Z-7030 SoC reads out digital data from all the ASICs of the carrier. The ASIC carrier board has mezzanine connectors that allow the interconnection of four carrier boards. The connectors support Serializer/Deserializer (SerDes) communication, transmission of low-voltage differential signaling (LVDS) control signals, and transmission of digital data with gigabit per second speeds. 6. SCROD board In the SRM, one of the four interconnected carrier boards is electrically and mechanically connected to the SCROD board (Figs. 16 and 17). The primary element of the SCROD board is a Xilinx Zynq-7000 Z-7045 SoC controller that receives the data recorded by the four carrier Z SoCs. Upon the receipt of the data, the Z-7045 SoC controller rapidly processes the waveform data and extracts the time at which the photon hits a particular MCP-PMT pixel. The Z-7045 SoC controller also calculates an estimate of the value of the charge collected at the anode that corresponds to the pixel of interest. The extracted hit time, together with the estimated charge value, is called feature extracted data. The controller assigns the feature extracted data an event number and forwards the data to the Belle II data acquisition (DAQ) system [17]. The itop FEE readout system records feature extracted data, instead of full waveform data, due to the itop maximum data size requirements from the Belle II DAQ system. The itop will transfer data to the Belle II DAQ system with a speed of up to 120 MB/s with an average Belle II DAQ trigger rate of 30 khz. It is assumed that the itop will operate at 2.5% occupancy, while the size of a single itop event will be 4 kb. Clock and triggering signals come to the SCROD from the Belle II timing distribution system [18] and are sent by the Z-7045 SoC controller to each of the four carrier Z-7030 SoCs through an LVDS fan-out. The digital data, recorded by the carrier Z-7030 SoCs, are sent to the Z-7045 SoC controller through a gigabit per second link realized with the mezzanine connectors. The SCROD board is equipped with two Avago AFBR-57D7APZ small form-factor pluggable fiber optical transceiver modules. One module sends the digital data to the Belle II DAQ system, the other transmits trigger bits from the IRSX ASICs to the Belle II Global Decision Logic 1 A custom lower force version of the pogo pins from Mill-Max Manufacturing Corporation. 5

6 system. The Avago AFBR-57D7APZ module allows optical transmission speed of up to 8 gigabyte per second. The SCROD also has double data rate random access memory (RAM) to store ASIC parameters and to buffer incoming data. Firmware downloads for the controller and carrier SoCs can be done through either of two Joint Test Action Group (JTAG) mounted connectors. One JTAG connector is useful for debugging purposes when an SRM takes data in a laboratory setting. The other JTAG connector is used during itop operation when the SRM is integrated in the detector. 7. Heat removal from the readout modules The power dissipated at the SRM can be as large as 80 W. Among the board stack components, the main power consumers are the SoCs, the IRSX ASICs, the operational amplifiers, and the voltage regulators. To properly remove heat from the SRM, all ASIC carrier and SCROD boards are attached to aluminum plates. The plates are machined in such a way that they allow niches and open spaces, so that the SCROD and ASIC carrier on-board electrical components remain unobstructed. Copper disks are epoxied to the carrier Z-7030 SoCs. A thermal gap filler paste is placed between the copper disks and the aluminum plates to improve the disk-to-plate coupling and improve the heat removal efficiency. When the board stack is assembled, the edges of the ASIC carrier and SCROD boards are sandwiched between the edges of the aluminum plates. In order to increase the heat flow from one plate to another, the edges of each board have a dense array of stitching vias that are filled with thermal grease. 8. High voltage board Since each SRM acts as a standalone readout unit, it is supplied with its own high voltage (HV) board (Fig. 18). One SRM reads out signals from eight MCP-PMTs, thus one HV board has eight channels. Each channel is a 400-megaohm resistive divider, coupled with high voltage transistors. The board delivers high voltage to a photocathode and to the microchannel plates of the MCP-PMT. The board is enclosed in an aluminum case, to which the SRM is mechanically attached, and each HV board is mechanically attached to a water cooled aluminum plate. Water, while circulating through the pipes embedded in the plate, removes the heat from the HV board and from the board stack. Pogo pins are installed on the HV board to output the high voltage. The make and the model of the pogo pins are the same as of the pogo pins installed on the ASIC carrier boards. The MCP-PMT operating voltages range from about 2100 V to about 3200 V. 9. Front Board Charges from the anodes of the MCP-PMT are collected via a special Front Board (Figs. 19, 20, and 21). In its working position, the Front Board is oriented parallel to the back surfaces of the MCP-PMTs. The Front Board has pin sockets installed in blind holes. The sockets hold MCP- PMT pin wires; one board holds four MCP-PMTs. A 4 x 2 array of MCP-PMTs, corresponding 6

7 to one SRM and to 128 itop channels, are served by two Front Boards. The sockets are wireconnected to pads on the opposite surface of the Front Board. When the SRM is installed in the itop, the ASIC carrier pogo pins are pressed against the pads that are connected to the MCP- PMT anode sockets of the Front Board. The signals from the anodes are then picked up by the pogo pins. In addition to transferring the anode charge signal to the itop SRM, the Front Board distributes the high voltage from the HV board to the MCP-PMT photocathode and microchannel plate contacts. Similar to the anode signal sockets, there are sockets on the Front Board for the MCP-PMT photocathode and microchannel plate pin wires, and those sockets have corresponding pads. The HV board pogo pins are pressed against those pads when the HV board is installed in the itop module to bias the MCP-PMTs. 10. Firmware The itop FEE readout system firmware was developed and implemented for Xilinx Zynq-7000 Z-7045 and Z-7030 SoCs. Each SoC combines a high-performance 28 nm Kintex-7 fieldprogrammable gate array (FPGA), a dual-core ARM Cortex-A9 processor, an on-board memory, and an extensive peripheral set in a single package. This allows the system design to be customized both for speed of the FPGA and for flexibility of the processor. In every SRM, the channel level trigger data are received by the Z-7045 SoC from four ASIC carrier board Z-7030 SoCs via custom serial interfaces implemented on standard FPGA Input/Output (I/O) interfaces (Fig. 22). The data are collected via dedicated gigabit transceivers (GTXs) that run a communication protocol, called a Pretty Good Protocol or PGP, developed at SLAC National Accelerator Laboratory [19, 20]. After arrival at the Z-7045 SoC, the data are streamed out through a GTX, connected to a fiber optic transceiver. The fiber optic transceiver relays the data to the Belle II Global Decision Logic, to be combined with data from other Belle II subsystems to initiate the itop system level triggers. These triggers, along with a divided copy of the SuperKEKB Radio Frequency (RF) clock, are distributed via Category 7 twisted pair (CAT7) cable and are received by a serial interface. The triggers are then fanned out to the ASIC carrier boards via mezzanine connectors. In response, each ASIC carrier transmits the data back, which are buffered, transmitted to the Processing System (PS) of the SoC via a built-in high performance Advanced extensible Interface (AXI), and are then pedestal subtracted and feature extracted. The data flow is controlled by registers that reside in the Programmable Logic (PL) of the SoC and are accessible via a general purpose AXI interface. The processed data are sent back to the PL to be buffered and transferred to the Belle II DAQ system via the specially developed Belle2Link protocol [21]. The primary function of the Z-7030 SoC firmware is to interface to four on-board IRSX ASICs (Fig. 23). Asynchronous, width encoded trigger bits from each ASIC channel are monitored by the SoC. When a photon is recorded from an MCP-PMT pixel, a time stamp of the event is assigned. In addition, triggers are monitored to tag those regions in the analog memory that have hits, and to avoid overwriting hits that are not yet digitized. Upon receipt of a system trigger from the SCROD, an ASIC Master Control block coordinates digitization and readout of the desired IRSX channels and analog memory regions. Digitized data are buffered within each IRSX control block, and multiplexed back to the SCROD via GTX interfaces running the PGP protocol. Register transactions are also relayed via this protocol from the SCROD. The ASIC 7

8 carrier PS is primarily used for monitoring auxiliary devices, such as voltages and temperature sensors. 11. Interface with the Belle II data acquisition system and with the Belle II timing system A specialized Common Pipelined Platform for Electronic Readout (COPPER) version III (Fig. 28) was developed for the Belle II experiment as a main component of the DAQ system [17]. COPPER-III is a 9U Versa Module Europa (VME) platform, the main component of which is a Peripheral Component Interconnect mezzanine card with a 32-bit 1.6 GHz Intel Atom Z530 processor. Four High Speed Link Boards (HSLBs) installed on the COPPER-III board (also with mezzanine connectors) collect gigabit per second data through optical links from four itop SRMs. One COPPER-III platform collects data from one itop module. The HSLB on-board controllers are Virtex-5 LXT FPGAs. The data collected from the itop module are forwarded to the Belle II event building system. A copy of the MHz SuperKEKB RF clock, divided by four, is provided to the SRMs from the Belle II front-end timing switch (FTSW) system [18]. For this purpose, dedicated FTSW boards (with a 6U VME form factor) were designed and fabricated. The on-board controllers of the FTSW boards are Virtex-5 LX FPGAs. One FTSW board is needed for two itop modules. The jitter of the Belle II global clock timing system is in the range from 20 ps to 30 ps. 12. Performance evaluation of the itop FEE readout system Performance of the ASIC carrier boards, the SCROD boards, and the SRMs was evaluated by a variety of measurements that were performed in four campaigns. During the first performance evaluation campaign, all ASIC carrier boards were tested individually. For each test, the front-end readout system was composed of a single carrier board attached to a SCROD board. A single SCROD board was used through all measurements, while all of the ASIC carrier boards, to be used in the SRMs, were evaluated. The measurements, for every channel of the four tested IRSX chips of each carrier board, included: - measuring amplitudes and root-mean-square deviations of the pedestal signals and checking that these parameters were within specifications, - measuring the trigger threshold voltages to verify that they were within specifications, - probing read and write of key IRSX registers responsible for the control of the sampling, - sampling and digitizing a 160 MHz sine wave signal, with an amplitude of 1 V, to verify that the follow-up reconstruction of the signal from the data does not result in discontinuities at window boundaries in the reconstructed sine wave, - measuring the time delay between the leading edges of two 1.5 V pulses of 7 ns widths; the time delay between the two calibration pulses was 20 ns. The measurement of the time delay between two pulses demonstrated that the nominal time resolution specification of the IRSX readout channel ranges from 20 ps to 30 ps (Fig. 24). The gains of the two-stage amplifier chains for each channel of the ASIC carrier board were also measured to ensure that they were within predefined specifications. Those tests were 8

9 done without MCP-PMTs, using a special emulator board, which had contact pads of a similar geometry to those of the Front Boards. During the measurements, the carrier board pogo pins were pressed against the pads on the emulator board in the same way as they are pressed against the pads on the Front Board when the carrier is a part of the SRM installed in the itop (Fig. 25). The gains were measured when the emulator board pad contacts had voltages similar to those of the MCP-PMT anode signal voltages on the pad contacts of the Front Board. The second performance evaluation campaign included testing firmware programming of all SCROD boards, together with accessing to their RAMs. In addition, quality assurance of all optical transceivers mounted on the SCROD boards was done. In the third performance evaluation campaign, the assembled SRMs were tested at the laser test bench (Fig. 26). The test simulated data taking for the SRM when it is installed in the itop. The laser was tuned for single photon detection by a single MCP-PMT pixel with the photomultiplier operational gain in the range from 2 x 10 5 to 3 x 10 5 and the detection efficiency of no less than 80%. During the measurements, the laser was triggered by an 800 Hz clock. In addition, a calibration pulse, completely independent from the laser trigger, was sent to the SRM. A copy of the MHz clock, divided by four, was provided to the SRM by one FTSW board. The measured time was the time between the leading edge of the reconstructed pulse from the MCP-PMT signal and the leading edge of the reconstructed calibration pulse. The expected time resolution of SRM channels coupled with the MCP-PMT anodes was a quadrature sum of the IRSX channel timing resolution, the MCP-PMT transit time spread, which value is in the range from 30 ps to 40 ps, the FTSW board clock jitter, which value is in the range from 20 ps to 30 ps, and 25 ps/count resolution of the time-to-digital converter (CAMAC Phillips Scientific 7186) used at the test bench. The time resolution of the SRM channels at the laser test bench was found to be in the range from 60 ps to 90 ps (Fig. 27). The itop FEE readout system must successfully sustain the radiation loads during the operational lifetime of Belle II, which is expected to be at least 10 years. It was estimated that, while operating at the design SuperKEKB instantaneous luminosity of 8 x cm -2 s -1, Belle II will accumulate a total fluence of 1 MeV equivalent neutrons of 15 x n/cm 2 and a total radiation dose of 50 Gy during 10 years of operation [22]. To verify radiation hardness, the SCROD and ASIC carrier boards were tested at the Radiation Standards and Calibration Laboratory facilities at the Pacific Northwest National Laboratory [23] in the fourth evaluation campaign [24]. The tested readout system consisted of one carrier board attached to the SCROD board (a configuration similar to that used during the first FEE evaluation campaign). Initially, the tested system was exposed to a flux of neutrons from a Cf-252 source, with fluence ranging from 1.5 x n/cm 2 to 3.6 x n/cm 2. The system was then subjected to a gamma ray dose ranging from 49 Gy to 51 Gy from a Co-60 source. The tested system operated continuously during the irradiation and was monitored for loss of communication, errors in data acquisition program configuration, and changes in voltage and current draw in the SCROD and ASIC carrier boards. A constant low rate of recoverable single event upsets was observed during the neutron irradiation. A gradual but permanent increase in the board current draw by less than 5%, with no accompanying faults, was caused by the gamma ray exposure. In both cases, no serious permanent damage was incurred by the on-board components. From these studies it was concluded that the SCROD and ASIC carrier boards will function in the radiation environment of Belle II over its lifetime. It was also estimated that the itop FEE readout system will have 9

10 approximately 70 ± 23 single event upset errors in one Belle II operation year equal to 10 7 seconds. 13. Conclusion In total, 78 SRMs were assembled from the fabricated SCROD and ASIC carrier boards. 64 board stacks were installed in the itop detector, with 14 spare board stacks. The installed SRMs made up the integrated itop front-end electronic readout system. Commissioning of the itop FEE readout system included in situ data taking from calibration laser and cosmic ray muon events with and without a 1.5 T magnetic field of the Belle II solenoid. The data taking demonstrated that the performance of the SCROD boards, ASIC carrier boards, and SRMs is comparable to or surpasses their performance during the first, second, and third evaluation campaigns. To date, the itop data acquisition operation proves robustness of the SRMs, as the reconstructed data show no signs of the FEE readout system performance degradation. Development of online and offline calibration algorithms, capable of reconstructing laser, cosmic ray muon, and e + e collision data with a time resolution of less than 50 ps, is underway. Acknowledgments We thank Roy Tom and Curtis McLellan of the University of Hawaii for their work on fabricating the SRM heat removal components and on fabricating testing tooling; Marc Rosen of the University of Hawaii for his work on building the laser test bench; Steven Covin of the University of Hawaii for his work on the SRM assembly; Louis Ridley, Larry Ruckman, and Robin Caplett of the University of Hawaii for their work on designing printed circuit boards for early versions of the itop FEE readout system; Christina Yee, Casey Honniball, and Grace Jung of the University of Hawaii for their work on soldering the printed circuit boards for the early versions of the itop FEE readout system; Xin Gao, Sergey Negrashov, Chester Lim, and Andrew Wong for their work on writing and verifying data acquisition firmware and software for the early versions of the itop FEE readout system; Seth Roffe, Nathan Herring, and Gregory Suehr of the University of Pittsburgh for their work on the performance evaluation of the SCROD boards; Joe Rabel, George Zuk, and David Emala of the University of Pittsburgh for their work on fabricating low voltage supply cables and custom connectors that interface the SCROD and the FTSW boards; Richard Lundy of the Pacific Northwest National Laboratory for his work on the pogo pin assembly installation; Craig Bookwalter of the Pacific Northwest National Laboratory for his work on authoring data acquisition code and on performance evaluation of an itop prototype at a test beam; John Vanderwerp of Indiana University for his work on fabricating the Front Boards; Michael Lang of Indiana University for his work on fabricating the High Voltage Boards; Marko Petric of Jožef Stefan Institute for his work on developing a Geant4 model of Cherenkov photon propagation in the itop module quartz components. We also thank all members of the Belle II TOP/bPID detector group who worked on installing the SRMs in the itop modules on-site at KEK, on commissioning the itop FEE readout system, on taking calibration data, on developing online and offline calibration software, and on monitoring the itop FEE readout system. This work was supported by the U.S. 10

11 Department of Energy contracts DE-AC05-76RL01830, DE-SC , DE-SC , DE- SC , and DE-SC Pacific Northwest National Laboratory is managed and operated by the Battelle Memorial Institute. References [1] T. Abe, et al., Belle II Technical Design Report, KEK-Report , [2] M. T. Cheng, et al., A Study of CP Violation in B Meson Decays: Technical Design Report, KEK Report 95-1, [3] A. Abashian, et al., The Belle detector, Nucl. Instr. and Meth. A, 479 (2002) [4] D. M. Asner, et al., US Belle II Project Technical Design Report, available at (2013). [5] K. Nishimura, et al., An imaging time-of-propagation system for charged particle identification at a super B factory, Nucl. Instr. and Meth. A, 623 (2010) [6] L. Ruckman, et al., Development of an Imaging Time-of-Propagation (itop) prototype detector, Nucl. Instr. and Meth. A, 623 (2010) [7] K. Nishimura, The time-of-propagation counter for Belle II, Nucl. Instr. and Meth. A, 639 (2011) [8] Kenji Inami, TOP counter for particle identification at the Belle II experiment, Nucl. Instr. and Meth. A, 766 (2014) 5-8. [9] S. Agostinelli, et al., Geant4 a simulation toolkit, Nucl. Instr. and Meth. A, 506 (2003) [10] J. Allison, et al., Geant4 developments and applications, IEEE Trans. Nucl. Sci., 53 (2006) [11] J. Allison, et al., Recent developments in Geant4, Nucl. Instr. and Meth. A, 835 (2016) [12] K. Inami, et al., Cross-talk suppressed multi-anode MCP-PMT, Nucl. Instr. and Meth. A, 592 (2008) [13] S. Hirose, et al., Development of the micro-channel plate photomultiplier for the Belle II time-of-propagation counter, Nucl. Instr. and Meth. A, 787 (2015) [14] G. S. Varner, et al., The large analog bandwidth recorder and digitizer with ordered readout (LABRADOR) ASIC, Nucl. Instr. and Meth. A, 583 (2007) [15] G. Varner, et al., The first version buffered large analog bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors, Nucl. Instr. and Meth. A, 591 (2008) [16] S. A. Kleinfelder, Development of a switched capacitor based multi-channel transient waveform recording integrated circuit, IEEE Trans. Nucl. Sci., 35 (1988) [17] M. Nakao, et al., Data acquisition system for Belle II, JINST, 5 (2010) C [18] M. Nakao, Timing distribution for the Belle II data acquisition system, JINST, 1 (2012) C [19] R. Herbst, Pretty Good Protocol Design Specification, available at (2006). [20] R. Herbst, Pretty Good Protocol Version 2 Design Specification, available at =slides&confid=600 (2011). 11

12 [21] Dehui Sun, et al., Belle2Link: A Global Data Readout and Transmission for Belle II Experiment at KEK, Phys. Procedia, 37 (2012) [22] T. Nanut, Top beam background, November 2014 Belle II General Meeting, available at d=1223 (2014). [23] D. E. Bihl, et al., Radiation and Health Technology Laboratory Capabilities, PNNL Rev. 2, available at rev.2.pdf (2005). [24] B. G. Fulsom and L. S. Wood, Radiation hardness testing of itop SCROD and carrier boards (v.1.0 Jan ), BELLE2-NOTE-0040, available at (2015). Table 1 The itop readout components and channel counts. Detector Module SRM ASIC Carrier IRSX chip Channels Detector Module SRM ASIC Carrier IRSX chip Channels

13 Figures Figure 1. Location of the imaging Time-Of-Propagation detector in Belle II. VXD: Vertex Detector. CDC: Central Drift Chamber. ECL: Electromagnetic Calorimeter. ARICH: Aerogel Ring-Imaging Cherenkov Detector. BKLM: Barrel Kaon-Long and Muon detector. EKLM: Endcap Kaon-Long and Muon detector. 13

14 itop Electromagnetic Calorimeter Central Drift Chamber Central Drift Chamber Electromagnetic Calorimeter itop Figure 2. Cross-sectional view of the Belle II detector. The itop barrel is placed between the Electromagnetic Calorimeter and the Central Drift Chamber, all of which are located inside the 1.5 T superconducting solenoid. 14

15 Figure 3. Sixteen itop modules arranged in a barrel. Figure 4. itop module showing the bar box. 15

16 Bar/mirror width 450 mm Prism length 100 mm Prism width 456 mm Photosensor array width 444 mm Thickness 20 mm Prism height 51 mm Length 2600 mm 2 x 1250 mm mm Figure 5. Dimensions of the itop module quartz components. charged particle Figure 6. Geant4 simulated passage of a 2 GeV charged particle through the itop module quartz components. The propagation path of Cherenkov photons from a kaon is in red. The propagation path of Cherenkov photons from a pion is in green. 16

17 Figure pixel Hamamatsu R M16(N) microchannel plate photomultiplier tube. The dimensions are 27.6 x 27.6 x 13.1 mm 3 without pin wires and 27.6 x 27.6 x 16.7 mm 3 with pin wires. 17

18 Figure 8. Ice Radio Sampler version X (IRSX) die photograph. 18

19 Write Strobe Trigger Vin T1 to ADC T2 Csample Vpedestal Figure 9. First stage of a sample and hold storage cell. 19

20 windows samples Figure 10. Switched capacitor array for one IRSX channel. Samples in window 170 are shown. 20

21 Vin Vramp Vcomp time Vin Vramp Ramp Generator Comparator Clock Vcomp Register D (0:11) 12 Gray Code Counter Figure 11. Wilkinson analog-to-digital conversion process performed on one sample. 21

22 Figure 12. Subdetector Readout Module (SRM). 22

23 ASIC carrier 4 IRSX ASICs 8 MCP- PMTs SRM ASIC carrier ASIC carrier ASIC carrier 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs ASIC carrier 4 IRSX ASICs itop module 8 MCP- PMTs 8 MCP- PMTs SRM SRM ASIC carrier ASIC carrier ASIC carrier ASIC carrier ASIC carrier ASIC carrier ASIC carrier 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs ASIC carrier 4 IRSX ASICs 8 MCP- PMTs SRM ASIC carrier ASIC carrier ASIC carrier 4 IRSX ASICs 4 IRSX ASICs 4 IRSX ASICs Figure 13. itop readout scheme. 23

24 pogo pin assemblies amplifiers Z-7030 ASIC ASIC connectors to ASIC carrier Figure 14. ASIC carrier board, view from top. 24

25 pogo pin assemblies amplifiers ASIC ASIC connectors to ASIC carrier or SCROD Figure 15. ASIC carrier board, view from bottom. 25

26 debugging trigger link data link programming and clock Figure 16. SCROD board, view from top. 26

27 RAM connectors to ASIC carriers Z-7045 low voltage power Figure 17. SCROD board, view from bottom. 27

28 pogo pin assembly Figure 18. High Voltage Board. 28

29 sockets for MCP-PMT anode and HV contacts (one board per four MCP-PMTs) Figure 19. Two adjacent Front Boards to serve one SRM. View from MCP-PMTs. 29

30 contact pads for ASIC carrier pogo pins contact pads for HV divider board Figure 20. Two adjacent Front Boards to serve one SRM. View from the SRM. 30

31 Front board Cooling pipes Prism Volume where the SRM is located High voltage board Figure 21. SRM installation space in an itop module. 31

32 T/T B2TT 508.9/4 MHz Trigger PL Data PS System Trigger Trigger Stream (Aurora) Serial Trigger Buffer and Sorter Serial Local Registers Serial Serial AXI-Lite Bus GTX GTX Register Data GTX GTX GTX GTX Register Data Output Data Buffering Input Data Buffering Pedestal calculation PS Main Feature extraction RAM mezzanine connectors Figure 22. SCROD firmware algorithm. PL: Programmable Logic that corresponds to the FPGA portion of the SoC. PS: Processing System that corresponds to the processor of the SoC. The processor has a reduced instruction set computer (RISC) architecture, and belongs to the Advanced RISC Machines (ARM) architecture family. T/T: trigger and timing. B2TT: Belle II Trigger and Timing. System Trigger and MHz SuperKEKB RF clock, divided by four, are fanned out within the PL. A CAT7 cable is used to receive T/T signals. Trigger and data are transmitted through fiber optic links. AXI-Lite Bus and PS Main are interfaced with a general purpose AXI interconnect. Input Data Buffering and PS Main are interfaced with a high performance AXI interconnect. Output Data Buffering and PS Main are interfaced with a high performance AXI interconnect. Pink blocks indicate standard firmware interfaces used throughout Belle II, violet blocks (GTX) indicate FPGA primitives, and blue blocks indicate custom firmware blocks used with the SRM. The pink block that is interfaced with the Output Data Buffering, AXI-Lite Bus, and GTX is part of Belle2Link protocol. Red arrows show the data flow. 32

33 mezzanine connectors PL PS Clock Trigger Serial T/T AXI-Lite Bus Sequencer Control Register Data GTX Output Data Buffering Readout Buffering PS Main Status Monitoring Register Interface Trigger Monitoring ASIC Master Control Analog Memory Digitization Data Readout Auxiliary Monitoring Serial Data Interface Channel-Level Triggers Memory Addressing Digitization (Gray Code) Serial Data Interface ASIC (x 4) Figure 23. ASIC carrier firmware algorithm. PL: Programmable Logic that corresponds to the FPGA portion of the SoC. PS: Processing System that corresponds to the processor of the SoC. The processor has a reduced instruction set computer (RISC) architecture, and belongs to the Advanced RISC Machines (ARM) architecture family. T/T: trigger and timing. AXI-Lite Bus and PS Main are interfaced with a general purpose AXI interconnect. Input Data Buffering and PS Main are interfaced with a high performance AXI interconnect. Output Data Buffering and PS Main are interfaced with a high performance AXI interconnect. The violet block (GTX) indicates FPGA primitives. Blue blocks indicate custom firmware blocks used with the SRM. The brown block indicates an IRSX control block (one for each ASIC). The Trigger block is fanned out within the PL. The Clock block generates and distributes 21 MHz, 170 MHz, and 254 MHz clocks, which are fanned out within the PL. Data Readout function is done through a 170 MHz 33

34 serial interface. Digitization is done with the 254 MHz clock. ASIC Memory Addressing is controlled through the 170 MHz serial interface. Channel-Level Triggers are sent by asynchronous bits. The Register Interface is a 21 MHz serial interface. Red arrows show the data flow. Figure 24. Typical single channel timing performance from a measurement of two pulses delayed by 20 ns. 34

35 MCP-PMT emulator Figure 25. Reading out emulated MCP-PMT signals by a single ASIC carrier board. 35

36 data fiber link programming and clock high voltage laser fiber MCP-PMT water cooled plate Figure 26. SRM in the laser test bench. 36

37 Figure 27. Typical single channel timing performance from a measurement of a delay between an MCP-PMT signal and a reference pulse at the laser test bench. The overall SRM timing resolution was a quadrature sum of the IRSX channel timing resolution, the MCP-PMT transit time spread of ps, the FTSW jitter of ps, and 25 ps/count resolution of the time-todigital converter (CAMAC Phillips Scientific 7186) used at the test bench. The long tail in the right side of the distribution, corresponding to greater measured times, is due to photoelectron backscattering effects in the MCP-PMT. 37

38 High Speed Link Board 1.6 GHz Intel Atom Z530 CPU global clock and trigger Figure 28. Common Pipelined Platform for Electronic Readout version III (COPPER-III). 38