Marconi Applied Technologies

Transcription

1 Marconi Applied Technologies L3M65 Series Low Light CCD Camera Module Set FEATURES Allows evaluation of the CCD65 sensor. Allows assessment of CCD65 drive signals. Flexible operating modes assist development of a userdefined electronics package. APPLICATIONS TV camera development. Slow-scan camera development. CCD evaluation. INTRODUCTION The L3M65 Series module set is part of the new L3Vision range of very high sensitivity CCD cameras. The module set, comprising four separate PCB assemblies, provides all the electronics (apart from a headboard) required to produce a camera based on the Marconi Applied Technologies range of CCDs. A Logic PCB provides all the timing signals necessary for driving the CCD65 in TV mode, including video processing, which produces either CCIR or RS70 video output. This board is normally plugged into the Bias and Buffer PCB, but it may be removed, allowing the user to feed drive signals directly into another connector on the Bias and Buffer board. The Bias and Buffer board generates all the DC bias voltages required by the CCD, and buffers the CCD drive signals. It is fitted with a 25-way D -type connector, which allows connection to the user s own headboard. An analogue output is provided for further processing by the user. Two High Voltage PCBs are provided. The first is based on resonant mode operation, and is designed for operation at. MHz pixel rate, required for operation of the CCD65 at TV rates. The second is designed for operation over a range of frequencies, set by the user, up to a maximum of 5 MHz. This is intended for use in slow-scan mode. OPTIONS 525-line operation, anti-blooming L3M65-05A 625-line operation, anti-blooming L3M65-06A 525-line operation, non anti-blooming L3M65-05B 625-line operation, non anti-blooming L3M65-06B BIAS AND BUFFER MODULE There is a row of six potentiometers on the Bias and Buffer module that allow bias voltages and CCD clock amplitudes to be adjusted. It is important that these are adjusted to obtain optimum low light imaging performance. The potentiometers are labelled as follows: Label Description Typical values for CCD65 (see note) DC DC Phase Voltage +4.0 V (b) ABD Anti-Blooming Drain Voltage +5.0 V (c) RD Reset Drain Voltage +8.0 V (d) GD Guard Drain Voltage +8.0 V (e) ISH Image and Store Clocks +9.0 V (f) High Level Voltage SS Substrate Voltage +4.5 V (g) Note: Other low light CCDs may require different bias voltages. Refer to the appropriate CCD data sheet for further information. Test points are provided on the module to allow these voltages to be measured easily. The HV modules are also available as separate items: L3MRS L3MHV Resonant Clocked Marconi Applied Technologies Limited, Waterhouse Lane, Chelmsford, Essex CM 2QU United Kingdom Telephone: + (0) Facsimile: +44 (0) mtech.uk@marconi.com Internet: Holding Company: Marconi p.l.c. Marconi Applied Technologies Inc. 4 Westchester Plaza, PO Box 482, Elmsford, NY USA Telephone: (94) Facsimile: (94) mtech.usa@marconi.com 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805

2 CONNECTOR POSITIONS ON BIAS/BUFFER MODULE OS GND Ref Test Point OS Test Point SS Test Point way D-type to CCD (J5) High Voltage Pulse Generator Module Connector (Rear) Optional Video/Logic Module Connectors 2 V In Power Connector (J6) 20-way IDC for Waveforms (J7) ISH Test Point 6-way IDC for TV Mode Interface (J) SS ISH GD RD ABD 0 V +2 V DC 2 CONNECTOR FUNCTIONS J6 POWER INPUT 2-way.25 mm Molex o GND o 2 +2 V IN J7 5 V WAVEFORMS 20-way IDC CHPUMPP o o 2 CHPUMPN S 4 3 o o 4 S 3 S 2 5 o o 6 S I 4 7 o o 8 I 3 I 2 9 o o 0 I R o o 2 R 3 R 2 3o o 4 R R 2HV 5o o 6 HV AMPLITUDE (0 to 5 V controls CCD gain) GND 7o o 8 GND +2 V IN 9o o V IN 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 2

3 J TV MODE INTERFACE (when Video/Logic board is fitted) J5 CONNECTOR TO LOW LIGHT CCD 25-way D-type socket 6-way IDC AGCCONT o o 2 HV AMPLITUDE (0 to 5V controls CCD gain) GEN2 3 o o 4 GEN BIN2 5 o o 6 BIN PIXSYNC 7 o o 8 LINESYNC FIELDSYNC 9 o o 0 FRAMESYNC VIDEOOUT o o 2 VIDEOGND GND 3o o 4 GND +2 V IN 5o o 6 +2 V IN GEN and GEN2 are not currently used. Binning options are: BIN BIN Binning Mode Selected 2 No Binning normal operation 0 Two Times Pixel Binning same pixel pairing every line 0 Two Times Pixel Binning pixel pairing alternates with odd/even field 0 0 Two Times Pixel Binning pixel pairing alternates with odd/even line number GND VSS OG ABD DD GD R DC R R R 2 R 3 HV GND 25 o 24 o 23 o 22 o 2 o 20 o 9 o 8 o 7 o 6 o 5 o 4 o o 3 o 2 o o 0 o 9 o 8 o 7 o 6 o 5 o 4 o 3 o 2 o VOS VRD V(D)OD I I 2 I 3 I 4 S S 2 S 3 S 4 GND R 2HV(CCD) PL Interconnection For HV Pulse Generator Module 0-way IDC R 2HV(CCD) GND R * GND (Power) N/C o o 2 HV GND (R 2HV Return) 3 o o 4 HV Amplitude Control (0 5 V) 5 o o 6 R 2HV (At Logic Level) 7 o o 8 +2 V (Power) 9 o o 0 N/C * At Logic Level for sampling peak level of high voltage pulse. OUTLINE OF BIAS/BUFFER MODULE (All dimensions in millimetres) 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 3

4 Recommendations for the Charge Pump Waveforms The timing diagram below shows charge pump drive waveforms which ensure the driving transistors are never on simultaneously. CHPUMPN 00 ns approx. CHPUMPP By widening CHPUMPP by about 00 ns or more relative to the edges of CHPUMPN the P channel transistor will have had time to turn off before the N channel transistor starts to turn on. Similarly on the falling edge the N channel transistor will have had time to turn off before the P channel transistor starts to conduct. This method provides increased efficiency of the charge pump, but it will still operate if the same waveform is applied to CHPUMPN and CHPUMPP. 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 4

5 CONNECTOR POSITIONS ON VIDEO/LOGIC MODULE Connectors to Bias/Buffer Module (rear) Video Video Out Connector White Clip 0 V Pedestal Level CONNECTOR FUNCTIONS J Video Signal Output 2-way.25 mm Molex o VIDEOGND o 2 VIDEOOUT OUTLINE OF VIDEO/LOGIC MODULE (All dimensions in millimetres) 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 5

6 CONNECTOR POSITION ON HIGH VOLTAGE PULSE GENERATOR MODULE PL 0-way IDC Connector For Power and I/O Heatsink OUTLINE OF HV MODULE (All dimensions in millimetres) 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 6

7 CONNECTOR POSITION ON RESONANT HV MODULE OUTLINE OF RESONANT MODULE (All dimensions in millimetres) 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 7

8 CONNECTOR FUNCTIONS (For both HV modules) PL Power, Control and HV Pulse Outputs 0-way IDC Pin Function R 2HV out 2 R 2HV gnd The high voltage pulse generator is suitable for use with pixel rates up to 5 MHz. The resonant circuit operates at. MHz (for TV format). Refer to the relevant CCD datasheet for gain law. 3 signal gnd 4 control input (0 to 5 V) 5 sample clock in (TTL) typically R 6 pixel clock in (TTL) - R 2HV 7 power gnd 8 +2 V supply 9 nc 0 nc PULSE TIMING DIAGRAM Pixel Clock In (R φ 2) Pixel Clock Out (R φ 2HV) tcph tcpl Sample Clock In tss+ tss - tsh - tsh+ 90% Pixel Clock Out (R φ 2HV) 0% tcrhv tcfhv Function Symbol Min Typ Max (ns) (ns) (ns) Propagation delay t cph, t cpl Sample clock setup and hold Output rise and fall t ss+ t ss- t sh+ t sh- t crhv t cfhv see notes 2 and 3 see notes 2 and NOTES. Duty cycle is dependent upon frequency. 2. Minimum sample pulse width 50 ns. 3. The Pixel Clock (R 2) may be used as Sample Clock. Marconi Applied Technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. Marconi Applied Technologies accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. 200 Marconi Applied Technologies Limited AA-L3M65 Series Issue, November 200 4/6805 Page 8