BlueCore 6-ROM (QFN) Product Data Sheet

Transcription

1 Features BlueCore 6-ROM (QFN) RF IN RF OUT Fully Qualified Bluetooth v2.1 + EDR system Piconet and Scatternet Support Minimum External Components Low-Power 1.5V Operation, 1.8V to 3.6V I/O Integrated 1.8V and 1.5V Regulators UART to 4Mbaud SDIO (Bluetooth Type A)/CSPI Interface Deep-Sleep SDIO Operation 6 x 6 x 0.9mm QFN Support for Coexistence RoHS Compliant General Description Applications The BlueCore 6-ROM (QFN) is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems including enhanced data rates (EDR) to 3Mbits/s. With the on-chip CSR Bluetooth software stack, it provides a fully compliant Bluetooth system to v2.1 + EDR of the specification for data and voice communications. 2.4GHz Radio Watchdog RAM ROM MMU Processor XTAL I/O Figure 1: System Architecture UART or SDIO/CSPI PIO SPI PCM / I 2 S Cellular handsets Single Chip Bluetooth v2.1 + EDR System Data Sheet for Personal Digital Assistants (PDAs) Automotive Personal Navigation Devices BC63B239A August 2007 BlueCore6-ROM (QFN) has been designed to reduce the number of external components required which ensures production costs are minimised. BlueCore6-ROM (QFN) includes AuriStream, which offers significant power reduction over the CVSD based system when used at both ends of the link. The device incorporates auto-calibration and built-in self-test (BIST) routines to simplify development, type approval and production test. All hardware and device firmware is fully compliant with the Bluetooth v2.1 + EDR specification. To improve the performance of both Bluetooth and b/g co-located systems a wide range of coexistence features are available including a variety of hardware signalling: basic activity signalling and Intel WCS activity and channel signalling. CSR plc 2007 Page 1 of 70

2 Contents Contents 1. Status Information Device Details Device Diagram Package Information Package Information Device Terminal Functions Package Dimensions PCB Design and Assembly Considerations x 6 x 0.9mm 40 Lead QFN Package Bluetooth RF Interface Description Bluetooth Radio Ports RF_N and RF_P Bluetooth Receiver Low Noise Amplifier RSSI Analogue to Digital Converter Bluetooth Transmitter IQ Modulator Power Amplifier Bluetooth Radio Synthesiser Clock Generation Clock Input and Generation Input Frequencies and PS Key Settings External Reference Clock Clock Start-Up Delay Crystal Oscillator (XTAL_IN, XTAL_OUT) Load Capacitance Frequency Trim Transconductance Driver Model Negative Resistance Model Crystal PS Key Settings Microcontroller, Memory and Baseband Logic AuriStream CODEC AuriStream CODEC Requirements AuriStream Hierarchy Memory Management Unit Burst Mode Controller Physical Layer Hardware Engine DSP System RAM ROM Microcontroller TCXO Enable OR Function WLAN Coexistence Interface Configurable I/O Parallel Ports TX-RX Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) Instruction Cycle Writing to the Device Reading from the Device Multi-Slave Operation Host Interfaces Host Selection UART Interface UART Configuration While Reset is Active CSR Serial Peripheral Interface (CSPI) CSPI Read/Write Cycles CSPI Register Write Cycle CSPI Register Read Cycle CSPI Burst Write Cycle CSPI Burst Read Cycle CSR plc 2007 Page 2 of 70

3 Contents 9.4. SDIO Interface SDIO/CSPI Deep-Sleep Control Schemes Retransmission Signalling Audio Interfaces PCM Interface PCM Interface Master/Slave Long Frame Sync Short Frame Sync Multi-slot Operation GCI Interface Slots and Sample Formats Additional Features PCM Timing Information PCM_CLK and PCM_SYNC Generation PCM Configuration Digital Audio Interface (I2S) Power Control and Regulation Power Control and Regulation Sequencing External Voltage Source High-Voltage Linear Regulator Low-Voltage Linear Regulator VREGENABLE RST# Digital Pin States on Reset Example Application Schematic Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Input/Output Terminal Characteristics Linear Regulator, High Voltage Linear Regulator, Low Voltage Digital Clocks Reset RSSI ADC External Reference Clock Power Consumption CSR Software Stacks BlueCore HCI Stack Key Features of the HCI Stack: Standard Bluetooth Functionality Key Features of the HCI Stack: Extra Functionality BCHS Software Additional Software for Other Embedded Applications CSR Development Systems Ordering Information Ordering Information Tape and Reel Information Document References Terms and Definitions Document History CSR plc 2007 Page 3 of 70

4 Contents List of Figures Figure 1 System Architecture... 1 Figure 3.1 Device Diagram... 9 Figure 4.1 BlueCore6-ROM Device Pinout Figure 4.2 Package Dimensions Figure 5.1 Simplified Circuit RF_N and RF_P Figure 6.1 Clock Architecture Figure 6.2 Crystal Driver Circuit Figure 6.3 Crystal Equivalent Circuit Figure 7.1 Baseband Digits Block Diagram Figure 7.2 AuriStream CODEC and the BT Radio Figure 7.3 AuriStream CODEC and the CVSD CODEC Figure 7.4 Example TCXO Enable OR Function Figure 8.1 SPI Write Operation Figure 8.2 SPI Read Operation Figure 9.1 Universal Asynchronous Receiver Figure 9.2 Break Signal Figure 9.3 CSPI Register Write Cycle Figure 9.4 CSPI Register Read Cycle Figure 9.5 CSPI Burst Write Cycle Figure 9.6 CSPI Burst Read Cycle Figure 10.1 as PCM Interface Master Figure 10.2 as PCM Interface Slave Figure 10.3 Long Frame Sync (Shown with 8-bit Companded Sample) Figure 10.4 Short Frame Sync (Shown with 16-bit Sample) Figure 10.5 Multi-slot Operation with Two Slots and 8-bit Companded Samples Figure 10.6 GCI Interface Figure Bit Slot Length and Sample Formats Figure 10.8 PCM Master Timing Long Frame Sync Figure 10.9 PCM Master Timing Short Frame Sync Figure PCM Slave Timing Long Frame Sync Figure PCM Slave Timing Short Frame Sync Figure Digital Audio Interface Modes Figure Digital Audio Interface Slave Timing Figure Digital Audio Interface Master Timing Figure 11.1 Voltage Regulator Configuration Figure 12.1 BlueCore6-ROM (QFN) Example Application Schematic Figure 14.1 BlueCore HCI Stack CSR plc 2007 Page 4 of 70

5 Contents List of Tables Table 6.1 PS Key Values for CDMA/3G Phone TCXO Table 6.2 Crystal Specification Table 7.1 AuriStream Supported Bitrates Table 8.1 Instruction Cycle for an SPI Transaction Table 9.1 SDIO_CLK and SDIO_CMD Transfer Protocols Table 9.2 Possible UART Settings Table 9.3 Standard Baud Rates Table 9.4 SDIO Mapping to CSPI Functions Table 10.1 PCM Master Timing Table 10.2 PCM Slave Timing Table 10.3 PSKEY_PCM_LOW_JITTER_CONFIG Description Table 10.4 PSKEY_PCM_CONFIG32 Description Table 10.5 PSKEY_PCM_SYNC_MULT Description Table 10.6 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface Table 10.7 PSKEY_DIGITAL_AUDIO_CONFIG Table 10.8 Digital Audio Interface Slave Timing Table 10.9 Digital Audio Interface Master Timing Table 11.1 Pin States of on Reset CSR plc 2007 Page 5 of 70

6 Contents List of Equations Equation 6.1 Load Capacitance Equation 6.2 Trim Capacitance Equation 6.3 Frequency Trim Equation 6.4 Pullability Equation 6.5 Transconductance Required for Oscillation Equation 6.6 Equivalent Negative Resistance Equation 9.1 Baud Rate Equation 10.1 PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock Equation 10.2 PCM_SYNC Frequency Relative to PCM_CLK CSR plc 2007 Page 6 of 70

7 Status Information 1 Status Information The status of this Data Sheet is. CSR Product Data Sheets progress according to the following format: Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-Production Information Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All electrical specifications may be changed by CSR without notice. Production Information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions. Life Support Policy and Use in Safety-Critical Applications CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. RoHS Compliance BlueCore6-ROM (QFN) devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). Trademarks, Patents and Licenses Unless otherwise stated, words and logos marked with or are trademarks registered or owned by CSR plc or its affiliates. Bluetooth and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners. I 2 S is a registered trademark of the Philips Corporation. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. CSR plc 2007 Page 7 of 70

8 Device Details 2 Device Details Bluetooth Radio Common TX/RX terminal simplifies external matching; eliminates external antenna switch No external trimming is required in production Bluetooth v2.1 + EDR Specification compliant Bluetooth Transmitter +6dBm RF transmit power with level control from onchip 6-bit DAC over a dynamic range >30dB Bluetooth Receiver Integrated channel filters Digital demodulator for improved sensitivity and cochannel rejection Real time digitised RSSI available on HCI interface Fast AGC for enhanced dynamic range Channel classification for AFH Synthesiser Fully integrated synthesiser requires no external VCO varactor diode, resonator or loop filter Compatible with crystals between 16 and 26MHz or an external clock between 12 and 52MHz Baseband and Software AuriStream (16, 24, 32, 40 kbps) CODEC Internal 48kbyte RAM, allows full speed data transfer, mixed voice and data, and full piconet operation, including all EDR packet types Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping. Supports all Bluetooth v2.1 + EDR features including esco and AFH Transcoders for A-law, µ-law and linear voice from host and A-law, µ-law and CVSD voice over air Physical Interfaces SDIO and CSPI Synchronous serial interface up to 4Mbits/s for system debugging UART interface with programmable data rate up to 4Mbaud Bi-directional serial programmable audio interface supporting PCM and I 2 S formats Auxiliary Features Crystal oscillator with built-in digital trimming Clock request output to control an external clock Device can run in low power modes from an external 32768Hz clock signal Power management includes digital shutdown, and wake up commands with an integrated low power oscillator for ultra low power Park/Sniff/Hold mode Auto Baud Rate setting, subject to host interface in use On-chip linear regulators: 1.8V output from typical V input to power I/O ring (load current 100mA) and second low dropout linear regulator producing 1.5V core voltage from 1.8V Power-on-reset cell detects low supply voltage Arbitrary sequencing of power supplies is permitted Bluetooth Stack CSR's Bluetooth Protocol Stack runs on the on-chip MCU in the configuration: Standard HCI over UART Package Options 40-lead 6 x 6 x 0.9mm, 0.5mm pitch QFN CSR plc 2007 Page 8 of 70

9 RF_N RF_P VDD_CORE LO_REF XTAL_OUT XTAL_IN CLK32K_IN VREGENABLE VREGIN_H VREGOUT_H VREGIN_L VDD_ANA VDD_RADIO BlueCore6-ROM Bluetooth Modem Clock Generation LNA PA IN EN High Voltage Linear Regulator OUT 32kHz Clock SENSE IN EN Low Voltage Linear Regulator IQ Demodulator IQ Modulator -45 I I Q Q +45 RSSI /N/N+1 Tune RF Receiver Demodulator RF Transmitter ADC DAC RF Synthesiser RF Synthesiser Loop Filter Power Control and Regulation Baseband Basic Rate Modem EDR Modem Radio Control RAM Interrupt Controller Timers MUX UART SDIO CSPI Serial Interfaces Memory Management Unit Bluetooth Stack Microcontroller MCU Programmable I/O AIO PIO SPI ROM PCM_CLK PCM_SYNC PCM_OUT PCM_IN RST# TEST_EN Device Diagram 3 Device Diagram PCM/I 2 S Interfaces Audio Interfaces SPI_MOSI SPI_CS# SPI_CLK SPI_MISO SDIO_CMD SDIO_SD_CS# SDIO_CLK SDIO_DATA3 SDIO_DATA2 SDIO_DATA1 SDIO_DATA0 CSPI_MOSI CSPI_CLK CSPI_CS# CSPI_INT CSPI_MISO SDIO_CMD SDIO_SD_CS# SDIO_CLK SDIO_DATA3 SDIO_DATA2 SDIO_DATA1 SDIO_DATA0 UART_CTS UART_RX UART_RTS UART_TX Fref PIO[0] OUT SENSE PIO[1:5,7,9] AIO[0] VDD_PADS VDD_PADS VDD_CORE Figure 3.1: Device Diagram CSR plc 2007 Page 9 of 70

10 Package Information 4 Package Information 4.1 Package Information Figure 4.1: BlueCore6-ROM Device Pinout CSR plc 2007 Page 10 of 70

11 Package Information 4.2 Device Terminal Functions Bluetooth Radio Lead Pad Type RF_N Supply Domain 7 RF RADIO Description Transmitter output/switched receiver input RF_P 6 RF RADIO Complement of RF_N Synthesiser and Oscillator Lead Pad Type Supply Domain Description XTAL_IN 11 Analogue ANA For crystal or external clock input XTAL_OUT 12 Analogue ANA Drive for crystal LO_REF 13 Analogue ANA Reference voltage decoupling CLK_32K SPI Interface SPI_MOSI SPI_CS# SPI_CLK SPI_MISO 27 Lead Input with weak internal pull-down Pad Type Input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Output, tri-state, with weak internal pull-down PADS Supply Domain PADS PADS PADS PADS Dedicated 32kHz external reference clock input Description SPI data input Chip select for Serial Peripheral Interface (SPI), active low SPI clock SPI data output CSR plc 2007 Page 11 of 70

12 Package Information SDIO/CSPI/UART Interfaces (a) Lead Pad Type SDIO_DATA[0] CSPI_MISO UART_TX SDIO_DATA[1] CSPI_INT UART_RTS SDIO_DATA[2] UART_RX SDIO_DATA[3] CSPI_CS# UART_CTS SDIO_CLK CSPI_CLK SDIO_CMD CSPI_MOSI Output, tri-state, with weak internal pull-down Input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Input, with weak internal pull-down SDIO_SD_CS# Input with weak internal 33 pull-down (a) See Section 9 for more information. PCM Interface (a) Lead Pad Type PCM_OUT PCM_IN PCM_SYNC PCM_CLK Output, tri-state, with weak internal pull-down Input, with weak internal pull-down Bi-directional with weak internal pull-down Bi-directional with weak internal pull-down Supply Domain PADS PADS PADS PADS PADS PADS PADS Supply Domain PADS PADS PADS PADS Description Synchronous data input/output CSPI data output UART data output, active high Synchronous data input/output CSPI data input UART request to send, active low Synchronous data input/output UART data input, active high Synchronous data input/output Chip select for CSR Serial Peripheral Interface (CSPI), active low UART clear to send, active low SDIO Clock CSPI Clock SDIO data input CSPI data input SDIO chip select to allow SDIO Accesses Description Synchronous data output Synchronous data input Synchronous data sync Synchronous data clock (a) The Digital Audio Interface (I 2 S) shares the same pins as the PCM interface. For more information about I 2 S, see section 10.2 CSR plc 2007 Page 12 of 70

13 Package Information PIO Port Lead Pad Type PIO[9] PIO[7] PIO[5] PIO[4] PIO[3] PIO[2] PIO[1] Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength internal pull-up/down Supply Domain PADS PADS PADS PADS PADS PADS PADS Description Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line AIO[0] (a) 14 Bi-directional ANA Programmable input/output line (a) There is no PIO[0] pin on BlueCore6-ROM (QFN) but the value can be routed out via AIO[0] Test and Debug RST# TEST_EN Lead 4 5 Pad Type Input with weak internal pull-up Input with strong internal pull-down Supply Domain PADS PADS Description Reset if low. Input debounced so must be low for >5ms to cause a reset For test purposes only (leave unconnected) CSR plc 2007 Page 13 of 70

14 Package Information Power Supplies Control Lead Description VREGENABLE 17 Take high to enable low and high voltage regulators Power Supplies Lead Description VREGIN_L 9 Input to internal low-voltage regulator VREGIN_H 16 Input to internal high-voltage regulator VREGOUT_H 15 High-voltage regulator output VDD_PADS 18, 35 Positive supply for digital input/output ports including PIO [1:5, 7, 9] VDD_CORE 26 Positive supply for internal digital circuitry VDD_RADIO 8 Positive supply for RF circuitry VDD_ANA 10 VSS Exposed pad Positive supply for analogue circuitry, AIO[0]. Output from internal 1.5V regulator Ground connections CSR plc 2007 Page 14 of 70

15 Package Information 4.3 Package Dimensions Figure 4.2: BlueCore6-ROM (QFN) Package Dimensions CSR plc 2007 Page 15 of 70

16 Package Information 4.4 PCB Design and Assembly Considerations x 6 x 0.9mm 40 Lead QFN Package The following list details the recommendations to achieve maximum board-level reliability of the 6 x 6 x 0.9mm 40 Lead QFN Package. Non-solder mask defined (NSMD) lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation. PCB land width should be 0.3mm and PCB land length should be 0.8mm to achieve maximum reliability Solder paste must be used during the assembly process. CSR plc 2007 Page 16 of 70

17 Bluetooth RF Interface Description 5 Bluetooth RF Interface Description 5.1 Bluetooth Radio Ports RF_N and RF_P RF_N and RF_P form a complementary balanced pair. On transmit their outputs are combined using a balun into the single-ended output required for the antenna. Similarly, on receive their input signals are combined internally. Both terminals present similar complex impedances that require matching networks between them and the balun. Starting from the substrate (chip side), the outputs can each be modelled as an ideal current source in parallel with a lossy resistance and a capacitor. The package parasitics can be represented as an equivalent series inductance. The DC level must be set at VDD_RADIO. Figure 5.1: Simplified Circuit RF_N and RF_P CSR plc 2007 Page 17 of 70

18 Bluetooth RF Interface Description 5.2 Bluetooth Receiver The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the receiver to be used in close proximity to Global System for Mobile Communications(GSM) and Wideband Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift Keying(FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore6-ROM (QFN) to exceed the Bluetooth requirements for co-channel and adjacent channel rejection. For EDR, the Demodulator contains an ADC which is used to digitise the IF received signal. This information is then passed to the EDR modem. See Section Low Noise Amplifier The LNA operates in differential mode and takes its input from the shared RF port RSSI Analogue to Digital Converter The Analogue to Digital Converter (ADC) implements fast Automatic Gain Control (AGC). The ADC samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference limited environments. 5.3 Bluetooth Transmitter IQ Modulator The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping Power Amplifier The internal Power Amplifier (PA) has a maximum output power of +6dBm. This allows BlueCore6-ROM (QFN) to be used in Class 2 and Class 3 Bluetooth radios without an external RF PA. Support for transmit power control allows a simple implementation for Class 1 with an external RF PA. 5.4 Bluetooth Radio Synthesiser The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator(VCO) screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v2.1 + EDR specification. CSR plc 2007 Page 18 of 70

19 Clock Generation 6 Clock Generation 6.1 Clock Input and Generation BlueCore6-ROM (QFN) requires a Bluetooth reference crystal clock frequency of between 12MHz and 52MHz from either an externally connected crystal, or from an external TCXO source. All BlueCore6-ROM (QFN) internal digital clocks are generated using a phase locked loop, which is locked to the frequency of either the external 12MHz to 52MHz reference clock source, or an external reference clock frequency of kHz, or an internally generated reference clock frequency of 1kHz. Figure 6.1: Clock Architecture The auxiliary PLL may use either clock source. The clock to the digital logic is the same in both cases. The use of the watchdog clock is determined with respect to Bluetooth operation in low power modes Input Frequencies and PS Key Settings BlueCore6-ROM (QFN) should be configured to operate with the chosen reference frequency. This is accomplished by setting PSKEY_ANA_FREQ (0x01FE) for all frequencies with an integer multiple of 250kHz. The input frequency default setting in BlueCore6-ROM (QFN) is 26MHz depending on the software build. For full details, see the software release note for the specific build at The following CDMA/3G phone TCXO frequencies are also catered for: 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz. The value of the PS Key is a multiple of 1kHz. Hence 38.4MHz is selected by using a PS Key value of Reference Crystal Frequency (MHz) PSKEY_ANA_FREQ (0x1FE) (Units of 1kHz) n x 250kHz Default Table 6.1: PS Key Values for CDMA/3G Phone TCXO CSR plc 2007 Page 19 of 70

20 Clock Generation 6.2 External Reference Clock A 32kHz clock can be applied to either AIO[0] or CLK32K_IN. If the external clock is applied to the analogue pad AIO[0], the digital signal should be driven with a maximum 1.5V. The CLK32K_IN pad is in the VDD_PADS domain with all the other digital I/O pads and is driven in the range 1.7V to 3.6V Clock Start-Up Delay BlueCore6-ROM (QFN) hardware incorporates an automatic 5ms delay after the assertion of the system clock request signal before running firmware. This is suitable for most applications using an external clock source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under these conditions, BlueCore6-ROM (QFN) firmware provides a software function that extends the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from 1-31ms. Zero is the default entry for 5ms delay. This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still keeping the current consumption of BlueCore6-ROM (QFN) as low as possible. BlueCore6-ROM (QFN) consumes about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware. 6.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) BlueCore6-ROM (QFN) contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator. The external crystal is connected to pins XTAL_IN and XTAL_OUT. Figure 6.2: Crystal Driver Circuit Figure 6.3 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors. Cm Lm Rm Co Figure 6.3: Crystal Equivalent Circuit The resonant frequency may be trimmed with the crystal load capacitance. BlueCore6-ROM (QFN) contains variable internal capacitors to provide a fine trim. CSR plc 2007 Page 20 of 70

21 Clock Generation Min Typ Max Frequency 16MHz 26MHz 26MHz Initial Tolerance - ±25ppm - Pullability - ±20ppm/pF - Transconductance 2.0mS - - Table 6.2: Crystal Specification The BlueCore6-ROM (QFN) driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance Load Capacitance For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore6-ROM (QFN) provides some of this load with the capacitors C trim and C int. The remainder should be from the external capacitors labelled C t1 and C t2. C t1 should be three times the value of C t2 for best noise performance. This maximises the signal swing, hence, slew rate at XTAL_IN (to which all on-chip clocks are referred). Crystal load capacitance, C l is calculated with Equation 6.1. Where: Note: C trim = 3.4pF nominal (mid-range setting) C int = 1.5pF Equation 6.1: Load Capacitance C int does not include the crystal internal self capacitance; it is the driver self capacitance Frequency Trim BlueCore6-ROM (QFN) enables frequency adjustments to be made. This feature is typically used to remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load capacitance with on-chip trim capacitors, C trim. The value of C trim is set by a 6-bit word in the PSKEY_ANA_FTRIM (0x1f6). Its value is calculated as follows: C trim = 110fF PSKEY_ AN A _ FT R IM Equation 6.2: Trim Capacitance The C trim capacitor is connected between XTAL_IN and ground. When viewed from the crystal terminals, the combination of the tank capacitors and the trim capacitor presents a load across the terminals of the crystal which varies in steps of typically 110fF for each least significant bit increment of PSKEY_ANA_FTRIM. The frequency trim is described by Equation 6.3. Equation 6.3: Frequency Trim Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pf. Total trim range is 0 to 63. If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 6.4. CSR plc 2007 Page 21 of 70

22 Clock Generation Equation 6.4: Pullability Where: C 0 = Crystal self capacitance (shunt capacitance) C m = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 6.3. Note: It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with ageing and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is required Transconductance Driver Model The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one terminal generates a voltage at the other. The transconductance amplifier in BlueCore6-ROM (QFN) uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product should be greater than three. The transconductance required for oscillation is defined by the relationship shown in Equation 6.5. Equation 6.5: Transconductance Required for Oscillation BlueCore6-ROM (QFN) guarantees a transconductance value of at least 2mA/V at maximum drive level. Notes: More drive strength is required for higher frequency crystals, higher loss crystals (larger R m ) or higher capacitance loading. Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level required is determined by the crystal driver transconductance Negative Resistance Model An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the BlueCore6- ROM (QFN) crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance may be calculated for it with the following formula in Equation 6.6: Equation 6.6: Equivalent Negative Resistance This formula shows the negative resistance of the BlueCore6-ROM (QFN) driver as a function of its drive strength. The value of the driver negative resistance may be easily measured by placing an additional resistance in series with the crystal. The maximum value of this resistor (where oscillation occurs) is the equivalent negative resistance of the oscillator. The BlueCore6-ROM (QFN) firmware automatically servos the drive level on the crystal circuit to achieve optimum input swing. The PSKEY_XTAL_TARGET_AMPLITUDE(0x24B ) is used by the firmware to servo the required amplitude of crystal oscillation. Refer to the software build release note for a detailed description Crystal PS Key Settings See Table 6.1. CSR plc 2007 Page 22 of 70

23 Microcontroller, Memory and Baseband Logic 7 Microcontroller, Memory and Baseband Logic 4Mbits ROM External Memory IF RAM Bluetooth Modem Interrupt Timer 7.1 AuriStream CODEC MMU MCU Figure 7.1: Baseband Digits Block Diagram UART or SDIO/CSPI The AuriStream CODEC works on the principle of transmitting the delta between the actual value of the signal and a prediction rather than the signal itself. Hence, the information transmitted is reduced along with the power requirement. The quality of the output depends on the number of bits used to represent the sample. The inclusion of AuriStream results in reduced power consumption compared to a CVSD implementation when used at both ends of the system AuriStream CODEC Requirements AuriStream supports the following modes of operation: G726 G722 fs Bit Rate (kbps) khz ( ) 10 khz ( ) ( ) ( ) ( ) 8 khz ( ) ( ) ( ) 16 khz ( ) PIO SPI Table 7.1: AuriStream Supported Bitrates Table Key: = Standard Mode ( ) = Optional Mode CSR plc 2007 Page 23 of 70

24 Microcontroller, Memory and Baseband Logic Where possible, AuriStream shares hardware between the encoder and decoder as well as the G726 and G722 implementations of the standard. The 40kbs and 20kbs modes of the G722 codec are specific to CSR. The AuriStream module will be required to support the 3Mbps stream transmitted by the BT radio. The worst-case scenario arises when the AuriStream block is configured as 16kbps at 8 khz, which equates to 2 bits per sample, giving a worst-case symbol rate at the input to the AuriStream block of 1.5Msps to sustain the transmitted bit stream. Voice Buffer (RAM) 1.5Msp AuriStream CODEC 3Mbps BT Radio AuriStream Hierarchy Figure 7.2: AuriStream CODEC and the BT Radio The AuriStream CODEC is positioned in parallel with the CVSD CODEC as shown in Figure 7.3 TX_RX_VOICE TX_RX_VOICE_CVSD TX_RX_VOICE_AURISTREAM VOICE_HOST_IN [15:0] VOICE_RADIO_IN [7:0] TX_RX_VOICE_MAIN Figure 7.3: AuriStream CODEC and the CVSD CODEC VOICE_HOST_OUT [15:0] VOICE_RADIO_OUT [7:0] The AuriStream CODEC is controlled by the TX_RX_VOICEmain block and the processor. Raw data from the host is read from the MMU by the transmit block. This data is fed via the TX_RX_VOICE_MAIN module to the required CODEC, the encoded data is then fed back to the transmit block for broadcast over the Bluetooth interface. During reception, the data is sourced from the radio and applied to the required CODEC. The decoded data is then stored back to RAM by the bluetooth receiver. CSR plc 2007 Page 24 of 70

25 Microcontroller, Memory and Baseband Logic 7.2 Memory Management Unit The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data that is in transit between the host and the air. The dynamic allocation of memory ensures efficient use of the available Random Access Memory(RAM) and is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers. 7.3 Burst Mode Controller During transmission the Burst Mode Controller(BMC) constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception. 7.4 Physical Layer Hardware Engine DSP Dedicated logic is used to perform the following: Forward error correction Header error control Cyclic redundancy check Encryption Data whitening Access code correlation Audio transcoding The following voice data translations and operations are performed by firmware: A-law/µ-law/linear voice data (from host) A-law/µ-law/Continuously Variable Slope Delta (CVSD) (over the air) Voice interpolation for lost packets Rate mismatches The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR including AFH and esco. 7.5 System RAM 48KB of on-chip RAM is provided to support the RISC MCU and is shared between the ring buffers used to hold voice/data for each active connection and the general purpose memory required by the Bluetooth stack. 7.6 ROM 4Mbits of metal programmable ROM is provided for system firmware implementation. 7.7 Microcontroller The microcontroller (MCU), interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host interfaces. A 16-bit reduced instruction set computer (RISC) microcontroller is used for low power consumption and efficient use of memory. 7.8 TCXO Enable OR Function An OR function exists for clock enable signals from a host controller and BlueCore6-ROM (QFN) where either device can turn on the clock without having to wake up the other device. PIO[3] can be used as the host clock enable input and PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore6-ROM (QFN). Note: To turn on the clock, the clock enable signal on PIO[3] must be high. CSR plc 2007 Page 25 of 70

26 Microcontroller, Memory and Baseband Logic Figure 7.4: Example TCXO Enable OR Function On reset and up to the time the PIO has been configured, PIO[2] is tri-state. Therefore, the developer must ensure that the circuitry connected to this pin is pulled via a resistor (470kΩ) to the appropriate power rail. This ensures that the TCXO is oscillating at start up. 7.9 WLAN Coexistence Interface Dedicated hardware is provided to implement a variety of coexistence schemes. Channel skipping AFH, priority signalling, channel signalling and host passing of channel instructions are all supported. The features are configured in firmware. For more information see CSR Bluetooth Coexistence Implementations Configurable I/O Parallel Ports 7 lines of programmable bi-directional input/outputs (I/O) are provided. PIO[1: 5, 7, 9] are powered from VDD_PADS. AIO[0] is powered from VDD_ANA. PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are configured as inputs with weak pull-downs at reset. Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[2] can be configured as a request line for an external clock source. Using PSKEY_CLOCK_REQUEST_ENABLE( 0x246), this terminal can be configured to be low when BlueCore6-ROM (QFN) is in Deep-Sleep and high when a clock is required. See also section 7.8 CSR cannot guarantee that the PIO assignments remain as described. Refer to the relevant software release note for the implementation of these PIO lines, as they are firmware build-specific TX-RX PIO[0] and PIO[1] are usually dedicated to RXEN and TXEN respectively, but they are also available for general use. Note: There is no PIO[0] pin on BlueCore6-ROM (QFN) but the value can be routed out through AIO[0]. CSR plc 2007 Page 26 of 70

27 Serial Peripheral Interface (SPI) 8 Serial Peripheral Interface (SPI) 8.1 BlueCore6-ROM (QFN) Serial Peripheral Interface (SPI) SPI is used for debug primarily. This section details the considerations required when interfacing to BlueCore6-ROM (QFN) via the SPI. Data may be written or read one word at a time or the auto increment feature may be used to access blocks Instruction Cycle The BlueCore6-ROM (QFN) is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 8.1 shows the instruction cycle for an SPI transaction. 1 Reset the SPI interface Hold SPI_CS# high for two SPI_CLK cycles 2 Write the command word Take SPI_CS# low and clock in the 8 bit command 3 Write the address Clock in the 16-bit address word 4 Write or read data words Clock in or out 16-bit data word(s) 5 Termination Take SPI_CS# high Table 8.1: Instruction Cycle for an SPI Transaction With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into the BlueCore6-ROM (QFN) on the rising edge of the clock line SPI_CLK. When reading, BlueCore6-ROM (QFN) replies to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CS# high. Sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore6-ROM (QFN) offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read. CSR plc 2007 Page 27 of 70

28 Serial Peripheral Interface (SPI) Writing to the Device To write to BlueCore6-ROM (QFN), the 8-bit write command ( ) is sent first (C[7:0]) followed by a 16-bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to consecutive locations until the transaction terminates when SPI_CS# is taken high Reading from the Device Figure 8.1: SPI Write Operation Reading from BlueCore6-ROM (QFN) is similar to writing to it. An 8-bit read command ( ) is sent first (C [7:0]), followed by the address of the location to be read (A[15:0]). BlueCore6-ROM (QFN) then outputs on SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0]. The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves, whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the slave device not responding. If SPI_CS# is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks, until the transaction terminates when SPI_CS# is taken high Multi-Slave Operation Figure 8.2: SPI Read Operation BlueCore6-ROM (QFN) should not be connected in a multi-slave arrangement by simple parallel connection of slave MISO lines. When BlueCore6-ROM (QFN) is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, BlueCore6-ROM (QFN) outputs 0 if the processor is running or 1 if it is stopped. CSR plc 2007 Page 28 of 70

29 Host Interfaces 9 Host Interfaces 9.1 Host Selection The MCU selects the UART/SDIO interfaces by reading PIO[4] at boot-time. When PIO[4] is high, the SDIO interface is enabled; when PIO[4] is low, the UART is enabled. If in UART mode, the MCU selects the UART transfer protocol automatically using the unused SDIO pins shown in Table 9.1 SDIO_CLK SDIO_CMD Protocol 9.2 UART Interface 0 0 bcsp 0 1 h4 1 0 h4ds 1 1 h5 Table 9.1: SDIO_CLK and SDIO_CMD Transfer Protocols This is a standard UART interface for communicating with other serial devices. BlueCore6-ROM (QFN) UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. (1) BlueCore UART_TX UART_RX UART_RTS UART_CTS Figure 9.1: Universal Asynchronous Receiver Four signals implement the UART function, as shown in Figure 9.1. When BlueCore6-ROM (QFN) is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. UART configuration parameters, such as baud rate and packet format, are set using BlueCore6-ROM (QFN) firmware. Note: An accelerated serial port adapter card is required to communicate with the UART at maximum baud rate using a standard PC. (1) Uses RS232 protocol, but voltage levels are 0V to VDD_PADS (requires external RS232 transceiver chip). CSR plc 2007 Page 29 of 70

30 Host Interfaces Parameter Baud Rate Flow Control Parity Minimum Maximum Possible Values 1200 baud ( 2%Error) 9600 baud ( 1%Error) 4Mbaud ( 1%Error) RTS/CTS or None None, Odd or Even Number of Stop Bits 1 or 2 Bits per Byte 8 Note: Table 9.2: Possible UART Settings Baud rate is the measure of symbol rate, i.e., the number of distinct symbol changes (signalling events) made to the transmission medium per second in a digitally modulated signal. See also Section 17 The UART interface is capable of resetting BlueCore6-ROM (QFN) on reception of a break signal. A break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Table 9.2. If t BRK is longer than the value, defined by the PSKEY_HOSTIO_UART_RESET_TIMEOUT, (0x1a4), a reset occurs. This feature allows a host to initialise the system to a known state. Also, BlueCore6-ROM (QFN) can emit a break character that may be used to wake the host. Figure 9.2: Break Signal Table 9.3 shows a list of commonly used baud rates and their associated values for the PSKEY_UART_BAUDRATE (0x1be). There is no requirement to use these standard values. Any baud rate within the supported range can be set in the PS Key according to the formula in Equation 9.1. CSR plc 2007 Page 30 of 70

31 Host Interfaces PSKEY _ UART _ BAUDRATE Baud Rate = Equation 9.1: Baud Rate Baud Rate Hex Persistent Store Value Dec Error x % x000a % x % x % x004f % x009d % x00ec % x013b % x01d % x03b % x075f % x0ebf % x161e % x1d7e % x2c3d % Table 9.3: Standard Baud Rates UART Configuration While Reset is Active The UART interface for BlueCore6-ROM (QFN) is tri-state while the chip is being held in reset. This allows the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tri-state when BlueCore6-ROM (QFN) reset is de-asserted and the firmware begins to run. CSR plc 2007 Page 31 of 70

32 Host Interfaces 9.3 CSR Serial Peripheral Interface (CSPI) The CSPI is a host interface which shares pins with the SDIO. It has been defined by CSR with the intention of producing a very simple interface. This has two advantages: It allows maximum compatibility with the possible host drivers It minimises the host software effort needed to form that data to be sent (e.g., by removing the need to calculate CRCs) This host interface allows an external host to control the Bluecore, using a CSR defined protocol built upon a 4-wire SPI bus. Note: The CSPI is entirely separate from the debug Serial Peripheral Interface described in Section 8. The CSPI allows access to the following: Function 0 registers Bluetooth Acceleration Registers MCU IO Registers Bluetooth MMU port The CSPI is a third protocol available for the host to transfer data into the Bluecore and shares pins with the other SDIO protocols. MMU buffers are accessed using burst read/writes. The command and address fields are used to select the correct buffer. The CSPI is able to generate an interrupt to the host when a memory access fails. This interrupt line is shared with the SDIO functions. Table 9.4 shows the mapping of SDIO pins onto the CSPI functions when CSPI is enabled. Pin CSPI Function Direction Description SDIO_DATA3 CSB I Chip Select SDIO_CMD MOSI I Master Out Slave In SDIO_DATA0 MISO O Master In Slave Out SDIO_CLK CLK I Clock SDIO_DATA1 INT O Interrupt Table 9.4: SDIO Mapping to CSPI Functions The CSPI Interface is an extension of the basic SPI Interface, with the access type determined by the following fields: 8-bit command (to initiate CSPI read/write access) 24-bit address 16-bit burst length (optional). Only applicable for burst transfers into or out of the MMU CSPI Read/Write Cycles Register read/write cycles are used to access Function 0, Bluetooth acceleration and MCU registers. Burst read/write cycles are used to access the MMU CSPI Register Write Cycle The command and address are locked into the slave, followed by 16bits of write data. An Error Byte is returned on the MISO signal indicating whether or not the transfer has been successful. CSR plc 2007 Page 32 of 70

33 Host Interfaces CSPI Register Read Cycle Figure 9.3: CSPI Register Write Cycle The command and address field are clocked into the slave, the slave then returns the following: Bytes of Padding data (MISO held low) Error Byte 16-bits of read data CSPI Burst Write Cycle Figure 9.4: CSPI Register Read Cycle Burst transfers are used to access the MMU buffers. They cannot be used to access registers. Burst read/write cycles are selected by setting the nregister/burst bit in the command field to 1. Burst transfers are byte orientated, have a minimum length of 0 bytes and a maximum length of 64kbytes. Setting the length field to 0 results in no data being transferred to or from the MMU. As with a register access, the command and address fields are transferred first. There is an optional length field transferred after the address. The use of the length field is controlled by the LengthFieldPresent bit in the Function 0 registers, which is cleared on reset CSPI Burst Read Cycle Figure 9.5: CSPI Burst Write Cycle Burst reads have a programmable amount of padding data that is returned by the slave bytes are returned as defined in the BurstPadding register. Following this the Error byte is returned followed by the data. Once the transfer has started, no further padding is needed. A FIFO within SDIO_TOP will pre-fetch the data. The address is not retransmitted, and is auto-updated within the slave. The length field is transmitted if LengthFieldPresentin the Function 0 registers is set. In the absence of a length field the CSB signal is used to indicate the end of the burst. Figure 9.6: CSPI Burst Read Cycle CSR plc 2007 Page 33 of 70