Solder Bumping Via Paste Reflow For Area Array Packages

Transcription

1 Solder Bumping Via Paste Reflow For Area Array Packages By Dr. Benlih Huang, and Dr. Ning-Cheng Lee Indium Corporation of America Utica, NY Tel: (315) ; Fax: (315) ; and ABSTRACT Several unique solder paste systems have been developed and tested for 63Sn/37Pb solder bumping for wafer, CSP, and BGA with the low cost print-detach-reflow process. The results indicate that the bump height achieved is very adequate and consistent for all three area array package systems. Microstructure of solder bumps appears normal. The yield is also very high for both before reflow and after reflow condition, and is dictated by printing performance. With the unique high slump resistance exhibited by those newly developed pastes, the paste transfer efficiency at printing stage becomes the most critical performance for this process. The transfer efficiency increases with increasing area ratio, increasing taper angle, decreasing pitch, decreasing stencil thickness, decreasing challenge, with adoption of square aperture design, and is not sensitive to aspect ratio of aperture to solder particle size. The paste systems appear to have more potential for depositing a larger amount of paste per unit pitch, as evidenced by the linear relation between expected paste volume and the deposited paste volume. Increasing metal content helps improving bumping performance. The bottleneck of increasing bumping performance for wafer applications appears to be developing a stencil manufacturing technology capable of providing an aperture pattern with spacing considerably smaller than the stencil thickness. Slow print speed is also essential for adequate printing. A non-shiny non-smooth stencil surface is considered beneficial for aiding paste rolling. The flux residue of those pastes is cleanable with solvents. Key Words: solder, bumping, solder paste, area array package, BGA, CSP, wafer, reflow, high speed, high throughput, low cost INTRODUCTION With the electronic industry advancing rapidly toward smaller, lighter, faster, and cheaper products, area array packages including BGAs, CSPs, and flip chips quickly becomes the focus of IC packaging technology, mainly due to the robustness in handling and considerable reduction in size. Up to this moment, the solder bumps of those packages are manufactured primarily via solder sphere attachment for BGAs, and via evaporation or electroplating processes for wafer bumping. Unfortunately, the sphere attachment process suffers a low throughput and high material cost disadvantages, particularly for mounting small spheres onto CSPs. On the other hand, both evaporation and electroplating process suffers high process cost as well as low throughput disadvantages. Solder paste printing and reflow process is a well established robust and cheap process. Obviously, the throughput and the cost of solder bumping could be at least order of magnitude more favorable if a conventional surface mount solder paste printing and reflow process can be employed. Works in this paste bumping process has been rare [1-8], and the focus is on wafer bumping only. In this study, the cost of paste bumping process is compared with other processes. In addition, solder bumping for BGA, CSP, and wafer via solder paste print/reflow process with high quality and high yield is demonstrated, and the requirements on solder paste materials and printing parameters are discussed. COST ANALYSIS Solder bumping can also be accomplished with the use of solder paste alone. This approach becomes more and more attractive when the area array packaging gets further miniaturized, therefore the solder bumps become smaller and smaller. This is mainly due to both cost and throughput consideration. With the use of the sphere transfer approach, since the cost of the sphere remains the same regardless of sphere size, the cost per bump is accordingly steady as well, regardless of bump size. Conversely, the cost of solder paste is determined by its volume. Therefore, with decreasing bump size, the cost per solder bump will reduce significantly when employing the solder paste bumping approach. Fig. 1 shows the comparison of solder materials cost for processes using sphere placement versus paste bumping. At bump size below 3 mils (.75 mm) diameter, the paste bumping cost becomes more and more favorable with a further decrease in bump size. In the case of wafer bumping, with the use of solder evaporation or plating process, the cost per bump is even higher. The cost of electroplating process is about $5-2/wafer. Assuming the cost is $125/wafer, and a wafer size of 8 inches diameter, patterned with full area array dies each loaded with 1 mil pitch bumps, the cost of electroplating solder bumping is about $.43/1 bumps. A similar analysis conducted by Bogdanski [9] shows the cost ranges from $.6-

2 sphere cost/k bump paste cost/k bump $ Solder Mat'l/K Bumps Sphere Diameter Fig. 1 Comparison of solder materials cost using solder paste versus sphere placement for producing 1 solder bumps. Solder paste bumping process becomes favorable at bump size below 3 mil diameter. 1.6/1 bumps, depending on the pad count per chip. The base cost for bumping he used was $1/wafer. For solder paste bumping process, the cost of solder paste for 1 mil pitch bumps will be less than $.1/1 bumps. Since solder paste print and reflow is generally a low cost process, the overall cost of using solder paste for wafer bumping will be two to three orders of magnitude lower than electroplating process. Throughput is another major consideration. The sphere placement process is a sequential process, and is typically limited to one chip, or at most few chips, per placement. Electroplating process involves multiple time consuming steps, as depicted in Fig. 2, therefore is even lower in throughput. On the other hand, the solder paste bumping process is a very high throughput process. With one stroke of printing, it is possible to deposit solder pastes onto hundreds of BGA or CSP packages or multiple wafers. Although the exact throughput of paste bumping depending on the detailed approaches chosen, the overall throughput is considered much higher than all other processes. MAJOR HURDLES Fig. 3 Massive bridging caused by slumping and the resultant solder robbing during 63Sn/37Pb paste bumping process. The procedure used is print-detach stencil-reflow. As discussed above, solder paste printing is considered a viable low cost bumping process [1-8]. The most desirable procedure is similar to the conventional surface mount process: print, detach the stencil, then reflow. It offers the greatest potential to cut the bumping cost markedly. However, in order to deliver sufficient solder volume to form an adequate bump height, the stencil aperture must be much larger than the pad dimension, since solder volume is only about 5-6% of solder paste. This will be fine for peripheral pad design or staggered pad patterning. In both cases, an overprint can be tolerated without causing problems. However, for full area array designs, the slumping of the overprinted solder paste will result in solder robbing at reflow, and consequently uneven solder bump size. Fig. 3 shows example of massive bridging due to slump and solder robbing when using print-detach-reflow process. The appropriate solder volume can also be achieved using a thick stencil instead of a large aperture. The potential problem here is typically poor paste release from the stencil aperture. Therefore, an easily releaseable solder paste is crucial for area-array BGA processes if a regular print-release process is desired for bumping with solder paste alone. In addition, the paste has to have a minimal slump performance in order to Fig. 2 Electroplated wafer bumping process flow [1].

3 avoid solder robbing. Lack of adequate solder paste materials able to meet both requirements has prevented this process from being adopted by industry up to now. In this study, a series of newly developed solder paste materials is used for the paste bumping work. EXPERIMENT 1. Solder Paste Materials Three 63Sn/37Pb solder pastes were used in this study, as listed in Table 1. All three pastes use resin based flux chemistry, and are either no-clean or solvent cleanable. Table 1. 63Sn/37Pb solder pastes used for paste bumping study. Paste Applications Mesh Solder Volume Flux Chemistry Fraction A Wafer bumping -635 (< 2 µ).49 Solvent cleanable B C CSP bumping BGA bumping -325/+5 (25-45 µ) -325/+5 (25-45 µ).52 No clean or solvent cleanable.62 No clean or solvent cleanable 2. Stencil, Board, and Process Parameters The design of stencil aperture patterns covers variation in aperture shape, aperture width, and stencil thickness for a given pitch dimension. In general, the design puts more emphasis on placing maximum amount of solder paste onto the board. Thus, if the paste performs well under those conditions, any need for a less paste volume can be easily entertained by using a thinner stencil with the same pattern. The design also emphasizes on a simple, symmetrical pattern design. This type of symmetrical design demands a very high performance from solder paste materials. If a solder paste can perform well under this condition, it will allow an easy adoption by the industry without concern on how to achieve a complicated nonsymmetrical staggered stencil pattern design, which can still be used to further enhance the performance if needed. Wafer Bumping (a) Stencil/Substrate: There were three types of patterns on the same stencil that have been employed for the wafer bumping test: 1 mil pitch with 7 mil square opening (board side), 8 mil pitch with 5.5 mil square opening (board side), and 7 mil pitch with 5 mil square opening (board side). Because the electroformed stencil openings were trapezoidal, the openings on the squeegee side were 5.5 mil, 3.5 mil, and 3.3 mil, respectively, correspondent to 7 mil, 5.5 mil, and 5 mil openings on the board side (see Table 2). In addition, stencil step-down strategy was employed with thickness as follows: 3 mil, 2.5 mil, and 2 mil for the 1 mil, 8 mil, and 7 mil pitch patterns, respectively. Each pattern had four 4 x 4 area array units, thus had altogether 96 openings for each pattern. The FR-4 testing board was designed to have corresponding round pads with 2.4 mil in diameter using a.5 ounce bare copper surface finish. No solder mask was employed on the FR-4 board. (b) Printing: A DEK 265 GS(X) printer was employed with 3.5 kg pressure per 1 mm polyurethane squeegee length and 1 mm/sec print speed. The stencil separation speed was 1 mm/sec. The print gap was. (c) Reflow: The reflow was conducted in an inline RTC IR oven with nitrogen atmosphere (oxygen at 2 ppm). Two boards were processed. CSP Bumping (a) Stencil and Board: Four electroformed stencils have been used for the chip scale package (CSP) bumping test. They were 6 mil, 8 mil, 9 mil, and 1 mil thick stencils. In each stencil there were 6 units of 4 x 4 area array patterns with three units being square and three units being round openings. For the 6 mil thick stencil the pitch was 25 mil, and for the 8, 9, and 1 mil thick stencils the pitch was 2 mil. Detailed stencil aperture features for each pattern can be found in Table 2. The half ounce bare Cu pads of the FR-4 boards were 8 mil in diameter. No solder mask was used for board. 5 boards were processed, providing 8, solder bumps for each pattern design. (b) Printing: A DEK 265GS(X) is employed with a pressure of 2 kg/1 mm. The print speed is 35 mm/sec, and the stencil separation is.2 mm/sec. The print gap is. (c) The reflow was conducted in an inline RTC IR oven with nitrogen atmosphere (oxygen at 2 ppm). In addition, for comparison purpose, some additional reflow was also conducted in a BTU forced air convection oven with nitrogen reflow atmosphere. The oxygen level was at 2 ppm as well. Unless otherwise specified, all of the samples discussed were reflowed with IR oven. BGA Bumping (a) Stencil and Board: One 16 mil thick electroformed stencil was used, with 6 units of 2 x 2 arrays of openings, three units being square and three units being round. All six units differ in opening dimension. The detailed aperture dimension information can be found in Table 2. The pitch of stencil and the FR-4 board was 5 mil. The round, non-solder mask defined bare copper pads were 2 mil in diameter. 5 boards were processed, providing 2 bumps for each pattern design.

4 Table 2 Dimension of stencil and boards and bump height and transfer efficiency of solder paste bumping results. Pitch Opening on squeegee side, a Stencil thickness, h Bump height, H Pad diameter Opening on board side, b Aperture wall area, A W (mil sq.) Aperture open area on board side, A B (mil sq.) Area Ratio (open area on board side/aperture wall area), R A Aperture volume, V A (cubic mil) Bump height standard deviation Bump volume, V B (cubic mil) Transfer efficiency, E T Square Opening ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± Round Opening ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± (b) A MPM SPM printer was employed for the BGA bumping with 3.3 kg pressure per 1 mm squeegee length and 12.7 mm/sec print speed. The stencil separation speed was 2.54 mm/sec and the print gap was.51 mm. (c) The reflow was performed in a RTC IR oven under nitrogen atmosphere (oxygen concentration at 2 ppm). 3. Properties Investigated The following properties are considered important therefore investigated for paste bumping process. Their definitions are described below. Aperture Area on Board Side, A B The open area of aperture on board side. For square aperture, A B = b 2 For round aperture, A B = π(b/2) 2 Where b: width or diameter of the board side opening

5 Aperture Volume, V A The volume of the aperture space. Volume of the square aperture V A = h [(a + b) x 2 a x b] /3 Volume of round aperture V A = π h [( a + b ) x 2 a x b ]/12 Where h, a and b are defined as above. Aperture Wall Area, A W The side wall area of an aperture. Area of side wall for square aperture A W = (h 2 + ((a b )/2) 2 ) (1/2) x ((a + b)/2) x 4 where a: width of the squeegee side opening b: width of the board side opening h: thickness of the stencil. Area of side wall for round aperture A W = π (h 2 + ((a b )/2) 2 ) (1/2) x (a + b)/2 where a: diameter of the squeegee side opening b: diameter of the board side opening h: thickness of the stencil. The solder paste volume desired (aperture volume V A ) per unit volume space available on board for deposition. A higher value represents a greater challenge in deposition. C h = V A / (pitch) 3 Normalized Bumping Performance, P NB The solder volume V B deposited per unit volume space available on board for deposition. A higher value represents a greater bumping performance. P NB = V B / (pitch) 3 Taper Angle Taper angle θ represents the tapering angle (in degree) of aperture, as shown below. A higher value means a greater extent of tapering. θ = 2 x tan -1 [(b a)/2h] x 18/π Where a = width of aperture on squeegee side b = width of aperture on board side h = stencil thickness Area Ratio, R A Area Ratio is the aperture area on board side divided by the aperture wall area. R A = A B / A W Aspect Ratio, R AS The ratio of the smallest aperture width to the largest solder particle size. R AS = The smallest aperture width / the largest solder particle size Bump Height, H The height of solder bump. The bump height was measured using both a vernier caliper and a focusing method. The latter employed focusing on the top of the bump and on the surface of FR-4 board at 4X magnification using a metallographic microscope. The difference is recorded as bump height. Bump Volume, V B The volume of solder bump. In this study, this is calculated with the following equation. V B = (½) A x H + (π/6) H 3 Where A: the area of the pad. H: bump height. Challenge, C h Transfer Efficiency, E T Efficiency of solder paste transfer during print process. It is determined by dividing the bump volume by the theoretical solder volume allowed in the open volume. E T = V B / V S Where V S = V A x (solder volume fraction of solder paste) RESULTS The bump height and transfer efficiency results are shown in Table 2, while the yield results are shown in Table 3. Also included in the two tables are some properties derived from calculation. The first critical factor in this success is the satisfactory release of solder paste during printing stage. Fig. 4 demonstrates the print quality for solder paste using a 16 mil stencil with a 5 mil pitch BGA pattern. The aperture is 47 mil square. Fig. 4a shows the overall view of the print, while 4b shows the close-up look of the print quality. A similar print

6 quality is also achieved for CSP and wafer bumping applications, as demonstrated in Fig. 5 and 6, respectively. The second critical factor is good wetting and non-slumping. Fig. 7 shows array of 63Sn/37Pb solder bumps processed with solder paste print-detach-reflow for a 5 mil pitch BGA. The bump height is 27 ±.32 mil. Fig. 8 shows the SEM of array of 63Sn/37Pb solder bumps processed with solder paste printdetach- reflow for a 2 mil pitch CSP. The bump height is 9.1 ±.48 mil. Fig. 9 shows the SEM of array of 63Sn/37Pb solder bumps processed with solder paste print-detach-reflow for a 1 mil pitch wafer. The bump height is 4.1 ±.27 mil. Table 3 Yield results of paste bumping experiment Pitch Opening on squeegee Opening on board side, b Stencil thickness, h Largest particle size The cross-section view of those solder bumps are shown in Fig. 1 for BGA, Fig. 11 and 12 for CSP processed with IR and forced convection oven, respectively. Fig. 13 is picture of BGA solder bump. In general, those bumps present a fairly normal microstructure compared with bumps produced by sphere placement or other existing wafer bumping processes. The solder bump height distribution was determined with focusing methods on 3 bumps for each pattern. Results on BGA are demonstrated for 43 square aperture pattern, as shown in Fig. 14 for both overall view (left) and close-up view of distribution (right). Fig. 15 shows distribution for CSP for a R AS C h P NB Yield before reflow Yield after reflow side, a Square Opening Round Opening Taper angle, θ

7 b a Fig. 6 A close-up view (4X) of 63Sn/37Pb solder paste with particle size smaller than 2 microns printed for wafer solder bumping purpose. The stencil used is 3 mil thick with 1 mil pitch pattern. The tapered aperture is 5.5 mil and 7 mil for squeegee side and board side, respectively. Fig. 4 Pictures of 63Sn/37Pb solder paste with microns particle size printed using a 16 mil stencil with a 5 mil pitch BGA pattern. The aperture is 47 mil square. (a) shows the overall view of the print, while (b) shows the close-up look of the print quality. Fig. 7 SEM of array of 63Sn/37Pb solder bumps processed with solder paste print-detach-reflow for a 5 mil pitch BGA. The bump height is 27 ±.32 mil. Fig. 5 A close-up view (1X) of 63Sn/37Pb solder paste with particle size microns printed for CSP solder bumping purpose. The stencil used is 9 mil thick with 2 mil pitch pattern. The tapered aperture is 12 mil and 15 mil for squeegee side and board side, respectively. Fig. 8 SEM of array of 63Sn/37Pb solder bumps processed with solder paste print-detach-reflow for a 2 mil pitch CSP. The bump height is 9.1 ±.48 mil.

8 Fig. 9 SEM of array of 63Sn/37Pb solder bumps processed with solder paste print-detach-reflow for a 1 mil pitch wafer. The bump height is 4.1 ±.27 mil. Fig. 12 SEM picture of CSP solder bump manufactured with 63Sn/37Pb solder paste via print-detach-reflow process and reflowed with forced convection oven BTU-N7 under nitrogen. Fig. 1 SEM of cross-section of BGA solder bump manufactured with 63Sn/37Pb solder paste via print-detachreflow process. Fig. 13 SEM of cross-section of wafer solder bump manufactured with 63Sn/37Pb solder paste via print-detachreflow process. system with square aperture (top 12/bottom 15 mil), 9 mil tencil, and 2 mil pitch. Fig. 16 and 17 shows distribution for wafer with 1 mil pitch and 7 mil pitch, respectively. Fig. 11 SEM of cross-section of CSP solder bump manufactured with 63Sn/37Pb solder paste via print-detachreflow process. DISCUSSION 1. Yield The post-reflow defects observed in the study are mostly bridging, and occasionally missing balls. The yield after reflow is calculated based on the number of pads not meeting the acceptance criteria, then divided by the total number of pads involved in testing. The yield before reflow is determined by visual examination of the paste deposits. Deposits with bridging, smearing, or noticeably insufficient paste volume (around one half) were counted as defects. Most of the defects observed before reflow are paste bridging or smearing. Partial paste release typically was not counted as defects due to limitation in visual inspection method. This can be reflected

9 Fraction mil square aperture, 16 mil stencil, 5 mil pitch Fraction Square aperture top 12/bottom 15 mil, 9 mil thick stencil, 2 mil pitch Bump Height Bump Height Fraction mil square aperture, 16 mil stencil, 5 mil pitch Fraction Square aperture top 12/bottom 15 mil, 9 mil thick stencil, 2 mil pitch Bump Height Bump Height Fig. 14 BGA bump height distribution for a system with 43 mil square aperture, 16 mil stencil, and 5 mil pitch. Top graph is an overall view, while the bottom graph is a closeup view. by Fig. 18, where virtually no correlation exists between yield before reflow and transfer efficiency. By reviewing the yield data in Table 3, first it can be noticed that the both yields (before and after reflow) are very high, with majority greater or much greater than 99%. Secondly, the yield after reflow is fairly close to that of before reflow, as indicated by Fig. 19, where the ratio of yield after reflow to yield before reflow is close to one for most cases. Overall, the yield after reflow is determined by the yield before reflow, thus suggesting that the printing step is the most critical step for the systems studied. For printing, besides bridging and smearing, transfer efficiency is the most important parameter affecting the bumping quality, as will be discussed below. Fig. 15 CSP bump height distribution for a system with square aperture (top 12/bottom 15 mil), 9 mil stencil, and 2 mil pitch. Top graph is an overall view, while the bottom graph is a close-up view. Aperture Shape The slightly higher ratio value for round aperture reflects a better non-slump performance for round aperture. This is expected, since round print has more average spacing between deposits than square print does. However, the difference is not significant, suggesting a fairly good non-slump characteristics of those pastes studied. In addition, round also displays a slightly higher yield before reflow than square aperture, presumably due to a less chance in paste bridging or smearing. It should be emphasized again that the yield discussed here basically does not include partial paste release defects, thus does not reflect the transfer efficiency performance, which will be discussed later.

10 Fraction mil pitch, 2 mil stencil, square aperture top 3.3/bottom 5 mil Fraction mil pitch, 3 mil thick stencil, square aperture with top 5.5/bottom 7 mil Bump Height Bump Height Fraction mil pitch, 2 mil stencil, square aperture top 3.3/bottom 5 mil Fraction mil pitch, 3 mil thick stencil, square aperture top 5.5/bottom 7 mil Bump Height Bump Height Fig. 17 Wafer bump height distribution for a system with square aperture (top 3.3/bottom 5 mil), 2 mil stencil, and 7 mil pitch. Top graph is an overall view, while the bottom graph is a close-up view. Fig. 16 Wafer bump height distribution for a system with square aperture (top 5.5/bottom 7 mil), 3 mil stencil, and 1 mil pitch. Top graph is an overall view, while the bottom graph is a closeup view. Transfer Efficiency Tw o outlier data points at yield befow 99% are not included in this chart Yield before reflow Yield Ratio (after reflow/before reflow) Square aperture Round aperture Paste Bumping Systems Fig. 18 No correlation exists between E T and yield before reflow, since that partial release was not included as defects due to visual inspection limitation. Fig. 19 Ratio of yield after reflow to yield before reflow for paste bumping systems processed.

11 2. Transfer Efficiency Table 2 shows that the transfer efficiency E T ranges from 6% to 116%. Obviously, the higher the E T value, the easier to achieve the bump height desired. For the two incidences where the E T value (116% and 14%) being greater than 1%, the stencil thickness used was 2 mil and 2.5 mil, respectively. The excessive paste deposited may be caused by deviation from on-contact print, or a slight warpage of the stencil or board, or insufficient precision in bump height determination. For E T value less than 1%, it is crucial to find out and understand the causes in order to further improve the bump volume control. Area Ratio A high area ratio (the aperture area on board side divided by the aperture wall area) should favor a better paste transfer, as supported by Fig. 2. The wide data scattering and mild slope indicates the relation is not very strong, and other important factors affecting the transfer efficiency may exist. Transfer Efficiency Wide data scattering reflecting existence of other important factors y =.822x x R 2 = All aperture sizes and shapes Area Ratio Fig. 2 Relation between transfer efficiency and area ratio. Aspect Ratio Aspect ratio (the ratio of the smallest aperture width to the largest solder particle size) has been reported to be important for typical SMT solder paste printing process [11]. However, the results shown in Fig. 21 indicate the E T value is virtually independent of aspect ratio. This suggests that the dominant factors for transfer efficiency probably are other properties such as aperture shape, stencil thickness, area ratio, pitch, and challenge level, etc.. Stencil Thickness It is expected that the paste release from aperture will be more difficult with increasing stencil thickness, partly due to a parallel increase in area ratio. This is verified by Fig. 22. Similar to area ratio factor, the correlation is also a weak one. Perhaps another reason for this is a better continuity in cohesion. When print paste with a thicker stencil, the paste brick is taller, therefore may contain more intrinsic defects, such as voids, within the paste. Upon lifting of stencil, the Transfer Efficiency All aperture sizes & shapes y =.8191x -.41 R 2 =.3.4 Aspect ratio show s negligible effect on.2 transfer efficiency Aspect Ratio Fig. 21 Relation between aspect ratio and transfer efficiency. No effect of aspect ratio on E T can be noticed. Transfer Efficiency All aperture shapes & sizes y = 1.125x R 2 = Stencil Thickness Fig. 22 Relation between stencil thickness and transfer efficiency. paste will have a greater chance to rupture due to a higher chance of containing defects, or a poorer continuity in cohesion. For a thin stencil, since the dot size is small, the chance of paste rupture due to intrinsic defect becomes lower, hence renders a better paste release. Challenge In general, the more paste volume needs to be deposited for a given pitch dimension, the thicker stencil and the larger aperture needs to be used in order to achieve enough volume. Use of a thicker stencil directly challenges the release efficiency, as indicated by Fig. 22. Enlargement in aperture is expected to ease the release difficulty, thus may neutralize the adverse effect of a thicker stencil. Fig. 23 shows the overall effect of a greater challenge still cause a mild decrease in transfer efficiency.

12 Transfer Efficiency All aperture sizes and shapes.6 y = x x x R 2 = Decreasing challenge results in increasing transfer efficiency Challenge Stencil Thickness y = -.1x x + 12 R 2 = Pitch Fig. 23 Effect of challenge on transfer efficiency. A greater challenge results in a lower transfer efficiency. Pitch A smaller pitch results in a higher transfer efficiency, as indicated by Fig. 24. This is a surprise. Perhaps this phenomenon can be attributed to a thinner stencil together with a smaller challenge associated with a finer pitch, as shown in Fig. 25 and 26, respectively. For a finer pitch, generally a thinner stencil is used. However, the aperture design for a thinner stencil could not use a very small spacing, since the stencil thus made will be too fragile to sustain any manual handling. In other words, the challenge (the solder paste volume desired per unit volume space available on board for deposition) supportable by stencil manufacturing technology has to be smaller for a thinner stencil. As illustrated in Fig. 22 and 23, a higher transfer efficiency is accordingly resulted from a finer pitch. Fig. 25 Relation between pitch dimension and stencil thickness. The stencil thickness used in this study is based on subjective decision instead of optimized thickness. Challenge y =.28x R 2 =.5392 Challenge decreases with decreasing pitch, due to.5 stencil thickness chosed & stencil technology limitatio n Pitch Transfer Efficiency All aperture sizes & shapes y = -.72Ln(x) + 5 R 2 =.81 Transfer efficiency increases w ith decreasing pitch due to decreasing challenge Pitch (mils) Fig. 24 Effect of pitch on transfer efficiency. Finer pitch results in a higher E T value, perhaps due to a smaller chance in incorporating defects within the paste. Fig. 26 Relation between pitch dimension and challenge. Challenge decreases with decreasing pitch, primarily due to stencil manufacturing limitation. Aperture Shape Transfer efficiency is also affected by aperture shape. Two aperture shapes, square and round, were used in this study. The relative impact of shape can be expressed as ratio of transfer efficiency of square aperture to round aperture with comparable width. Fig. 27 shows that the average value of ratio is 1.1 and square aperture exhibits a better transfer efficiency. This better transfer efficiency associated with square aperture may be partly attributed to its higher area ratio. By examining Table 2, for CSP and BGA patterns (pitch greater than 1 mil), the average area ratio is.532 and.516 for square and round aperture, respectively. However, since the ratio of.532 to

13 Ratio of Transfer Efficiency with Equal Aperture Width (Sq/Round) Square aperture generally show s better transfer efficiency than round aperture of equal w idth 1 Average of ratio = is merely 1.3, it is not be sufficient to fully explain the more profound effect of square over round shape on transfer efficiency. Taper Angle Perhaps the favorable transfer efficiency of square shape can be better explained by taper angle effect. The taper angle θ for each individual aperture pattern is shown in Table 3. For CSP and BGA patterns, square aperture shows a higher average θ value (11.1 degree) than that of round aperture (7.9 degree). Since aperture with a larger taper angle is expected to display a better transfer efficiency, the considerably higher θ value of square versus round aperture may be the main reason that square aperture exhibits a better transfer efficiency than round aperture. 3. Bump Height The bump heights achieved in this study, as shown in Table 4, generally meet or exceed the requirement for area array packages. Table 4 also shows the diameter of sphere with an equivalent solder volume. The latter can be used to estimate the bump height for other packages with different pad diameter. The tight height control of the solder bumps, as demonstrated by Fig , also exceeds the common requirement of ± 2% in volume or size control [12]. Aperture Shape Bump height is affected by aperture shape. As shown in Fig. 28, square aperture provided a higher bump height, as illustrated by examining the ratio of bump height of square aperture to that of round aperture. Here the width of square aperture is comparable to the diameter of round aperture compared. In all incidences, the ratio is always larger than 1. The higher bump height associated with square aperture is Stencil Design Systems 13 Fig. 27 Effect of stencil aperture design on transfer efficiency. 15 Ratio of Bump Height with Equal Aperture Width (Sq/round) CSP & BGA understandable based on its larger aperture volume and transfer efficiency. Since the round aperture only shows a marginally higher yield than square system, while the square system provides a considerably higher bump height, it becomes obvious that a square aperture design should be used for paste bumping process. Pitch The bump height decrease rapidly with decreasing pitch, as shown in Fig. 29. Although the decreasing trend is expected, the decreasing rate is not necessarily reflecting the maximal bump height achievable. Instead, it is affected by the stencil 9 11 Paste Bumping Systems Fig. 28 All systems studied here showed a higher bump height is obtained from the square aperture rather than from the round aperture. Here the width of square aperture is comparable to the diameter of round aperture compared. Bump Height y =.55x x R 2 = Pitch Fig. 29 Relation between pitch and bump height.

14 Table 4 Solder bump height and equivalent solder volume for each system studied. Pitch Bump height, H Equivalent sphere diameter Square Opening Round Opening thickness used in this study, and the maximum opening volume allowed. The stencil thickness chosen in this study (see Fig. 25) is a result of subjective decision. For wafer or CSP bumping applications, a thicker stencil may be used. This thicker stencil should be more sturdy, thus allow the use of a smaller spacing or the design of a higher challenge (larger aperture volume) for aperture pattern. Normalized Bumping Performance (PNB) y =.15x R 2 = Pitch Fig. 3 Relation between pitch and normalized bumping performance. Normalized Bumping Performance Although bumping performance is normally evaluated according to the net bump height achieved, the bumping potential can be more objectively analyzed based on normalized bumping performance. The latter is the solder volume V B deposited per unit volume space available on board for deposition. By analyzing bumping volume this way, the pitch variation factor can be thus eliminated, and pastes bumping performance on different pitch levels or footprint patterns can be cross-compared. If a paste shows a higher normalized bumping performance than another paste, the former paste most likely will always provide a higher bump height if tested on the same pitch device. Fig. 3 shows the normalized bumping performance P NB declines with decreasing pitch. However, as discussed in earlier section, this is attributable to the stencil thickness chosen subjectively, and the maximum stencil opening allowed accordingly. A properly designed stencil thickness may allow a higher P NB value for the finer pitch. Potential of Paste By plotting the normalized bumping performance P NB against challenge C h it would allow people to estimate if the paste bumping performance can be pushed further to a higher level. Fig. 31 shows that the P NB value is almost linearly proportional to C h value. This behavior suggests that the paste bumping performance may still increase with further increase in challenge (a higher C h value). This bumping performance potential may reach its limit if the curve starts to level off or turn downward. This stipulation is supported by the relation between transfer efficiency and normalized bumping performance. Fig. 32 shows that the normalized bumping performance is virtually

15 Normalized Bumping Performance y =.4371x x +.86 R 2 =.8792 All aperture size and shapes Bumping performance increases linearly with.2 increas ing challenge, indicating printing has not run into limitatio n o f materials yet Challenge microstructure may be caused by the difference in cooling rate. It suggests that the microstructure of solder bumps formed may be sensitive to either the reflow oven used or the profile used. A higher magnification of the microstructure of BGA, CSP, and wafer is shown in Fig. 33, 34, and 35, respectively. The thickness of Cu-Sn intermetallics layer ranges from 1-3 µ, also within the normal range. Although few voids were observed occasionally, no microvoids can be discerned at magnification up to 5X, reflecting a solid microstructure needed for a reliable solder structure formation. 4. Stencil As discussed in the Yield section, slumping or bridging is not an issue with the pastes studied here. For such paste systems, a stencil pattern with a very small spacing is acceptable. This characteristics allows the stencil opening to be maximized thus allows the use of a thinner stencil hence a better paste Fig. 31 Relation between challenge and normalized bumping performance. Normalized Bumping Performance All aperture sizes & shapes y =.115x R 2 =.36.2 Bumping performance is independent of transfer efficiency Transfer Efficiency Fig. 33 Microstructure of BGA 63Sn/37Pb solder bump formed with solder paste which was reflowed with IR oven. The intermetallic layer is about 2-3 µ thickness. Fig. 32 Relation between transfer efficiency and normalized bumping performance. independent of transfer efficiency, reflecting that the bumping performance has not reached the limit of paste release capability yet. Instead, it is merely refrained by other factors such as stencil thickness chosen or the maximum challenge allowed due to limitation in stencil manufacturing technology, as discussed in the previous sections. Microstructure The metallurgical microstructure of the solder bumps formed, as shown in Fig. 1-13, indicate a normal characteristics of solder bumps. It is interesting to note that the bump formed from forced convection oven exhibits distinct crystalline structure (see Fig. 12) while that from IR oven exhibits a much finer microphase structure (Fig. 11). This difference in Fig. 34 Microstructure of CSP 63Sn/37Pb solder bump formed with solder paste which was reflowed with IR oven. The intermetallic layer is about 2-3 µ thickness.

16 Fig. 35 Microstructure of wafer 63Sn/37Pb solder bump formed with solder paste which was reflowed with IR oven. The intermetallic layer is about 1-2 µ thickness. release. Stencil Design Guideline Always maximizing the opening and minimizing the stencil thickness should be the rule to be applied to stencil pattern design for paste bumping purpose. Bottleneck For Further Improvement The approach described above challenges the stencil technology, since the aspect ratio for stencil manufacturing is typically That is, the spacing can not be smaller than the thickness of the stencil. Fig. 36 shows the stencil with 47 mil aperture width. Thus the 3 mils spacing for the stencil is much smaller than the stencil thickness (16 mil) used. The stencils used in this study were made, although with difficulty, via electroforming process. Those stencils demonstrate that the large aperture design desired for paste bumping process are manufacturable. Presumably with further improvement in process control, the stencil design can be pushed to an even larger opening, thus allows more paste volume to be deposited. In the case of wafer bumping, the stencil aperture design provides a considerably smaller challenge C h than that of BGA or CSP, as shown in Table 3 and Fig. 26. This design constraint caused by the fragileness of thin stencil suggests that an improvement in wafer bumping performance is relying on the development of a stronger stencil material. 5. Printing The three pastes used in this study generally is high in viscosity in order to maximize the slump resistance. For a successful implementation of paste bumping process, a slow squeegee speed such as 1 mm/sec will be required. The stencil surface used in this study was smooth and shiny. The authors anticipate that a stencil with matte surface or otherwise roughened surface (such as sand blast) will facilitate Fig. 36 An electroformed stencil with 47 mil aperture width and 16 mil thickness. a better paste rolling, thus a better print consistency. Due to the high viscosity, enclosed chamber print head design may not be adequate for handling this type of paste. 6. Effect of Solder Paste Materials The paste bumping process has been conducted with the use of different paste materials, including the flux and/or powder. In order to understand the effect of paste characteristics on bumping performance, the average value of P NB for three pastes are calculated, with the results shown in Table 5. Paste C has the best bumping performance, followed by Paste B, with Paste A being the lowest in P NB value. Table 5 Comparison of P NB for various pastes studied. Paste P NB Metal Volume Fraction Average Challenge Involved In Applications, C h A B C Also shown in Table 5 is the paste metal content (v/v). Results indicate that the normalized bumping performance increases with increasing metal content, as further illustrated by Fig. 37, thus demonstrating the key approach of further improving paste bumping performance. However, the impact of paste metal volume fraction on P NB should not be over emphasized. By examining Table 5, paste C exhibits a value in P NB about two times of that of A and B, while the metal volume fraction is only slightly higher than that of A and B. The P NB performance exhibited by the pastes actually can be better correlated with the challenge values associated with the paste applications, as shown in Table 5. As discussed earlier,

17 PNB (Normalized Bumping Performance) R 2 = Metal Vol Fraction in Paste Fig. 37 Relation between metal volume fraction of solder paste with normalized bumping performance (P NB ). the challenge level is determined by the stencil design, rather than the paste chemistry. 7. Cleanability The flux residue of all three solder pastes used in this study is cleanable with solvents, such as Kyzen s Micronox 231 wafer cleaner. CONCLUSION Several unique solder paste systems have been developed and tested for 63Sn/37Pb solder bumping for wafer, CSP, and BGA with the low cost print-detach-reflow process. The results indicate that the bump height achieved is very adequate and consistent for all three area array package systems. Microstructure of solder bumps appears normal. The yield is also very high for both before reflow and after reflow condition, and is dictated by printing performance. With the unique high slump resistance exhibited by those newly developed pastes, the paste transfer efficiency at printing stage becomes the most critical performance for this process. The transfer efficiency increases with increasing area ratio, increasing taper angle, decreasing pitch, decreasing stencil thickness, decreasing challenge, with adoption of square aperture design, and is not sensitive to aspect ratio of aperture to solder particle size. The paste systems appear to have more potential for depositing a larger amount of paste per unit pitch, as evidenced by the linear relation between expected paste volume and the deposited paste volume. Increasing metal content helps improving bumping performance. The bottleneck of increasing bumping performance for wafer applications appears to be developing a stencil manufacturing technology capable of providing an aperture pattern with spacing considerably smaller than the stencil thickness. Slow print speed is also essential for adequate printing. A non-shiny non-smooth stencil surface is considered beneficial for aiding paste rolling. The flux residue of those pastes is cleanable with solvents. ACKNOWLEDGEMENT The authors would like to express great appreciation to Benjamin E. Nieman and Geoffrey K. Beckwith for their dedication in developing solder paste products and testing work for this project. REFERENCE 1. J. Kloeser & R. Aschenbrenner, H. Reichl, "Low cost flip-chip assembly: a challenge for future market", in Proc. Of The Third International Symposium of Electronic Packaging Technology, p , Aug , 1998, Beijing, China.T. Oppert, T. Teutsch, E. Zakel, D. Tovar, A low cost bumping process for 3 mm wafers, in Proceedings of IMAPS, p.34-38, 1999.A.J.G. Strandjord, S.F. Popelar, and C. A. Erickson, Low cost wafer bumping processes for flip chip applications (Electroless Nickel-Gold/Stencil printing), In Proceedings of IMAPS, p.18-33, J. Kloeser, P. Coskina, E. Jung, A. Ostmann, R. Aschenbrenner, and H. Reichl, A low cost bumping process for flip chip and CSP applications, In Proceedings of IMAPS, p. 1-7, J.D. Schake, Stencil printing for wafer bumping, Semiconductor International, p , October Joachim Kloeser, Kai Kutzner, Erik Jung, Katrin Heinricht, Liane Lauter, Michael Töpper, Eiji Ochi*, Rolf Aschenbrenner and Herbert Reichl, "EXPERIENCE WITH A FULLY AUTOMATIC FLIP-CHIP ASSEMBLY LINE INTEGRATING SMT", in Proc. Of Nepcon West 1998, Anaheim, CA, Mar. 1-5, J. Kloeser & R. Aschenbrenner, H. Reichl, "Low cost flip-chip assembly: a challenge for future market", in Proc. Of The Third International Symposium of Electronic Packaging Technology, p , Aug , 1998, Beijing, China 8. N.-C.Lee, Troubleshooting BGA assembly, in Symposium of BGA, in Nepcon West, Anaheim, CA, Feb., Jack Bogdanski, "The Economies of Flip Chip Wafer Bumping and Assembly", in Proc. Of Nepcon West 1998, Anaheim, CA, Mar. 1-5, M. Kelly and J. Lau, Low cost solder bumped flip chip MCM-L demonstration, Circuit World, Vol. 21, No. 4, M. Xiao, K.J. Lawless, and N.C. Lee, Prospects of solder paste applications in ultra-fine pitch era, Surface Mount International, San Jose, CA, Aug Private communication with Joseph Fjelstad, Dec. 21, 1999.