A HIGH SPEED FIFO DESIGN USING ERROR REDUCED DATA COMPRESSION TECHNIQUE FOR IMAGE/VIDEO APPLICATIONS

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1 A HIGH SPEED FIFO DESIGN USING ERROR REDUCED DATA COMPRESSION TECHNIQUE FOR IMAGE/VIDEO APPLICATIONS #1V.SIRISHA,PG Scholar, Dept of ECE (VLSID), Sri Sunflower College of Engineering and Technology, Lankapalli, (A.P),INDIA #2MR. CH.NAGA SRINIVASARAO M.Tech., Assistant Professor, ECE, SSCET, Lankapalli,(A.P), INDIA ID: ABSTRACT: Many image/video processing algorithms require FIFO for filtering. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. We have proposed an energy- and area-efficient FIFO design for image/video applications through FIFO with error-reduced data compression (FERDC) and near-threshold operation. On architecture level, FERDC technique is proposed to reduce the size and power consumption of the FIFO by utilizing the spatial correlation between neighboring pixels and performing error-reduced data compression together with quantization to minimize the mean square error (MSE). On circuit level, near threshold operation is adopted to achieve further power reduction while maintaining the required performance. To demonstrate the proposed FIFO, it has been implemented using a 0.18-μm CMOS process technology. The implementation covers different FIFO length, including 128, 256, 512, and The experimental results show that the proposed FIFO operating at 0.5 V and MHz achieves up to 99%, 65%, and 34.91% reduction in dynamic power, leakage power, and area, respectively, with a small MSE of 2.76, compared with the conventional FIFO design. The proposed FIFO can be applied to a wide range of image/video signal processing applications to achieve high area and energy efficiency. Keywords: Data Compression, FIFO, Differential Predictor, Quantizer, Encoder, Decoder, MSE, Thresholding, Image/ Video Processing. I INTRODUCTION Recent developments in the integrated circuit (IC) design technology enable us to realize complex algorithms on silicon. Most of the image/video processing algorithms implemented in ICs for the real time performance are memory dominant. Moreover, some need to be ultra-low power, especially for biomedical and mobile applications. Therefore, one of the main bottlenecks of fulfilling an ultra-low power image/video processor lies in on-chip memory such as SRAM and FIFO. According to the studies, on-chip memory occupies 50%-80% of the overall power consumption. Laplacian Pyramid (LP) is one of the popular multiresolution (multiscale) image representations in image/video processing applications such as image fusion, compression, feature extraction and object recognition. Various LP hardware designs have been proposed. However, they all focus on the performance rather than the power consumption. As portable applications become more and more popular, there is an increasing demand for system miniaturization and low power consumption, which is shifting the design focus from performance to area & power optimization. As a heavily used component in LP processing engine (LPPE) as well as in other image/video processors, FIFO consumes significant portion of area and power consumption. Various techniques available in literature for dealing with FIFOs can be categorized as architecture-level and circuit level techniques. A recent work published is a general architecture-level approach introducing the area and energy efficient FIFO through error-reduced PAPER AVAILABLE ON 176

2 data compression (FERDC). FERDC reduces dynamic and leakage power, and area by 28.84% and 32.73%, and 34.91% respectively. coefficients (D1) are obtained by subtracting theestimated image from the original input image. II. LITERATURE SURVEY Video frame storage and synchronization are a part of almost any video and imaging application. Because the nature of video data is sequential, high-density FIFOs (HDFIFOs) are best suited for these applications. This application note describes a few video applications to explain the data path and data handling required. It also compares implementing a frame buffer using Cypress HDFIFO (CY7FXXXX) to the conventional method of using an FPGA and DDR SDRAM, along with memory size and bandwidth calculations. Advantages of using Cypress HDFIFO over the conventional solution are described. Fig. 1: General Laplacian Pyramid structure. In our previous LP design as illustrated in Fig. 2, novellp architecture using poly-phase representations and nobleidentities is proposed to reverse the order of resampling andfilters and hence avoid redundant and zero-operand operations,occupying 50% of overall operations. Overview of Video Applications Figure 1 shows the system block diagram of an IPTV. The input transport streams in any encoded format such as DVB ASI, MPEG2, or SDI are passed through a multi-format codec to be transcoded into an H.264 transport stream. The encoded transport stream is encapsulated with channel information and sent over Ethernet. On the receiving path, the incoming transport stream is decoded. Postprocessing such as noise reduction, color enhancement, scaling, and deinterlacing occurs before display. PREVIOUS LAPLACIAN PYRAMID (LP) ARCHITECTURE LP comprises decimation and interpolation functions asshown in Fig. 1. The decimation part, denoted as Gaussianpyramid (GP), produces low frequency coefficients (C1) froman input image (C0). The output of the decimation part isfurther processed by the interpolation part to calculate anestimated version of the input image. Subsequently, highfrequency Fig. 2: LP architecture In our previous LP design as illustrated in Fig. 2, novellp architecture using poly-phase representations and nobleidentities is proposed to reverse the order of resampling andfilters and hence avoid redundant and zero-operand operations,occupying 50% of overall operations. E0 and E1 are filterblocks, and R0 and R1 are polyphase components. It is worthnoticing that two rows (Row2i and Row2i-1) of an image areprocessed in Fig. 2 because the equivalent Column block in Fig. 2 necessitates its second input from the next row. Each Column block (Fig. 2) requires a FIFO block to keep the essential number of data, generated by the PAPER AVAILABLE ON 177

3 Row block. Its size is calculated by the filter length, the input image width and the input data bitwidth. Moreover, since the Delay blocks synchronize the original input data with the outputs of Column block in interpolation part, they are also realized by the FIFOs. Their size is defined by the input data bit-width andthe total delay introduced by decimation and interpolationparts. FIFOs dominate the area and powerof the LPPE and therefore, smart FIFOs are highly required tofurther improve the area and the power of the LPPE III EXISTING SYSTEM On Architecture level, a technique named as FIFO with error-reduced data compression (FERDC) is proposed to reduce the FIFO size. This reduces both area and power consumption of the FIFO with negligible distortion. On circuit level, Near- Threshold operation is adopted to reduce the power consumption of the FIFO. Fig.3 shows the Existing FERDC technique to realize an 8 8 filter using the architecture described. Since there is an eight-tap vertical filter applied, seven FIFOs are required to store the data in Fig.1. The FERDC employs a concept of pixel prediction, where every pixel can be predicted utilizing adjacent pixels and accordingly input data is horizontally decorrelated and then quantized. Finally, the encoded data read from FIFO are decoded to retrieve the original input data. Therefore, it consists of encoding and decoding parts along with the reduced-size FIFO. Therefore, in Fig. 1, all FIFOs except for the first one are fed by the output of previous FIFOs. Fig. 3 FIFO Architecture for an Eight-tab Vertical Filter. Problem Statements: The main Problem in the Existing System is Data Serialization and More Delay. The Existing System is Slow in Implementation. Due to Data Serialization Errors may be Increased. The Mean Square Error and Peak Signal to Noise Ratio will be Increased A Good Quality Image with Spatial Correlation is not Obtained in the Output. IV PROPOSED SYSTEM Due to the Problems in the Existing system A Parallel Architecture is Proposed. Many Image Processing Algorithms are Implemented with Fixed- Point Arithmetic, B can be Measured at the Output of the Horizontal filter Performed by the Direct-Form Implementation, as shown in Fig. 4. Direct-Form Implementation of Horizontal Filters. In this Proposed System, Parallel Processing is Used Instead of Serial Processing. For this We are 8-bit Registers are Placed in between the Different Block Outputs to Store 8-bit Data at a Time and Process that Data at a Time. Due to this Parallel Processing the Delay is Reduced and hence the System is Implemented with High Speed. Fig.4 shows the proposed FERDC technique to realize an 8 8 filter using the architecture. Since there is an eight-tap vertical filter applied, seven FIFOs are required to store the data in Fig.3.2 The FERDC employs a concept of pixel prediction, where every pixel can be predicted utilizing adjacent pixels and accordingly input data is horizontally decorrelated and then quantized. Finally, the encoded data read from FIFO are decoded to retrieve the original input data. Therefore, it consists of encoding and decoding parts along with the reduced-size FIFO. Therefore, in Fig.3.2, all FIFOs except for the first one are fed by the output of previous FIFOs. PAPER AVAILABLE ON 178

4 Therefore, one encoding part is required for the seven FIFOs, while one decoding part is needed at the output of each FIFO. Fig 4: FIFO Architecture for Eight-tab Vertical Filter (a) Using Proposed Technique (b) Using Conventional FIFO. V. METHODOLOGY This project proposes a power and area efficient Laplacian Pyramid processing engine (LPPE) for multiresolution image representation in image/video processing. In the proposed LPPE, a novel FIFO architecture with adaptive data compression is proposed to reduce the power and area consumption of LPPE. A new filtering extension method is also proposed to reduce the output errors. In circuit level, near threshold design is adopted to further reduce the power consumption by supply voltage scaling. width, yi is updated by the quantization error of the previous data to prevent the quantization errors from being accumulated at the output (xiq1). However, this input-independent data compression causes large MSE at the outputs. To address this, a Quantizer Parameters Adaptive Tuning Block is designed to make the compression adaptive to the input data so as to reduce the MSE. The four quantizer parameters fl, sl, Step1 and Step 2 are updated as a function of the maximum value of the present row to make the quantizer adaptive for the next incoming data spectrum. After updating the quantizer parameters, it is still possible for some values in the next row to fall outside of [-sl, sl]. Therefore, while processing the next row, the corresponding errors from the quantizer are averaged and used to update the retrieved data. FAREDCs are used in the FIFO and Delay blocks to reduce the area and power. The proposed FIFOs architecture for a sample 5th-order filter. In the output of each FIFO block, named as yi sj D where j varies from 1 to 4, is connected to the input of the next FIFO Core. FIFO Results: VI. RESULTS Existing System Results FIFO With Error Reduced Data Compression (FERDC): In this work, we propose a FIFO with adaptive error reduced data compression (FAERDC). The operation principle of FAERDC in a 5th order. It utilizes a differential predictor to remove the horizontal correlation between the subsequent data and generates the energy-compacted output (yi). Before sending yi to the quantizer (Q) to reduce the data Fig 5: RTL Schematic PAPER AVAILABLE ON 179

5 Fig 6: Technology Schematic Fig 8 : simulation result of the existed FERDC technique Proposed System Results: Fig 7: Design Summary Synthesis Report: Timing Summary: Minimum period: ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 4.651ns Maximum output required time after clock: 4.310ns Maximum combinational path delay: No path found Fig 9: RTL Schematic PAPER AVAILABLE ON 180

6 Maximum output required time after clock: 4.063ns Maximum combinational path delay: No path found. Fig 12: Simulation results of the proposed (parallel processed) FERDC technique Fig 10: Technology Schematic VII. CONCLUSION In this Paper, A High Speed FIFO is Designed Using Error-Reduced Data Compression Technique for Image/Video Applications. The Proposed Design is Applied to an Image Filtering Application, and Achieves. VIII. REFERENCES [1] K. Danckaert, K. Masselos, F. Cathoor, H. J. De Man, and C. Goutis, "Strategy for power-efficient design of parallel systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 2, pp , Jun Synthesis Report: Timing Summary: Fig 11: Design Summary Minimum period: 8.758ns (Maximum Frequency: MHz) [2] P. Burt and E. Adelson, "The Laplacian Pyramid as a Compact Image Code," IEEE Trans. commun., vol. 31, no. 4, pp , Apr [3] D. G. Lowe, "Distinctive Image Features from Scale-Invariant Keypoints," International Journal of Computer Vision, vol. 60, no. 2, pp , Minimum input arrival time before clock: 4.084ns PAPER AVAILABLE ON 181

7 [4] S. Chen, Q. Guo, H. Leung, and E. Bosse, "A Maximum Likelihood Approach to Joint Image Registration and Fusion," IEEE Trans. Image Process., vol. 20, no. 5, pp , May IX AUTHORS [5] Y. Song, K. Gao, G. Ni, and R. Lu, "Implementation of real-time Laplacian pyramid image fusion processing based on FPGA," Proceedings of the SPIE, 2007, pp [6] V. Popovic, K. Seyid, A. Schmid, and Y. Leblebici, "Real-time hardware implementation of multi-resolution image blending," in IEEE Int. Conf. ICASSP, Vancouver, BC, 2013, pp [7] S. M. A. Zeinolabedin, N. Karimi, and S. Samavi, "Low computational complexity hardware implementation of Laplacian Pyramid," in Proc. IEEE 18th Iranian Conf. Electr. Eng., 2010, pp CH.NAGA SRINIVASARAO, M.Tech Assistant professor, Sri Sun Flower College of Engineering & Technology, Lankapalli V.SIRISHA, PG scholar Dept of ECE (VLSID), Sri Sunflower College of Engineering and Technology, B.Tech degree in Electronics and Communication Engineering at DMSSVH College of Engineering And Technology, Machilipatnam PAPER AVAILABLE ON 182