EAGLE V 4240 Instruction Manual

Transcription

1 EAGLEV_IM_V1.1_ doc 20/11/14 1 of 34 Project designation Eagle V 4240 Scientific CCD Camera Document title Eagle V 4240 Instruction Manual This document is the property of Raptor Photonics and must not be copied, shown or in any way be communicated to persons other than those requiring the information for the execution of their duty.

2 EAGLEV_IM_V1.1_ doc 20/11/14 2 of 34 DOCUMENT VALIDATION Name Title Date Prepared Brendan Rolston CTO 4 th June 2014 Reviewed Geoff Martin Principal Systems Engineer 20 th Nov 2014 Reviewed Reviewed Reviewed Reviewed Approved Brendan Rolston CTO 20 th Nov 2014 Authorized Brendan Rolston CTO 20 th Nov 2014 DOCUMENT CHANGE RECORD Issue Change order Date Pages affected Comment - 04/06/14 Draft 1.0 N/A 13/06/14 First Issue 1.1 N/A 20/11/14 24,25,27,28,29 Updated default delays for shutter and readout mode default = 0x01

3 EAGLEV_IM_V1.1_ doc 20/11/14 3 of 34 TABLE OF CONTENTS 1 SCOPE DESIGN OVERVIEW Mechanical Profile Physical Interfaces Liquid cooling quick release couplings Camera link connector Input Power to Power Supply Module Trigger In (50Ω SMA) Trigger out, Exposure (50Ω SMA) Trigger out, Readout (50Ω SMA) Digital Video out CAMERA CONTROL DETAILS Micro reset System state FPGA control register Frame rate Exposure Trigger Modes Idle mode Internal Trigger External Trigger Snapshot trigger Trigger Abort ROI (Region of Interest) Binning Binning and ROI Pixel readout rate Shutter control Test Pattern Image Unit Serial number Manufacturers Data ADC calibration data (Sensor Temperature) DAC calibration data SERIAL COMMUNICATION (CAMERALINK INTERFACE) Overview ETX/ERROR codes Set Commands Query Commands Serial Command Examples Set System status (Enable Command Ack and Check sum mode) Get System Status Get Micro version... 29

4 EAGLEV_IM_V1.1_ doc 20/11/14 4 of Get FPGA version Reset camera Read Sensor PCB temperature Serial Command Error Examples Missing or wrong checksum Partial host command with missing data/etx/checksum Corrupt/Unknown host command FPGA FIRMWARE UPLOAD FIGURES Figure 1: (a) & (b) Camera module, (c) Power Supply Module and (d) Camera Power Cable Figure 2: SolidWorks model basic dimensions of camera module... 6 Figure 3: SolidWorks model basic dimensions of power supply module... 7 Figure 4: Mechanical profile drawing SolidWorks model... 8 Figure 5: 26 pin MDR Connector... 9 Figure 6: Example frame periods and rates with symmetric binning Figure 7: Digital Video Timing Figure 8: External Trigger timing Figure 9: ROI size and offset Figure 10: CCD temperature as a function of ADC value

5 EAGLEV_IM_V1.1_ doc 20/11/14 5 of 34 1 SCOPE This document provides detailed instructions for the operation of the Eagle V 4240, liquid cooled, Scientific CCD camera. Details of the camera electrical interfaces and communication protocols are also provided. Photographs of the Camera module, Power Supply and Camera Power Cable are shown below. (a) (b) (c) (d) Figure 1: (a) & (b) Camera module, (c) Power Supply Module and (d) Camera Power Cable.

6 EAGLEV_IM_V1.1_ doc 20/11/14 6 of 34 2 DESIGN OVERVIEW 2.1 Mechanical Profile Camera weight = 3.0kg Units shown in [inches] mm Figure 2: SolidWorks model basic dimensions of camera module

7 EAGLEV_IM_V1.1_ doc 20/11/14 7 of 34 Power Supply weight = 0.5kg Units shown in [inches] mm Figure 3: SolidWorks model basic dimensions of power supply module

8 EAGLEV_IM_V1.1_ doc 20/11/14 8 of 34 Figure 4: Mechanical profile drawing SolidWorks model Feature Description 1,2 Liquid cooling inlet/outlet valved coupling, CPC P/N MCD TTL Trigger output, 50ohm SMA (Exposure) 4 TTL Trigger output, 50ohm SMA (Readout) 5 Camera link connector (Base) MDR, 3M P/N PC 6 Label recess, (Model Number. Serial Number) 7 TTL Trigger input, 50ohm SMA (Trigger In) 8 Camera power connector, LEMO P/N EGG.2B.319.CLL (mating cable supplied)

9 EAGLEV_IM_V1.1_ doc 20/11/14 9 of Physical Interfaces Liquid cooling quick release couplings The camera electronics drive a ThermoElectric Cooler (TEC) to cool the CCD. The Hot side of the TEC is cooled via circulating coolant. Connection to the coolant channel is made via two quick release, valved coupling bodies (Colder Products Co. P/N MCD1004). Please ensure compatibility with these connectors on the camera module before attempting to connect the coolant supply Camera link connector The camera uses a camera link standard Mini Delta Ribbon (MDR) 26 way connector, 3M, P/N PC. The pin-out is shown below. TxOUT0_N TxOUT1_N TxOUT2_N TxCLKOUT_N TxOUT3_N SerTC_P SerTFG_N CC1_N CC2_P CC3_N CC4_P TxOUT0_P TxOUT1_P TxOUT2_P TxCLKOUT_P TxOUT3_P SerTC_N SerTFG_P CC1_P CC2_N CC3_P CC4_N GND MDR26 3M_MDR_EZ8B Figure 5: 26 pin MDR Connector Input Power to Power Supply Module 12VDC power is delivered to the power supply module via a 2 way LEMO socket, P/N EGG.2B.302.CLL. The corresponding plug connector is P/N FGG.2B.302.CLAD92 (for normal entry version) or P/N FHG.2B.302.CLAD62 (for right angled version). The pin out of the connector is detailed in the table below. Pin Number Connection 1 +12VDC 2 GND Unit input power specification is +12VDC ± 10%, power dissipation 20W with the TEC switched off. Additional inrush current (peak power) is required when the cooler power is switched from low to high. Peak power 120W with total, steady state power consumption 100W _CN1 inner_shield1 X0- X1- X2- Xclk- X3- SerTC+ SerTFG- CC1- CC2+ CC3- CC4+ inner_shield2 inner_shield3 X0+ X1+ X2+ Xclk+ X3+ SerTC- SerTFG+ CC1+ CC2- CC3+ CC4- inner_shield4 MOUNTING1 MOUNTING2 MDR26

10 EAGLEV_IM_V1.1_ doc 20/11/14 10 of Trigger In (50Ω SMA) External synchronisation with the start of integration signal may be achieved using the Trigger IN connector. Input impedance = 510Ω, 200pF input capacitance. Input logic levels are: - Logic HIGH > 2.31V - Logic Low < 0.99V Min. pulse width = 100ns Trigger out, Exposure (50Ω SMA) For all modes of the camera the Trigger output, Exposure SMA, will represent the integration period of the sensor. The trigger output signal will be a TTL output pulse. The signal will remain low (0V) and then be driven high during the integration period. The source impedance will be equal to 50Ω Trigger out, Readout (50Ω SMA) For all modes of the camera the Trigger output, Readout SMA, will represent the duration of the CCD readout. The trigger output signal will be a TTL output pulse. The signal will remain low (0V) and then be driven high during the read out period of the CCD. The source impedance will be equal to 50Ω.

11 EAGLEV_IM_V1.1_ doc 20/11/14 11 of Digital Video out The Eagle V camera produces mono, digital video output. A camera link strobe clock of 40MHz is used with 16bit data and 1 tap output, i.e. Base camera link. Output signals comply with the Camera Link Standard ( Ref. For unbinned image data, pixel readout rates of 2MHz and 75kHz are available. Applying only horizontal binning will reduce the time to readout a frame (frame period) at 75kHz pixel readout rate, however the frame period will be unaffected at 2MHz pixel readout rate. Combinations of Horizontal and Vertical binning may be used to increase the frame rate. For minimum exposure example minimum frame periods, maximum frame rates, are given below: 2MHz Pixel clock 75KHz Pixel clock BIN Frame Period (s) Frame Rate (Hz) BIN Frame Period (s) Frame Rate (Hz) Figure 6: Example frame periods and rates with symmetric binning FVAL is held high for the duration of a valid frame readout LVAL is held high for the duration of a valid line readout & will go low before/after each valid line DVAL will only go high for valid pixels during a line read out, and will stay high for the duration of a 40MHz clock period. Logic levels are as per camera link standard. The Eagle V 4240 has active pixels. Camera link signals and pixel order as shown below.

12 EAGLEV_IM_V1.1_ doc 20/11/14 12 of 34 FV HIGH FV PERIOD FVAL LV HIGH LVAL DVAL LV START LV LOW CH1 data Pixel no. DVAL/ Pixel No. 1 2 CH1 data/ Pixel No. 1 X X 2 X Figure 7: Digital Video Timing FVPERIOD FVHIGH LVSTART = Frame Valid period, Programmable see table + add exposure time = Frame Valid High = see table = Delay from rising edge of Frame Valid to Rising edge of first Line valid = Line Valid Start = (100µs) ybin + (8.4µs) (2052/ybin) LVHIGH = Line Valid High = (FVHIGH / no. of lines) - LVLOW LVLOW = Line Valid low = LVSTART Image Latency is not more than1 line period The Eagle V 4240 camera has been tested and verified on EPIX PIXCI EL1, EB1, E4 and E8 camera link frame grabber cards.

13 EAGLEV_IM_V1.1_ doc 20/11/14 13 of 34 3 CAMERA CONTROL DETAILS 3.1 Micro reset The camera contains an internal microcontroller that is used to process serial commands from the host. The micro controller can be reset by sending a reset command. The micro will take approx. 100msec to reset. The host can poll the camera with a Get System Status command until a valid response is received. 3.2 System state The system state register is used to control the serial communications mode and enable access to the on board EPROM for programming and reading system information. The system state register may also be used to reset the FPGA or hold the FPGA in reset. Note that when reset is released the FPGA will take approx. 500msecs to reboot. 3.3 FPGA control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PreAmp gain Reserved Reserved Reserved Reserved Reserved OVERTEMP TEC on/off The FPGA control register is used to switch the cooling ON/OFF, read the status of the over temperature flag and to select the level of preamp gain. The set point for the TEC cooling is controlled by a 12 bit DAC see section An over temperature flag is also provided that gives the status of the cameras over temperature trip. If the internal temperature of the camera s PCB goes beyond 80 C the TEC power will be turned off and this flag will be set to 1. The TEC power will remain off until the OVRTEMP flag is reset by sending a command to the FPGA control register to clear this bit. The camera will continue to function if this flag is high but the TEC cooling will be disabled. By default the camera powers on with a conversion factor ~1e/ADU giving a maximum signal level of approximately electrons. The TEC will be OFF by default.

14 EAGLEV_IM_V1.1_ doc 20/11/14 14 of Frame rate When internal trigger and fixed frame rate have been selected the Frame rate registers are used to specify the required frame rate. A 32 bit register is used to hold the frame rate value with each count equal to 25nsecs (i.e. 1/40MHz). For example; 1frame per second 1frame per minute 1frame per hour = 40,000,000cnts = 2,400,000,000cnts = 144,000,000,000cnts Should the exposure exceed the frame period then the exposure will dominate and the frame rate will be reduced accordingly. The maximum frame rate that can be achieved is dependent on the pixel readout rate, the vertical dimension (i.e. number of rows) of the image being readout and the level of binning in the image. 3.5 Exposure The exposure registers are used to determine the exposure of the sensor under all triggering conditions. A 40 bit register is used to hold the exposure value with each count equal to 25nsecs (i.e. 1/40MHz). Theoretical max exposure = 7.6 hours. In practice the max exposure will be limited by the amount of background radiation events and at warmer CCD temperatures the dark current of the device. Once an exposure has started it cannot be interrupted by another trigger. For example, if the camera is in external trigger mode, any trigger pulses applied to the camera during exposure will be ignored. An exposure may be aborted by setting the Abort bit the in trigger mode register. Once an exposure has been aborted the camera will run in the trigger mode selected by the trigger mode register.

15 EAGLEV_IM_V1.1_ doc 20/11/14 15 of Trigger Modes The trigger modes of the camera can be set using the internal trigger mode register. Bits are as outlined below: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Ext R/F Ext Trig en Reserved Reserved Abort Seq. trig Fix. frm en Snap Shot Note that bit 3 and bit 0 are self clearing bits Idle mode If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence trigger bit 2 is set = 0, then the camera will remain in idle mode i.e. no images will be read from the sensor Internal Trigger If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence trigger bit 2 is set = 1, then the camera will use an internal trigger to start the integration and readout of the sensor. The camera will run with continuous integration and readout of the sensor. Two modes of internal trigger are available Integrate Then Read (ITR) mode and Fixed Frame Rate (FFR) mode. If the Fixed frame rate bit 1 = 0 then ITR mode will be used to capture a continuous sequence of images. The camera will immediately trigger the start of a new integration period when the previous image readout has completed. If the Fixed frame rate bit 1 = 1 then the camera will generate an internal trigger signal at a user programmable frame rate.

16 EAGLEV_IM_V1.1_ doc 20/11/14 16 of External Trigger If the External trigger enable, bit 6, of the Trigger mode register is set = 1 then the camera will use an external trigger to start the integration and subsequent readout of the sensor. If the External Rising/Falling, bit 7, is set = 1 then the rising edge of an incoming trigger pulse is used to trigger the start of integration. Else the falling edge is used to trigger the start of integration, both scenarios are depicted in the diagram below. Notes: - It is not possible to overlap the readout & integration period for an externally triggered acquisition. - External trigger initiates the start of integration of the sensor. EXT. TRIG (+ve) EXT. TRIG (-ve) T pw T fp T s T rd T s Wait for trig Integration Readout Wait for trig Etc. TRIG OUT T int Figure 8: External Trigger timing Tfp = Frame period Tpw = Trigger pulse width, min width > one 40MHz clock period Ts = Delay from rising / falling edge of trigger to start of Integration (i.e. exposure) = ms (during this time the sensor is cleared in preparation for the start of exposure). Trd = readout time for 1 progressive frame Tint = integration time of sensor Jitter performance < 25ns (i.e. within one 40MHz clock period)

17 EAGLEV_IM_V1.1_ doc 20/11/14 17 of Snapshot trigger If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence trigger bit 2 is set = 0, then the camera will remain in idle mode i.e. no images will be read from the sensor. Setting bit 0 will trigger an acquisition from the camera. Note that bit 0 is self clearing Trigger Abort For all modes of the camera the Trigger Abort, bit 3, will abort the current exposure when it is set = 1. Video data will still be sent from the camera. The image sent will be for the duration of the exposure up until the abort command was received. Note that bit 3 of the trigger mode register is self-clearing. 3.7 ROI (Region of Interest) A region of interest within the main active region of may be defined. The ROI is setup using a bank of registers to control the X offset, the ROI width, the Y offset and the ROI height. These parameters are shown pictorially below. The user must ensure that X offset + ROI width is 2048 and similarly the Y offset + ROI height is Also ROI width and ROI height must be > pixels X W X = ROI X Offset Y Y = ROI Y Offset W = ROI width 2048 lines H ROI H = ROI height Figure 9: ROI size and offset It is possible to send a zero value to the ROI height, this will cause the camera to stop imaging even when a new value of greater than zero is issued. When/If this occurs the ROI height must be set to a value greater than zero and a Trigger Abort command will then need to be issued to reset the acquisition sequence. The camera will then trigger and readout as normal.

18 EAGLEV_IM_V1.1_ doc 20/11/14 18 of 34 It is recommended that when the ROI has been changed that the Host re-issues the command to set the appropriate trigger mode with the 'Trigger Abort' (bit 3) set in the trigger mode register. Further triggers/commands may be issued after this command. Note: The Image resolution must be set correctly in the frame grabber format file to ensure correct display of the data. 3.8 Binning In addition to standard 1 1 output, various levels of pixel binning may be programmed up to 64*64. Pixel binning is performed on the CCD and asymmetric binning combinations may be used e.g. (1 2); (2 1); (1 3); (3 1); (4 7) etc. For values of binning that do not divide evenly into the total number of pixels within the specified ROI in either the X or the Y direction; the division fraction will always be rounded up to give the total number of display pixels for a given bin level. e.g. XBIN = 7, gives 2048 / 7 = => 293 horizontal display pixels, note that the last column will not contain the full bin of 7 pixels but will contain a bin of the last 4 of the active pixels. Note: The Image resolution must be set correctly in the frame grabber format file to ensure correct display of the data. 3.9 Binning and ROI Binning and ROI may be active simultaneously. The ROI is determined on a single pixel basis after which Binning may be applied Pixel readout rate A pixel readout rate of either 2MHz or 75kHz may be selected. Using a pixel readout of 2MHz provides the shortest full frame readout time. Using a pixel readout rate of 75kHz provides the lowest readout noise for the camera Note that X (horizontal) binning is performed at 2MHz for both the 2MHz and the 75kHz mode Shutter control By default, the shutter is in the closed position. It can be programmed to be: permanently closed. permanently open. open for the duration of a valid exposure period. Additional delay registers may also be programmed to allow the shutter to be fully open before and fully closed after the exposure period, prior to the CCD being readout. This will prevent light falling on the sensor during readout and causing smear.

19 EAGLEV_IM_V1.1_ doc 20/11/14 19 of Test Pattern Image For all readout modes of the camera a test pattern image may be read from the camera instead of CCD data. The test image will consist of a fixed ramp pattern that will start with a value of 0 on the first pixel read from the camera and increment by one for each subsequent pixel read from the camera Unit Serial number The camera serial number may be read from the camera EPROM when the COMMS is enabled to the EPROM. Two bytes are used to hold the units serial number. Note that the serial number may also be read as part of the Manufacturers data (section 3.14) Manufacturers Data Manufacturer s data may be read from the camera s EPROM when the COMMS is enabled to the EPROM. 18 bytes are used to hold the manufacturers data that includes the unit serial number. Starting at address 0x bytes Serial number 3 bytes Build Date (DD/MM/YY) 5 bytes Build code (5 ASCII chars) 2 bytes ADC cal 0 C point 2 bytes ADC cal +40 C point 2 bytes DAC cal 0 C point 2 bytes DAC cal +40 C point ADC calibration data (Sensor Temperature) Two ADC values are held in the EPROM, each ADC value is held in 2bytes of the EPROM. The two ADC values represent the imaging sensor temperature at 0 degrees Celsius and +40 degrees Celsius. The ADC reading will vary linearly with temperature and the two calibration points may be used to define a straight line that can be used to convert the ADC reading to degrees Celsius. The temperature of the CCD is determined from a platinum resister attached to the CCD. The voltage across the resistor varies linearly with temperature. This voltage is read via an Analogue to Digital (ADC) converter. For calibration two ADC count values for the CCD temperature are determined during qualification testing for each camera i.e. at 0degC and at +40degC. These two points are stored in the cameras EPROM. A straight line graph can then be used to determine temperature for any given ADC count value. Straight line eqn. where the slope, Constant offset, Y = (M X) + C, becomes M = (Y1 - Y2) / (X1 - X2) -- two known points from calibration C = Y2 M (X2) For any ADC value, ADC temp ( C) = M (ADC counts) + C

20 EAGLEV_IM_V1.1_ doc 20/11/14 20 of 34 For example using the calibration values; ADC cal. 0 C = 1226 counts, ADC cal. +40 C = 788 counts Temperature degc ROIC ADC count vs Temp y = x degC ADC count value ROIC ADC +15degC Linear (ROIC ADC) Figure 10: CCD temperature as a function of ADC value. In the above example a reading from the ADC of 1062 counts would equate to +15 C DAC calibration data A Digital to Analogue converter (DAC) is used to produce a voltage for the set point of the TEC control loop. Two values are determined for 0 C and +40 C for each camera during qualification testing and stored in the cameras EPROM. The relationship of DAC counts to set point temperature is linear and therefore a straight line graph can be used to determine the set point temperature from the DAC count value.

21 EAGLEV_IM_V1.1_ doc 20/11/14 21 of 34 4 SERIAL COMMUNICATION (CAMERALINK INTERFACE) 4.1 Overview For version 2.3 of the Micro firmware, the Power on default settings for camera serial port are: baud - 1 start bit - 8 data bits - 1 stop bit UART message format from Host to camera Command Data 1 Data 2... Data n ETX Chk_Sum The first Byte is the command to the Microcontroller in the camera, following bytes contain data required by the command, the End of Transmission (ETX) byte terminates the command. 0x50 is always used to terminate the command. An additional check sum byte may also be required to be sent by the host if check sum mode is enabled. UART message format from camera to Host Data 1 Data 2... Data n ETX Chk_Sum All or none of the above bytes may be sent in response to commands from the host depending on the commands sent by the host. An optional mode of operation is included in the firmware for command acknowledge. Once enabled the camera will respond to all commands send by the host. After the camera has received and processed the command from the host, a single command acknowledge byte will be sent at the ETX i.e. should the host command require data to be sent from the camera then the ETX byte will be sent at the end of the requested data. Another optional mode of operation is included in the firmware is for check sum operation, this mode should only be used when the command acknowledge mode is enabled. Once the check sum mode is enabled the camera will only act upon commands that are received with the correct check sum byte sent at the end of the command packet. Note that if the check sum feature is not enabled check sum bytes may still be sent at the end of a command packet, the command will be processed and the check sum will be ignored. The check sum byte should be the result of the Exclusive OR of all bytes in the Host command packet including the ETX byte. When check sum mode is enabled data returned from the camera will include an echo of the checksum from the host command By default the camera will boot up with both command acknowledge and check sum operation disabled. It is intended that the camera be operated from a higher level perspective whereby complete UART messages or groups of UART messages are used to achieve required camera functionality. Bits in registers that have not been identified in the documentation should be considered reserved and should not be accessed.

22 EAGLEV_IM_V1.1_ doc 20/11/14 22 of 34 Once a command has been received by the camera all subsequent commands from the host will be ignored until the command has been processed. It is recommend that both command acknowledge and check sum operation be enabled at power up. 4.2 ETX/ERROR codes Error codes will be sent as ETX characters by the camera in response to commands that have failed. 0x50 ETX Command acknowledge, command processed successfully. 0x51 0x52 0x53 ETX_SER_TIMEOUT ETX_CK_SUM_ERR ETX_I2C_ERR Partial command packet received, camera timed out waiting for end of packet. Command not processed Check sum transmitted by host did not match that calculated for the packet. Command not processed An I2C command has been received from the Host but failed internally in the camera. 0x54 ETX_UNKNOWN_CMD Data was detected on serial line, command not recognized 0x55 ETX_DONE_LOW Host Command to access the camera EPROM successfully received by camera but not processed as EPROM is busy i.e. FPGA trying to boot.

23 EAGLEV_IM_V1.1_ doc 20/11/14 23 of Set Commands Set Command Serial Packet Comments Micro RESET 0x55 0x99 0x66 0x11 0x50 0xEB Will trap Micro causing watchdog and reset of firmware. The camera will give no response to this command Set system state 0x4F 0xYY 0x50 8 bit value YY Bit 7 = Reserved Bit 6 = 1 check sum mode enabled Bit 5 = Reserved Bit 4 = 1 to enable command ACK Bit 3..2 = Reserved Bit 2 = 1 if FPGA booted ok Bit 1 = 0 to Hold FPGA in RESET Bit 0 = 1 to enable comms to FPGA EPROM Set FPGA CTRL reg 0x53 0xE0 0x02 0x00 0xYY 0x50 YY Bit 7 = 0 to enable high pre amp gain i.e. ~1e/ADU (Default=0) YY Bit 6,5,4,3,2 = reserved (Default=0) YY Bit 1 = 1 to reset the temperature trip flag, self-clearing bit (Default=0) YY Bit 0 = 1 to enable TEC (Default=0) 40 bit value, 5 separate commands, 0x53 0xE0 0x02 0xDC 0xY1 0x50 1 count = 1 40MHz period = 25nsecs Set Frame rate 0x53 0xE0 0x02 0xDD 0xY2 0x50 Y1 = MSB of 5 byte word (Internal trigger, 0x53 0xE0 0x02 0xDE 0xY3 0x50 : fixed rate only) 0x53 0xE0 0x02 0xDF 0xY4 0x50 Y5 = LSB of 5 byte word; 0x53 0xE0 0x02 0xE0 0xY5 0x50 Frame rate updated on LSB write Set Exposure Set Trig Mode 0x53 0xE0 0x02 0xED 0xY1 0x50 0x53 0xE0 0x02 0xEE 0xY2 0x50 0x53 0xE0 0x02 0xEF 0xY3 0x50 0x53 0xE0 0x02 0xF0 0xY4 0x50 0x53 0xE0 0x02 0xF1 0xY5 0x50 0x53 0xE0 0x02 0xD4 0xYY 0x50 40 bit value, 5 separate commands, 1count = 1 40MHz period = 25nsecs Y1 = MSB of 5 byte word ::: Y5 = LSB of 5 byte word; Frame rate updated on LSB write YY Bit 7 = 1 to enable rising edge, = 0 falling edge Ext trigger (Default=1) YY Bit 6 = 1 to enable External trigger (Default=0) YY Bit 3 = 1 to Abort current exposure, self-clearing bit (Default=0) YY Bit 2 = 1 to start continuous seq'., 0 to stop (Default=1) YY Bit 1 = 1 to enable Fixed frame rate, 0 for continuous ITR (Default=0) YY Bit 0 = 1 for snapshot, self clearing bit (Default=0)

24 EAGLEV_IM_V1.1_ doc 20/11/14 24 of bit DAC value, LSB = LL byte, Lower nibble of MM = MSBs Set TEC set point Set ROI X Size Set ROI X offset Set ROI Y Size Set ROI Y offset Set X Binning Set Y Binning Set pixel readout clock Set shutter control Set shutter open delay 0x53 0xE0 0x02 0x03 0xMM 0x50 0x53 0xE0 0x02 0x04 0xLL 0x50 0x53 0xE0 0x02 0xB4 0xMM 0x50 0x53 0xE0 0x02 0xB5 0xLL 0x50 0x53 0xE0 0x02 0xB6 0xMM 0x50 0x53 0xE0 0x02 0xB7 0xLL 0x50 0x53 0xE0 0x02 0xB8 0xMM 0x50 0x53 0xE0 0x02 0xB9 0xLL 0x50 0x53 0xE0 0x02 0xBA 0xMM 0x50 0x53 0xE0 0x02 0xBB 0xLL 0x50 0x53 0xE0 0x02 0xA1 0xYY 0x50 0x53 0xE0 0x02 0xA2 0xYY 0x50 0x53 0xE0 0x02 0xA3 0xY1 0x50 0x53 0xE0 0x02 0xA4 0xY2 0x50 0x53 0xE0 0x02 0xA5 0xYY 0x50 0x53 0xE0 0x02 0xA6 0xYY 0x50 Reg 0x03, bits 3..0 = set point bits Reg 0x04, bits 7..0 = set point bits bit value to be converted to temperature (see "Get manufacturers Data" section 3.14) 12bit value MM bits 3..0 = size bits LL bits 7..0 = size bits 7..0 Data updated on write to LSBs 12bit value MM bits 7..0 = offset bits LL bits 7..0 = offset bits 7..0 Data updated on write to LSBs 12bit value MM bits 3..0 = size bits LL bits 7..0 = size bits 7..0 Data updated on write to LSBs 12bit value MM bits 3..0 = size bits LL bits 7..0 = size bits 7..0 Data updated on write to LSBs YY Default = 0x00 YY = 0x00, X binning 1 YY = 0x01, X binning 2 : YY = 0x1F, X binning 32 YY = 0x3F, X binning 64 YY Default = 0x00 YY = 0x00, Y binning 1 YY = 0x01, Y binning 2 : YY = 0x1F, Y binning 32 YY = 0x3F, Y binning 64 2MHz Y1=0x02,Y2=0x02 (Default) 75kHz Y1=0x43, Y2=0x80 YY Default = 0x00 YY = 0x00, shutter always closed YY = 0x01, shutter always open YY = 0x02, shutter open for duration exposure time 8 bit value, 1count = 1/(80MHz/2^17) period = msecs YY Default = 0x0C = 19.66ms

25 EAGLEV_IM_V1.1_ doc 20/11/14 25 of 34 Set shutter closed delay Set readout mode 0x53 0xE0 0x02 0xA7 0xYY 0x50 0x53 0xE0 0x02 0xF7 0xYY 0x50 8 bit value, 1count = 1/(80MHz/2^17) period = msecs YY Default = 0x1E = 49.15ms YY = 0x01, normal readout (Default) YY = 0x04, Test pattern enabled

26 EAGLEV_IM_V1.1_ doc 20/11/14 26 of Query Commands Query Send Serial Packet Command Get system status Get FPGA Status Get Frame rate (Internal trigger, fixed rate only) Get Exposure Get Trig Mode 0x49 0x50 0x53 0xE0 0x01 0x00 0x50 0x53 0xE0 0x01 0xDC 0x50 0x53 0xE0 0x01 0xDD 0x50 0x53 0xE0 0x01 0xDE 0x50 0x53 0xE0 0x01 0xDF 0x50 0x53 0xE0 0x01 0xE0 0x50 0x53 0xE0 0x01 0xED 0x50 0x53 0xE0 0x01 0xEE 0x50 0x53 0xE0 0x01 0xEF 0x50 0x53 0xE0 0x01 0xF0 0x50 0x53 0xE0 0x01 0xF1 0x50 0x53 0xE0 0x01 0xD4 0x50 Comments 1 byte returned from camera Bit 7 = Reserved Bit 6 = 1 check sum mode enabled Bit 5 = Reserved Bit 4 = 1 to enable command ACK Bit 3 = Reserved Bit 2 = 1 if FPGA booted ok Bit 1 = 0 to Hold FPGA in RESET Bit 0 = 1 to enable comms to FPGA EPROM 1 byte returned from camera Bit 7 = 0 to enable high pre amp gain i.e. ~1e/ADU (Default=0) Bit 6,5,4,3,2 = reserved (Default=0) Bit 1 = 1 OverTemp >80 C tripped (Default=0) Bit 0 = 1 to enable TEC (Default=0) 40 bit value, 5 8bit internal registers DC to E0 read, register E0 contains the LSBs 1 count = 1 40MHz period = 25nsecs 40 bit value, 5 8bit internal registers ED to F1 read, register F1 contains the LSBs 1 count = 1 40MHz period = 25nsecs 1 byte returned; Bit 7 = 1 rising edge trig enabled Bit 6 = 1 External trigger enabled Bit 5,4 = reserved Bit 3 = Always read as '0' Bit 2 = 1 continuous seq'., enabled Bit 1 = 1 FFR enabled, 0 for continuous ITR Bit 0 = Always read as '0'

27 EAGLEV_IM_V1.1_ doc 20/11/14 27 of 34 Get TEC set point Get ROI X Size Get ROI X offset Get ROI Y Size Get ROI Y offset Get X Binning Get Y Binning Get pixel readout clock Get shutter control status Get shutter open delay 0x53 0xE0 0x01 0x03 0x50 0x53 0xE0 0x01 0x04 0x50 0x53 0xE0 0x01 0xB4 0x50 0x53 0xE0 0x01 0xB5 0x50 0x53 0xE0 0x01 0xB6 0x50 0x53 0xE0 0x01 0xB7 0x50 0x53 0xE0 0x01 0xB8 0x50 0x53 0xE0 0x01 0xB9 0x50 0x53 0xE0 0x01 0xBA 0x50 0x53 0xE0 0x01 0xBB 0x50 0x53 0xE0 0x01 0xA1 0x50 0x53 0xE0 0x01 0xA2 0x50 0x53 0xE0 0x01 0xA3 0x50 0x53 0xE0 0x01 0xA4 0x50 0x53 0xE0 0x01 0xA5 0x50 0x53 0xE0 0x02 0xA6 0xYY 0x50 12 bit DAC value, Reg 0x03, bits 3..0 = set point bits Reg 0x04, bits 7..0 = set point bits bit value to be converted to temperature (see " Get manufacturers Data" section 3.14) 2 bytes returned; 12bit value 1 st byte (B4) bits 3..0 = size bits nd byte (B5) bits 7..0 = size bits bytes returned; 12bit value 1 st byte (B6) bits 3..0 = offset bits nd byte (B7) bits 7..0 = offset bits bytes returned; 12bit value 1 st byte (B8) bits 3..0 = size bits nd byte (B9) bits 7..0 = size bits bytes returned; 12bit value 1 st byte (BA) bits 3..0 = offset bits nd byte (BB) bits 7..0 = offset bits byte returned; = 0x00, X binning 1 (Default) = 0x01, X binning 2 : = 0x1F, X binning 32 = 0x3F, X binning 64 1 byte returned; = 0x00, Y binning 1 (Default) = 0x01, Y binning 2 : = 0x1F, Y binning 32 = 0x3F, Y binning 64 2 bytes returned; 1 st byte from register 0xA3 => Y1 2 nd byte from register 0xA4 => Y2 2MHz Y1=0x02,Y2=0x02 (Default) 75kHz Y1=0x43, Y2=0x80 1 byte returned; = 0x00, shutter closed (Default) = 0x01, shutter open = 0x02, shutter open for duration exposure time 1 byte returned; 8 bit value, 1count = 1/(80MHz/2^17) period = msecs Default = 0x0C = 19.66ms

28 EAGLEV_IM_V1.1_ doc 20/11/14 28 of 34 Get shutter closed delay Get readout mode Get PCB temperature Get CCD silicon temperature Get Micro version Get FPGA version Get Unit Serial Number Get manufacturers Data 0x53 0xE0 0x02 0xA7 0xYY 0x50 0x53 0xE0 0x01 0xF7 0x50 0x53 0xE0 0x02 0x70 0x00 0x50 0x53 0xE0 0x02 0x71 0x00 0x50 0x53 0xE0 0x02 0x6E 0x00 0x50 0x53 0xE0 0x02 0x6F 0x00 0x50 0x56 0x50 0x53 0xE0 0x01 0x7E 0x50 0x53 0xE0 0x01 0x7F 0x50 0x53 0xAE 0x05 0x01 0x00 0x00 0x02 0x00 0x50 0x53 0xAF 0x02 0x50 0x53 0xAE 0x05 0x01 0x00 0x00 0x02 0x00 0x50 0x53 0xAF 0x12 0x50 1 byte returned; 8 bit value, 1count = 1/(80MHz/2^17) period = msecs Default = 0x1E = 49.15ms 1 byte returned; = 0x01, normal readout (Default) = 0x04, Test pattern enabled 2 bytes returned for 12 bit signed value 1 st byte => bits 3..0 = MSBs nd byte => bits 7..0 = LSBs 7..0 Divide 12 bit value by 16 to get temp. 2 bytes returned, MSB followed by LSB, indicate sensor temperature reading. Conversion formula to C see section bytes returned. 1 st byte Major version 2 nd byte Minor version. Set address 7E (Major Version Byte) Read address 7E, 1 byte Set address 7F (Minor Version Byte) Read address 7F, 1 byte NOTE: System state must have bit 0 set = 1 to enable comms to FPGA EPROM, when comms to FPGA EPROM not required recommend system state bit 0 = 0. 2 bytes returned 1 st byte is the LSB 2 nd is the MSB NOTE: System state must have bit 0 set = 1 to enable comms to FPGA EPROM, when comms to FPGA EPROM not required recommend system state bit 0 = 0. Get 18 bytes from cameras EPROM. For 2 byte values 1st byte returned is the LSB. Starting at address 0x bytes Serial number 3 bytes Build Date (DD/MM/YY) 5 bytes Build code (5 ASCII chars) 2 bytes ADC cal 0 C point 2 bytes ADC cal +40 C point 2 bytes DAC cal 0 C point 2 bytes DAC cal +40 C point

29 EAGLEV_IM_V1.1_ doc 20/11/14 29 of Serial Command Examples NOTE: Assume that Command Ack and Check sum mode are enabled unless otherwise stated Set System status (Enable Command Ack and Check sum mode) From power up Command TX bytes (to camera) RX d bytes (From camera) Set System status (=0x56) 0x4F 0x56 0x50 0x49 0x50 0x49 (ack + chk_sum) YY Bit 7= 0 - reserved YY Bit 6= 1 to enable check sum mode YY Bit 5= 0 to enable external comms YY Bit 4 = 1 to enable command ack YY Bit 3 = 0 - reserved YY Bit 2 = 1 - reserved YY Bit 1 = 1 FPGA NOT in RESET YY Bit 0 = 0 to disable comms to FPGA EPROM Get System Status Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x49 0x50 0x19 0x56 0x50 0x19 (status = 0x56) Get Micro version Command TX bytes (to camera) RX d bytes (From camera) Get Micro version 0x56 0x50 0x06 0x02 0x06 0x50 0x06 (V2.6) Get FPGA version Command TX bytes (to camera) RX d bytes (From camera) 0x53 0xE0 0x01 0x7E 0x50 0x9C 0x50 0x9C 0xE3 0x01 0x50 0xE3 Get FPGA version 0x53 0xE0 0x01 0x7F 0x50 0x50 0x9C 0x9D 0xE3 0x0F 0x50 0xE3 (v1.15) Reset camera Command TX bytes (to camera) RX d bytes (From camera) Micro Reset 0x55 0x99 0x66 0x11 0x50 0xEB None Set system State to Hold FPGA in RST -- Poll camera with this command every 500msecs until Rx bytes received 0x4F 0x51 0x50 0x4E (0x50 0x4E) received when Micro has re-booted successfully

30 EAGLEV_IM_V1.1_ doc 20/11/14 30 of 34 Set system State to boot the FPGA Get system status -- Poll the camera with this command every 500ms until bit 2 of the received status indicates that the FPGA has booted ok. 0x4F 0x52 0x50 0x4D 0x49 0x50 0x19 0x50 0x4D (0x52 0x50 0x19) -- FPGA not booted (0x56 0x50 0x19) -- FPGA booted ok Read Sensor PCB temperature Command TX bytes (to camera) RX d bytes (From camera) 0x53 0xE0 0x02 0x70 0x00 0x50 0x91 0x50 0x91 0xE3 0x01 0x50 0xE3 Get PCB temperature 0x53 0xE0 0x02 0x71 0x00 0x50 0x90 0x50 0x90 0xE3 0x93 0x50 0xE3 (25.18degC) 4.6 Serial Command Error Examples NOTE: Assume that Command Ack and Check sum mode are enabled unless otherwise stated Missing or wrong checksum Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x49 0x50 0x52 0x19 Camera has received a partial command but not received the correct check sum and therefore responds with an error code of 0x52 + sends the check sum byte that it had been expecting. The command is ignored Partial host command with missing data/etx/checksum Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x49 0x51 0x19 Camera has received a partial command but not received expected data or the ETX character. Camera responds with error code 0x51 + sends the check sum byte that it had been expecting. The command is ignored Corrupt/Unknown host command Command TX bytes (to camera) RX d bytes (From camera) Get system status 0x48 0x50 0x19 0x54 0x48 1st byte is corrupt and the camera has received an unknown command. Camera responds with error code 0x54 + sends the check sum byte that it had been expecting. The command is ignored.

31 EAGLEV_IM_V1.1_ doc 20/11/14 31 of 34 - FPGA FIRMWARE UPLOAD

32 EAGLEV_IM_V1.1_ doc 20/11/14 32 of 34 CAMERA EPROM The camera EPROM is divided into 15 sectors with address spaces as outlined below. Note that each address points to a 16bit word. /* Sector Structure... Sector Kwords words start end start end FFF FFF FFF FFF FFF FFF FFF FFF FFFF FFF FFFF FFF FFFF FFF FFFF SECTOR 1 - is used for Manufacture specific data i.e. serial number etc. SECTORS 2-15 are used to hold the FPGA configuration information. To program a new FPGA configuration 1. Sectors 2-15 must be erased 2. a new bit file must be uploaded to Sectors 2-15 Note that SECTOR 1 must not be ERASED as this contains detailed data about the camera. SECTOR ERASE The following command is used to erase a sector. SECTOR xx ERASE - 0x53 0xAE 0x05 0x04 0xAA 0xBB 0xCC 0x00 0x50 Where the Hex Number AABBCC represents an address in the sector to be erased. After the SECTOR erase command has been issued a small delay is required for the ERASE to take place. Successful erase can be determined by polling the sector with the following command. 0x53 0xAF 0x01 0x50 If a value of 0xFF is returned the sector erase is complete.

33 EAGLEV_IM_V1.1_ doc 20/11/14 33 of 34 Example Sector ERASEs SECTOR 2 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x10 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 3 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x20 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 4 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x30 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 5 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x40 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 6 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x50 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 7 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x60 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 8 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x70 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 9 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 10 ERASE - 0x53 0xAE 0x05 0x04 0x01 0x00 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 11 ERASE - 0x53 0xAE 0x05 0x04 0x01 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 12 ERASE - 0x53 0xAE 0x05 0x04 0x02 0x00 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 13 ERASE - 0x53 0xAE 0x05 0x04 0x02 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 14 ERASE - 0x53 0xAE 0x05 0x04 0x03 0x00 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR 15 ERASE - 0x53 0xAE 0x05 0x04 0x03 0x80 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received) SECTOR PROGRAMMING Bursts of 32 DATA bytes (sixteen 16bit words) should be sent to the EPROM using a single command, the EPROM will auto increment the addresses. Burst write command 0x53 0xAE 0x25 0x02 0xAA 0xBB 0xCC 0xN1 0xN2 0xN3...0xN32 0x00 0x50 The address of the burst write is given by AABBCC, 32 DATA bytes as read from bit file are sent N1-N32 Address AABBCC should start at the base address of sector 2 i.e. 0x and increment by 16 for every burst command until the end of file. At the end of file the last burst may not require 32bytes due to the file size, if this is the case the last 32 should be padded out to 32. Data in padding ignored.

34 EAGLEV_IM_V1.1_ doc 20/11/14 34 of 34 Notes: It is recommended to operate the camera with Command Ack. Waiting for a command Ack will ensure burst writes have taken place before moving to the next burst write. The bit stream contains a check sum that is used by the FPGA during power up. If data is corrupted during upload the FPGA will not boot. Verification that FPGA has successfully booted can be done by reading the FPGA version number. Example command list Command Enable FPGA programming Erase EEPROM sector 2 Confirm Sector 2 erase (by reading LSByte) Erase EEPROM sectors 3-15 and confirm erase after each sector. Burst write 32 bytes of bit file Multiple burst writes of 32 bytes of bit file Enable External Comms Get FPGA version Disable External Comms TX bytes (to camera) 0x4F 0x53 0x50 0x53 0xAE 0x05 0x04 0x00 0x10 0x00 0x00 0x50 0x53 0xAF 0x01 0x50 As above with relevant sector address 0x53 0xAE 0x25 0x02 0x00 0x10 0x00 0xN1 0xN2 0xN3...0xN32 0x00 0x50 0x53 0xAE 0x25 0x02 0xAA 0xBB 0xCC 0xN1 0xN2 0xN3...0xN32 0x00 0x50 0x4f 0x02 0x50 0x53 0xE0 0x01 0x7E 0x50 0x53 0xE0 0x01 0x7F 0x50 RX d bytes (from camera) 0x50 0x50 0xFF 0x50 As above 0x50 0x50 0x50 0x50 0x01 0x50 0x50 0x0D 0x50 Comments Enable cmd ack, Enable chk sum, Hold FPGA in reset, enable EPROM comms Poll until 0xFF is returned Poll after each sector is erased until 0xFF is returned 1st burst starting at Sector 2 address. Address 0xAABBCC starts at sector 2 base address and needs to be incremented by 16 for each successive burst until end of file. FPGA will now boot with new firmware, need to delay approx. 500msec Version x4F 0x52 0x50 0x50 Disable External Comms