Lab 2: Common Base Common Collector Design Exercise

CSUS EEE 109 Lab - Section 01 Lab 2: Common Base Common Collector Design Exercise Author: Bogdan Pishtoy / Lab Partner: Roman Vermenchuk Lab Report due March 26 th Lab Instructor: Dr. Kevin Geoghegan 2016-03-25 Page 1 of 31

TABLE OF CONTENTS ABSTRACT... 3 EQUIPMENT LIST... 3 PART I: PRELIMINARY CALCULATIONS... 4 STEP 1: VOLTAGE GAIN EXPRESSION... 4 STEP 2: CIRCUIT DESIGN... 7 PART II: SPICE SIMULATIONS... 14 STEP 3: BIAS POINT ANALYSIS... 14 STEP 4: GAIN AND INPUT RESISTANCE SIMULATION MEASUREMENT... 14 STEP 5: MAXIMUM OUTPUT VOLTAGE SWING... 15 STEP 6: OUTPUT RESISTANCE CALCULATION... 16 STEP 7: DESIGN SPECIFICATION COMPARISON... 17 PART III: LABORATORY EXPERIMENT... 19 STEP 8: BIAS CONDITIONS VERIFICATION... 19 STEP 9: SMALL-SIGNAL GAIN MEASUREMENT... 20 STEP 10: MAXIMUM OUTPUT SWING MEASUREMENT... 21 STEP 11: INPUT RESISTANCE... 23 STEP 12: SPECIFICATIONS CHECK... 24 STEP 13: REPLACING THE BIAS NETWORK... 25 CONCLUSION... 27 ITEM 1:... 27 ITEM 2:... 28 ITEM 3:... 28 ITEM 5:... 29 ITEM 6:... 30 APPENDIX A: INPUT AND OUTPUT RESISTANCE MEASUREMENTS... 31 2016-03-25 Page 2 of 31

Abstract The purpose of this laboratory assignment is to familiarize the student with amplifier design and the process behind it. More specifically, a common-base current buffer amplifier, common-collector amplifier, and a diode connected common-emitter amplifier will be analyzed at certain portions of the laboratory. One important aspect of amplifier design is making approximations to limit the number of unknowns while designing. In this laboratory, specifications were given bounding the student to certain parameters. Reasonable approximations had to be made to achieve the given specifications, while using circuit analysis techniques to reach the final design. The design process is initiated in the hand calculations section of the report, tested using simulation software, and verified in the laboratory experiment. The report touches on what it means to make reasonable approximations and the logic, the measurements, and the technique behind it. Equipment List Description Other Specifications 1.1 OrCAD PSPICE Lite Software Version 9.2 1.2 MS Office Suite Version 2013 1.3 Digital Multi Meter (DMM) Agilent 34450a 1.4 Waveform Generator Agilent 33120 1.5 Triple Output DC Power Supply Agilent E3631A Power Supply 1.6 Digital Oscilloscope Tektronix DPO 3014, 4 channel 1.7 Voltage Probes Tektronix Tek P6139A, 500 MHz, 8.0pF, 10 MΩ, 10x 1.8 Analog Discovery Kit Dual Channel Oscilloscope & Function Generator 1.9 Common-Emitter BJT 2N3904 1.10 Common Collector BJT 2N3904 1.11 Breadboard Jameco breadboard with jumper wires 1.12 Resistors Further specified in report 1.13 Capacitors Further specified in report 2016-03-25 Page 3 of 31

Part I: Preliminary Calculations Step 1: Voltage Gain Expression A typical common-base amplifier circuit with a common-collector amplifier attached at the second stage is displayed in Figure 1. This circuit was used for deriving an expression for the voltage gain of the CB stage along with hand calculations for designing of the circuit in reference to given specifications. Figure 1: Common Base Common Collector Amplifier In this step, we will be deriving the expression for the voltage gain of the CB stage using hand calculations as seen in Figures 2a and Figure 2b. 2016-03-25 Page 4 of 31

Figure 2a: Hand Calculation for Step 1 2016-03-25 Page 5 of 31

Figure 2b: Hand Calculation for Step 1 From the hand calculations, the expression for the voltage gain of the CB stage derived is: V C1 V in = R C1 R A + [R E1 //(r e + R BB β )] R E1 R E1 + r e + R BB β (1.1) 2016-03-25 Page 6 of 31

When recognizing the input resistance in the denominator of the right side of Equation 1.1, the alternate form of the equation is then, V C1 V in = R C1 R in R E1 R E1 + r e + R BB β (1.2) Step 2: Circuit Design In this step, we were to design the circuit by selecting proper values for R C1, R E1, R A, and R E2. The design was constrained by standard resistor values and the following specifications seen in Figure 3. Figure 3: Design Specifications for CB-CC Amplifier We can breakdown the calculation into two stages: the CB stage and CC stage. The CB stage coincides with R A, R C1, and R E1 and the input. The latter stage interacts primarily with R E2 and the output. Simply by making use of the specifications we can solve for R A by, R A = 0.66R in = 0.66 75 = 49.5 Ω Rounding R A, to a standard resistor value we get R A = 51 Ω. And now recognizing the input resistance of the CB stage has the following equation, with two unknowns presently. R in = R A + [R E1 //(r e1 + R BB1 )] (2.1) β Firstly, we can solve for R BB1 from the bias network with a voltage divider equation followed by a parallel combination of resistors R BN1 and R BN2. The assumption made in the calculation is ignoring of resistors R BN3 and R P (the potentiometer). Since their series combination is much greater than either R BN1 or R BN2, it is safe to assume this. The hand calculations for the resistors are seen in Figure 4. 2016-03-25 Page 7 of 31

Recalling two more equations can lead us to narrowing down of the unknowns and solving for R E1. These equations are, And, r e1 = V T I E1 (2.2) I E1 = V E1 V EE R E1 = 0 + 5 R E1 = 5 R E1 (2.2.2) Plugging into Equation 2.2 and approximating V T = 25mV, gives us the following relationship: 2016-03-25 Page 8 of 31

r e1 = 0.005R E1 (2.3) Now plugging this back into Equation 2.1 leaves us with only one unknown: R E1. The hand calculations in Figure 4 demonstrate the acquiring of the value in the form of a quadratic equation. Figure 5: Calculating R E1 Finding R E1 enables us to find the DC bias emitter current of the CB stage. The calculation in demonstrated in Figure 6. Also, in Figure 6 the calculation of R C1 is shown where the alternate form of Equation 1.1 is used along with the specified gain of 20 V/V is used. 2016-03-25 Page 9 of 31

Figure 6: Calculation of I E1 and R C1 A similar route can be used for calculating R E2. Recognizing the output resistance equation in the form of R o = R E2 //(r e2 + R BEQ β ) (2.4) Where R BEQ, is the equivalent resistance to ground seen looking into the base from the emitter side. It is simply the series combination of R C1 and 1k resistor, since we are using r o1 =. Figure 6 also shows that R BEQ = 2.5 kω. 2016-03-25 Page 10 of 31

And now following the strategy of substituting r e2 with some multiple of R E2. Again, the relationships are as follows: r e2 = V T I E2 (2.5) I E2 = V out + 5 R E2 (2.6) Solving for V out, is seen in Figure 7 below. However, an assumption had to be made to solve for it. The assumption of V B2 = V C1 is used because the current at the base of Q2 is insignificant in comparison with the collector and emitter current at the same stage. This is due to the relationship i B = i C/β, which gives us the safe assumption of a smaller order of magnitude current leading to an insignificant voltage drop from V C1 to V B2. And we also know that V out is only separated from V B2 by 0.7 V (the voltage drop across the base-to-emitter region). 2016-03-25 Page 11 of 31

Figure 7: Calculating R E2 Once again, we ve substituted r e2 to solve for R E2 with a quadratic equation. The relationship was as follows, r e2 = 0.0036R E2 (2.7) 2016-03-25 Page 12 of 31

This finishes our design process, and the summary of the calculated resistor values along with the DC bias values are summarized in Table 1 below. Table 1: Summary of Design Process Calculated Resistor Values Calculated Bias Conditions R A 51 Ω I C1 1.515 ma R C1 1.5 kω I E1 1.515 ma R E1 3.3 kω V C1 2.727 V R E2 7.5 kω V OUT 2.027 V R BN1 6.14 kω 860 Ω R BB1 2016-03-25 Page 13 of 31

Part II: SPICE Simulations Step 3: Bias Point Analysis In this step, we entered the designed circuit with reference to Figure 1 and the values from Table 1. We are omitting the signal source for now. Once the circuit is built, we are to adjust the value of V BB until V E1 is less than 2 mv. From Figure 8, we can see that our calculated bias conditions in Table 1, match very well with the bias calculations of SPICE. The slight differences come from SPICE using different values for the threshold voltage and for β. Figure 8: Bias Point Analysis without Signal Source Step 4: Gain and Input Resistance Simulation Measurement Adding the source signal with its characteristic impedance of 50 Ohms, we proceeded to find the input resistance along with the gain of both stages. An AC analysis was used to obtain the low-frequency voltage gain as seen in Figure 9. The gain of 19.797 V/V found in Figure 9 is safely in the midband range and is really close to the specification value of 20 V/V. 2016-03-25 Page 14 of 31

Gain = 19.797 V/V Figure 9: AC Analysis V out/v in vs Frequency The input resistance was found using a test voltage signal with a deliberate resistance (R X) as the equipment. This is known as the voltage divider method which relates the input and output resistances to the test equipment as such, R in = R X V TEST V IN 1 (4.1) A further description of the voltage divider method and sample calculations can be seen in Appendix A. A value of R X = 50 Ω was chosen for simplicity. Plotting a graph of V TEST/V IN, and taking the midband value of the plot is the proper way of calculating the input resistance. Figure 10 demonstrates this. Gain = 1.673 V/V Figure 10: AC Analysis V TEST/V IN for Calculating R IN Plugging in the found gain from Figure 10 into Equation 4.1, we get R IN = 74.28 Ω. This is nearly the same value as the specifications provided and is definitely in the ± 10% range as specified. Step 5: Maximum Output Voltage Swing In the step, a transient analysis was performed on the same circuit from Step 4. We were to adjust the amplitude of the sinusoidal source and see the effect on the transient response. After adjusting the step size and run time, the transient response looked better. 2016-03-25 Page 15 of 31

As seen in Figure 11 below, the maximum output voltage swing was V OUTMAX = 4.45 V p-p. V MAX = 4.035 V V OUTMAX = 4.450 V p-p V MIN = -414.391 mv Figure 11: Transient Response (V OUT vs Time) Displaying Maximum Output Voltage Swing In comparison with the specifications, a larger output voltage swing of 1.2 V p-p is acheived. But, we are still in the context of the specification because the minimum output voltage swing is to be 3.2 V p-p. Step 6: Output Resistance Calculation In this step we are finding the output resistance of the circuit. The method that is employed is the voltage divider method further discussed in the Appendix. As seen in Figure 12, the test voltage, V TEST, and a known deliberate resistor, R S1, is added into the output node to calculate the series resistance. Figure 12: Setup of Test Signal for finding R out Now, the output resistance can be found using the following equation R out = R X V TEST V OUT 1 (6.1) 2016-03-25 Page 16 of 31

After setting up the test equipment for finding the output resistance, a plot of V TEST/V OUT is now achievable. From Figure 13 below, one can see the gain achieved by the test signal. Plugging into Equation 6.1 yields R OUT = 20.01 Ω. Gain = 3.499 V/V Figure 13: AC Analysis V TEST/V OUT for Calculating R OUT The results of this step show that we are still in the specification boundary of R OUT 50 Ω. Step 7: Design Specification Comparison After designing the circuit and simulating it, a comparison can be made between the specification table from Figure 3 and the simulated values from PSPICE. Table 2 demonstrates that each design specification has been met and that the calculated values from Steps 1 and 2 hold valid. Table 2: Specifications vs PSPICE values Parameter Type R IN V OUT/V IN (V/V) V OUTMAX R OUT Specification Parameter 75 Ω ± 10% 20 ± 10% 3.2 V p-p 50 Ω Simulated PSPICE Parameter 74.28 19.797 4.45 V p-p 20.02 Ω The final design is displayed in Figure 14. The Laboratory Experiment is ready to be taken on now. 2016-03-25 Page 17 of 31

Figure 14: CB-CC Amplifier Designed Circuit 2016-03-25 Page 18 of 31

Part III: Laboratory Experiment Step 8: Bias Conditions Verification In this step, we assembled the circuit from our final design, as recorded in Step 7, but did not connect the signal generator yet. We applied power and proceeded to measure the bias conditions. We then adjusted the potentiometer, R p, in the bias network as seen in Figure 15 below. We adjusted it until V B1 was approximately 0.685 V, yielding V E1 = 1 mv as measured with the Digital Multi Meter. Thus, this makes the emitter at Q1 nearly a virtual ground. Figure 15: Bias Network leading to the base of Q1 Our measurements are summarized in Table 3 below. The measured resistor values were a nearly perfect match, matching with less than 1% difference. The bias currents, collector voltage, and output voltage were reasonably close to the calculated values of our design, with differences ranging up to 7.4%. Some reasons for the differences are not well-enough matched transistors, noise in measurements, and un-perfect ground and source voltages. Table 3: Theoretical and Measured Bias Conditions Calculated Resistor Values Measured Values Percentage Difference Calculated Bias Conditions Measured Bias Conditions Percentage Difference R A 51 Ω 50.804 Ω 0.38% I C1 1.505 ma 1.616 ma 7.38% R C1 1.5 kω 1.499 kω 0.07% I E1 1.515 ma 1.620 ma 6.93% R E1 3.3 kω 3.286 kω 0.42% V C1 2.727 V 2.570 V 5.76% R E2 7.5 kω 7.491 kω 0.12% V OUT 2.027 V 1.878 V 7.35% R BN1 6.14 kω 6.139 kω 0.02% R BB1 860 Ω 853.63 Ω 0.74% 2016-03-25 Page 19 of 31

Step 9: Small-Signal Gain Measurement In this step, we measured the small-signal gain of the common-base common-collector amplifier. To do so, we firstly connected the signal generator and began to find the midband frequency range. We needed to know that we are operating in the midband frequency range to establish that small-signal changes won t bring about drastic changes in magnitude. The below procedure for finding the midband frequency range is taken directly from laboratory experiment 1. 1. Isolate the amplifier by placing voltage probes from an oscilloscope on the base and collector. 2. Record a relatively constant voltage on the collector by shifting the frequency knob. This is the midband collector voltage. 3. Find the lower -3dB frequency by verifying a voltage that is 1 of the midband collector voltage. 2 To do so, decrease the frequency on the function generator until the measured amplitude of the collector voltage reaches V collector. 2 4. Find the upper -3dB frequency by verifying a voltage that is 1 of the midband collector voltage. 2 To do so, tune increase the frequency on the function generator until the measured amplitude of the collector voltage reaches V collector. 2 5. Using the information from Step 3 and Step 4, the midband frequency range is as follows, Midband frequency range = upper f 3dB lower f 3dB = 2.81 MHz 87 Hz = 2.81 MHz (9.1) After finding the midband frequency range, we ensured ourselves that operating at approximately one decade above the lower cutoff frequency (at 1 khz) would give us a stable gain measurement. Thus, as seen in Figure 16 below, we used the oscilloscope to measure the gain with respect to the output (the collector of Q1) and input (the function generator). In Figure 16, the yellow trace labeled channel 1 represents the input and the blue trace labeled channel 2 represents the output. Our results yielded V OUT = 2.160 V and V IN = 114 mv yielding a small signal gain of 18.947 V/V as seen in Equation 9.2 below. Small signal gain = V out V in = 2.160 V 0.114 V = 18.947 (V V ) (9.2) 2016-03-25 Page 20 of 31

Input = 114 mv Output = 2.160 V Figure 16: Small-signal gain measurement with the oscilloscope Step 10: Maximum Output Swing Measurement For this step, we found the maximum output signal swing of our amplifier circuit. This was one of the requested performance parameters. To do so, we viewed the output voltage on the oscilloscope as we adjusted the amplitude of the inputting voltage on the function generator. When we saw clipping at either the top or bottom peak of the signal, we knew we went above the maximum output signal swing. Figure 17 displays the first clipping we saw at the output with the function generator set at 220 mv. 2016-03-25 Page 21 of 31

Output clipping, V gen = 220 mv Figure 17: Output signal clipping at top peak Readjusting the function generator to 180 mv amplitude gives us an output signal at V OUTMAX = 3.904 V pp. Figure 18 demonstrates that the output is no longer clipped. The maximum output signal swing was verified by the peak-to-peak measurement available on the oscilloscope. No clipping, V gen = 180 mv Figure 18: Output signal no longer clipping Thus, using the oscilloscope, we were able to verify the maximum output signal swing. 2016-03-25 Page 22 of 31

Step 11: Input Resistance Another specified performance parameter was the input resistance was to be within 10% of 75 Ω. We used the same procedure as used in simulations to find the input resistance looking into resistor R A. However, the measurements proved to be a bit tricky. We couldn t physically place a probe at the source of the function generator. Thus, we had to take it for the gospel that the setting set on the dial is the actual test voltage. We also had to trust that the function generator had an internal impedance, Rs, of 50 Ω as viewed on the dial settings. However, this setting is assuming that the device under test has 50 Ω impedance giving a perfect voltage divider from the source to load. Since we are using 10x oscilloscope probes, this adds a massive impedance to our device under test, thus giving the effect of seeing all of the voltage provided by the source. Thus, since our load isn t well-matched, the voltage measured in Figure 19 is actually twice the voltage seen on the dial settings. Hence, our test voltage should be multiplied by two. And so, using the test voltage as the dial on the function generator, and setting its amplitude to 200 mv pp, we measured the input voltage on the oscilloscope to be 242.6 mv pp as seen in Figure 19. Then using Equation 4.1, we solved for input resistance by, R in = R s V TEST V IN 1 = 50 2 200 242.6 1 = 77.06 (11.1) V IN = 242 mv pp Figure 19: Input Voltage Oscilloscope Measurement Our procedure for finding the input resistance 2016-03-25 Page 23 of 31

Step 12: Specifications Check This step was just a reality check of our constructed circuit with respect to the requested specification parameters. To have a complete comparison, the output resistance must also be measured. Unfortunately, we couldn t set up an experiment to measure the output resistance, due to leaving the laboratory earlier and lacking the proper equipment in a home setting. However, as seen in Table 4, the design proves to meet all the requested parameters and is well within the range of specification. Table 4: Given specifications vs simulated parameters vs measured parameters Parameter Type R IN V OUT/V IN (V/V) V OUTMAX R OUT Specification Parameter 75 Ω ± 10% 20 ± 10% 3.2 V p-p 50 Ω Simulated PSPICE Parameter 74.28 Ω 19.797 4.45 V p-p 20.02 Ω Measured Parameter 77.06 Ω 18.947 3.904 V p-p Luckily, we didn t have to adjust our circuit as to how it was from the very beginning. Figure 20 presents the final version of our circuit. Figure 20: Final Circuit Schematic 2016-03-25 Page 24 of 31

Step 13: Replacing the Bias Network After verifying all of the requested parameters with respect to the measured parameters, we were to improve our circuit. In this case, improving meant to replace the bias network with a new transistor, Q3. In theory, if transistors Q1 and Q3 are well-matched, and have the same collector current, their two emitter voltages should be nearly equal, thus making V E1 0. We changed the bias network to that of Figure 21. Figure 21: Replacement for Bias Network We then proceeded to verify the DC bias conditions, with the source signal disconnected. We also measured the voltage at the input of the amplifier, V B1. The results were recorded into Table 5 below. As seen from Table 5, the collector currents are nearly matched and both of the emitter voltages of transistors Q1 and Q3 are nearly zero. This is due to the voltage at the input of the amplifier, 0.691 V, nearly matching the base-to-emitter voltage, which we typically approximate to be 0.7 V. Table 5: Measured Bias Conditions Measured Resistor Values Measured DC Currents Measured DC Voltages R C1 1.499 kω I C1 1.466 ma V E1-2.500 mv R C3 3.130 kω I C3 1.404 ma V E3 0.029 mv R E1 3.286 kω V B1 0.691 V V C1 2.778 V 2.095 V V OUT 2016-03-25 Page 25 of 31

Next, we measured the small-signal gain with the substituted bias network. For this measurement, we used the Analog Discovery Waveform Generator and oscilloscope to verify the results as seen in Figure 22. V OUT = 2.002 V V IN = 93.6 mv Figure 22: Small-signal gain measurement Small signal gain = V out V in A gain of 21.389 V/V is still in the specifications boundary of 20 V/V ± 10%. = 2.002 V 0.0936 V = 21.389 (V V ) (13.1) 2016-03-25 Page 26 of 31

Item 1: Conclusion Show your final design and summarize all of the specifications you measured. (Do not re-state procedure, just summarize results.) The schematic is presented in Figure 23 and the measured specifications are recorded into Table 6. Figure 23: Final Circuit Design Schematic Table 6: Summary of Measured Values in Final Design Name Measured Value Specs Tolerance R A 50.804 Ω R C1 1.499 kω R E1 3.286 kω R E2 7.491 kω R BB1 853.63 Ω R IN 77.06 Ω 75 Ω ±10% R OUT 50 Ω spec. V OUTMAX 3.904 V pp 3.2 V pp spec. V OUT/V IN 18.947 V/V 20 V/V ± 10% 2016-03-25 Page 27 of 31

Item 2: How were the input resistance calculations and the output resistance calculations for this amplifier alike? Why? The input resistance and output resistance were very much alike for this amplifier circuit because of the same method used in calculations. It is the voltage divider method obtained from Dr. Heedley s Appendix 5.2, further discussed in Appendix A. In summary, a test voltage is applied to an active circuit with a deliberate known resistor, Rx. Then measuring the voltage drop after the resistor, tells us the characteristics of the circuit under test with Equation 6.1. From my observations from Steps 4, 6, 11, and 12, the formula is identical where V IN represents the voltage characteristic to the amplifier itself. R out = R X V TEST V IN 1 = (same formula for R IN ) (6.1) Item 3: Compare the voltage gain you measured to R C1 R IN (using the measured R IN). In a few words, explain why R C1 R IN should be the voltage gain. Using the measured values of R C1 and R IN, V OUT V IN R C1 R IN = 1.499 kω 77.06 Ω = 19.45 (V V ) The measured gain we found was 18.947 V/V, showing a 2.67% difference between the two values. The ratio of the two resistor values is nearly the same as the measured gain, but I don t believe it should be the voltage gain. However, I can explain why it is a good approximation. If we look back to the calculations for the voltage gain in Step 1, we see the equation: V C1 V in = R C1 R in R E1 R E1 + r e + R BB β (1.2) The fraction to the right of R C1 is nearly equal to one since r R e + R BB is small in comparison with RE1. We IN β know it is small because Equation 2.2 says, And, r e1 = V T 25 mv = = 17.05 Ω (2.2) I E1 1.466 ma R BB β = 853.63 100 = 8.54 Ω 2016-03-25 Page 28 of 31

In comparison with R E1 = 3.286 kω,(r e + R BB ) = 17.05 + 8.54 = 25.6 Ω. Since 3.286 kω >> 25.6 Ω, the β right side of the fraction can be reduced to, Which simplifies Equation 1.2 to, R E1 R E1 + r e + R BB β R E1 R E1 = 1 V C1 V in = R C1 R in Therefore R C1/R IN is a good and valid approximation of the voltage gain. Item 5: A common-base stage is sometimes called a current buffer. How did Q1 function as a current buffer in this experiment? Consider the division of the signal current i in at the emitter of Q1. How is the outcome of that current division consistent with the Q1 being a current buffer? Looking back to calculations from Step 1, we see the current division branching to that of the emitter of Q1 and resistor R E1. Figure 24 displays the diagram signifying each current being divided with respect to the input current. Since R E1 >> r e + R BB β Figure 24: Current Division from input to Q1, the following equation is formed, i e1 = i in R E1 R E1 + r e1 + R BB β i in R E1 R E1 = i in This equation shows that the input current is 180 out of phase with the emitter current of Q1. Therefore, Q1 acts as a current buffer, buffering or lagging the inputting current by a phase of 180 while keeping the amplitude fairly constant. 2016-03-25 Page 29 of 31

Item 6: Did the measured voltage gain go up or down when the bias network of Figure 5 was used? Why? The measured voltage gain went up from 18.947 V/V to 21.389 V/V. The reason for this is described by the approximation version of Equation 1.2 from conclusion Item 3, Where, V C1 V in = R C1 R in (1.2) R in = R A + R E1 //(r e1 + R BB β ) The only factor that was changed in this Equation was R BB which is now, R BB = R C3 //r π //r o R C3 = 3.13 kω The equivalent approximation is made since R C3 << r o and < r π. Thus, if R BB increases from 860 Ω to 3.13 kω, the input resistance decreases due to the parallel combination of R E1 //(r e1 + R BB β ). And since the input resistance is decreased, and seeing that the gain is inversely proportional to the input resistance, this increases the gain. In short, an increase of R BB increased the gain. 2016-03-25 Page 30 of 31

Appendix A: Input and Output Resistance Measurements Below is a sample representation of the voltage divider method of calculating the input and output resistances taken from Appendix 5.2 of the EEE 109 Moodle Webpage. The Appendix displays that a test voltage signal along with a deliberate resistor, R X, is added to an input or output node. Once that happens, R X is now in series with the unknown resistor. Knowing the test voltage and recognizing that the input voltage of the circuit is now in the form of a voltage divider yields R X R out = = (same formula for R V IN ) (6.1) TEST 1 V IN As seen, the same method is implemented for finding both the input and output resistances. 2016-03-25 Page 31 of 31