MUN5DW, NSBCEPDXV6, NSBCEPDP6 Complementary Bias Resistor Transistors R =.7 k, R =.7 k NPN and PNP Transistors with Monolithic Bias Resistor Network () PIN CONNECTIONS () () This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. Q R R R R Q Features Simplifies Circuit Design Reduces Board Space Reduces Component Count S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q Qualified and PPAP Capable These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant () (5) MARKING DIAGRAMS SOT6 CASE 9B 6 (6) M MAXIMUM RATINGS (T A = both polarities Q (PNP) & Q (NPN), unless otherwise noted) Rating Symbol Max Unit Collector-Base Voltage V CBO 5 Collector-Emitter Voltage V CEO 5 Collector Current Continuous I C madc Input Forward Voltage V IN(fwd) Input Reverse Voltage V IN(rev) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION MUN5DWTG, NSVMUN5DWTG Device Package Shipping SOT6,/Tape & Reel NSBCEPDXV6TG SOT56,/Tape & Reel NSBCEPDP6T5G SOT96 8,/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. SOT56 CASE 6A SOT96 CASE 57AD M /V = Specific Device Code M = Date Code* = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. V M Semiconductor Components Industries, LLC, September, Rev. Publication Order Number: DTCEP/D
MUN5DW, NSBCEPDXV6, NSBCEPDP6 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit MUN5DW (SOT6) ONE JUNCTION HEATED T A = (Note ) (Note ) Derate above (Note ) (Note ) (Note ) Junction to Ambient (Note ) MUN5DW (SOT6) BOTH JUNCTION HEATED (Note ) T A = (Note ) (Note ) Derate above (Note ) (Note ) Junction to Ambient (Note ) (Note ) Junction to Lead (Note ) (Note ) 87 56.5. R JA 67 9 5 85.. R JA 9 5 R JL 88 8 Junction and Storage Temperature Range T J, T stg 55 to +5 C NSBCEPDXV6 (SOT56) ONE JUNCTION HEATED T A = (Note ) Derate above (Note ) Junction to Ambient (Note ) NSBCEPDXV6 (SOT56) BOTH JUNCTION HEATED (Note ) T A = (Note ) Derate above (Note ) Junction to Ambient (Note ) 57.9 R JA 5 5. R JA 5 Junction and Storage Temperature Range T J, T stg 55 to +5 C NSBCEPDP6 (SOT96) ONE JUNCTION HEATED T A = (Note ) Derate above (Note ) Junction to Ambient (Note ) NSBCEPDP6 (SOT96) BOTH JUNCTION HEATED (Note ) T A = (Note ) Derate above (Note ) Junction to Ambient (Note ) 69.9. R JA 5 6 9 8.7. R JA 69 6 Junction and Storage Temperature Range T J, T stg 55 to +5 C. FR @ Minimum Pad.. FR @.. Inch Pad.. Both junction heated values assume total power is sum of two equally powered channels.. FR @ mm, oz. copper traces, still air. 5. FR @ 5 mm, oz. copper traces, still air. mw mw mw mw MW MW
MUN5DW, NSBCEPDXV6, NSBCEPDP6 ELECTRICAL CHARACTERISTICS (T A = both polarities Q (PNP) & Q (NPN), unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Collector-Base Cutoff Current I CBO nadc (V CB =5V, I E =) Collector-Emitter Cutoff Current (V CE =5V, I B =) Emitter-Base Cutoff Current (V EB = 6. V, I C =) Collector-Base Breakdown Voltage (I C = A, I E =) Collector-Emitter Breakdown Voltage (Note 6) (I C =. ma, I B =) ON CHARACTERISTICS DC Current Gain (Note 6) (I C = 5. ma, V CE =V) Collector-Emitter Saturation Voltage (Note 6) (I C = ma, I B =. ma) Input Voltage (Off) (V CE = 5. V, I C = A) (NPN) (V CE = 5. V, I C = A) (PNP) Input Voltage (On) (V CE =. V, I C = ma) (NPN) (V CE =. V, I C = ma) (PNP) Output Voltage (On) (V CC = 5. V, V B =.5 V, R L =. k ) Output Voltage (Off) (V CC = 5. V, V B =.5 V, R L =. k ) I CEO 5 I EBO.5 V (BR)CBO 5 V (BR)CEO 5 h FE 5 V CE(sat).5 V i(off) V i(on)....8 V OL. V OH.9 Input Resistor R..7 6. k Resistor Ratio R /R.8.. 6. Pulsed Condition: Pulse Width = ms, Duty Cycle %. nadc madc V, POWER DISSIPATION (mw) 5 5 5 5 () () () () SOT6;.. Inch Pad () SOT56; Minimum Pad () SOT96; mm, oz. Copper Trace 5 5 5 5 75 5 5 AMBIENT TEMPERATURE ( C) Figure. Derating Curve
MUN5DW, NSBCEPDXV6, NSBCEPDP6 TYPICAL CHARACTERISTICS NPN TRANSISTOR MUN5DW, NSBCEPDXV6 V CE(sat), COLLECTOREMITTER VOLTAGE (V).. I C /I B = 5 C 5 h FE, DC CURRENT GAIN.. V CE = V 5 C Figure. V CE(sat), vs. I C Figure. DC Current Gain C ob, OUTPUT CAPACITANCE (pf).6..8...6..8. f = khz I E = A T A =. 5 C V O = 5 V 5. 5 V R, REVERSE VOLTAGE (V) Figure. Output Capacitance Figure 5. Output Current vs. Input Voltage 5 C V O =. V. Figure 6. Input Voltage vs. Output Current 5
MUN5DW, NSBCEPDXV6, NSBCEPDP6 TYPICAL CHARACTERISTICS PNP TRANSISTOR MUN5DW, NSBCEPDXV6 V CE(sat), COLLECTOREMITTER VOLTAGE (V)... I C /I B = 75 C 5 h FE, DC CURRENT GAIN V CE = V 75 C T A = Figure 7. V CE(sat) vs. I C Figure 8. DC Current Gain C ob, OUTPUT CAPACITANCE (pf) 9 8 7 6 5 f = khz l E = A T A =.. 75 C T A = V O = 5 V 5. 5 6 7 8 9 V R, REVERSE VOLTAGE (V) Figure 9. Output Capacitance Figure. Output Current vs. Input Voltage T A = 75 C V O =. V. 5 Figure. Input Voltage vs. Output Current 5
MUN5DW, NSBCEPDXV6, NSBCEPDP6 TYPICAL CHARACTERISTICS NPN TRANSISTOR NSBCEPDP6 V CE(sat), COLLECTOREMITTER VOLTAGE (V).. I C /I B = 5 C 5 h FE, DC CURRENT GAIN.. V CE = V 5 C Figure. V CE(sat), vs. I C Figure. DC Current Gain C ob, OUTPUT CAPACITANCE (pf)...6..8. f = khz I E = A T A =. 5 C V O = 5 V 5. V R, REVERSE VOLTAGE (V) Figure. Output Capacitance Figure 5. Output Current vs. Input Voltage 5 C V O =. V. Figure 6. Input Voltage vs. Output Current 5 6
MUN5DW, NSBCEPDXV6, NSBCEPDP6 TYPICAL CHARACTERISTICS PNP TRANSISTOR NSBCEPDP6 V CE(sat), COLLECTOREMITTER VOLTAGE (V).. I C /I B = 5 C 5 h FE, DC CURRENT GAIN.. 5 C V CE = V Figure 7. V CE(sat) vs. I C Figure 8. DC Current Gain C ob, OUTPUT CAPACITANCE (pf) 7 6 5 f = khz I E = A T A =. 5 C V O = 5 V 5. 5 6 7 V R, REVERSE VOLTAGE (V) Figure 9. Output Capacitance Figure. Output Current vs. Input Voltage 5 C. V O =. V 5 Figure. Input Voltage vs. Output Current 7
MUN5DW, NSBCEPDXV6, NSBCEPDP6 PACKAGE DIMENSIONS SC88/SC76/SOT6 CASE 9B ISSUE W D e NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: INCH.. 9B OBSOLETE, NEW STANDARD 9B. H E 6 5 E b 6 PL. (.8) M E M MILLIMETERS DIM MIN NOM MAX A.8.95. A..5. A b... C...5 D.8.. E.5.5.5 e.65 BSC L... H E... INCHES MIN NOM MAX..7..... REF.8 REF..8...5..7.78.86.5.9.5.6 BSC..8..78.8.86 A A C A L SOLDERING FOOTPRINT*.5.97.65.5..57.65.5.9.78 SCALE : SC88/SC76/SOT6 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8
MUN5DW, NSBCEPDXV6, NSBCEPDP6 PACKAGE DIMENSIONS SOT56, 6 LEAD CASE 6A ISSUE F D X A L NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 98.. CONTROLLING DIMENSION: MILLIMETERS. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 6 5 e E Y b 65 PL.8 (.) M X Y H E C MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A.5.55.6... b.7..7.7.9. C D.8.5..6.8.7..59.5.6.7.66 E.....7.5 e.5 BSC. BSC L.....8. H E.5.6.7.59.6.66 SOLDERING FOOTPRINT*..8.5.77.5.5..9.5.5.97.97 SCALE : mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 9
MUN5DW, NSBCEPDXV6, NSBCEPDP6 PACKAGE DIMENSIONS SOT96 CASE 57AD ISSUE E D 6 5 TOP VIEW e X Y E 6X L A C SIDE VIEW H E NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.5M, 99.. CONTROLLING DIMENSION: MILLIMETERS. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS DIM MIN NOM MAX A..7. b..5. C.7..7 D.95..5 E.75.8.85 e.5 BSC H E.95..5 L.9 REF L.5..5 6X L BOTTOM VIEW 6X b.8 X Y RECOMMENDED MOUNTING FOOTPRINT* 6X. 6X.5 PACKAGE OUTLINE..5 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patentmarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 56, Denver, Colorado 87 USA Phone: 67575 or 886 Toll Free USA/Canada Fax: 67576 or 8867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 889855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: 85875 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative DTCEP/D
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