A Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury

A Low Power Analog Front End Capable of Monitoring Knee Movements to Detect Injury Garren Boggs, Hua Chen, Sridhar Sivapurapu ECE 6414 Final Presentation

Outline Motivation System Overview Analog Front End SAR ADC Linear Regulator and Biasing Putting it all Together Future Work Questions

Motivation Target: Athletes participating in sports that involve increased stress on the lower body have an increased risk of developing knee injuries. Product: The need for a non-invasive solution for the detection and prevention of such injuries, ensuring the athlete s ability to continue their participation. Starting Point: Dr. Inan s previous research into microphone selection and Analog Front End.

System Overview

Analog Front End

Amplifier Specifications ICMR: Rail-to-Rail Output Swing: Rail-to-Rail Open Loop Gain: 100 db Stage 1 Closed Loop Gain: 26dB Stage 2 Closed Loop Gain: 37dB Closed Loop Bandwidth: 21KHz Reasonably High Drive Current

Amplifier Schematic and Characteristics Parameter Value Supply Voltage +3V ICMR Rail-to- Rail Output Swing 2.9mV / 2.998V V OS 94μV CMRR 132dB PSRR+ 66dB PSRR- 56dB A 0 108dB f 0dB 12.7MHz ϕ M 93.5 Max Current Drive 223μA R out 248kΩ Slew Rate 5.829V/μs V n,input (1MHz BW) 10.89μV rms Power Consumption 149μW 1pF C c

Amplifier Open Loop Response

Bandpass Filter Specifications Topology: G m -C biquadratic Bandwidth: 15Hz 21kHz Response Type: Butterworth Order: 12 th Very Low Power Consumption

OTA Schematic and Characteristics Parameter Value Supply Voltage +3V G m 297nS 41dB A 0 V n,input (1MHz BW) Power Consumption 96.18μV rms 3.76μW

OTA GM

High Pass Filter Schematic

Low Pass Filter Schematic

Band Pass Filter Response

Full Analog Front End Schematic

Full Analog Front End Frequency Response

Full Analog Front End Transient Response f = 1 khz f = 100 khz

Analog to Digital Converter

ADC Top Level Schematic

Comparator Schematic and Characteristics Parameter Value Supply Voltage 3 V P Max 173 µw P average 71.4 µw Peak Energy/Comparison 2.76 pj t plh t phl Hysteresis Minimum Pulse Width t r,t f ICMR, Output Swing 54 ns 35 ns (-8 mv, 9 mv) 50.5 ns 1.14 ns Rail-to-Rail

Successive Approximation Register Picture from: R. Hedayati, "A Study of Successive Approximation Registers and Implementation of an Ultra- Low Power 10-bit SAR ADC in 65nm CMOS Technology," 2011. [Online]. Available: http://www.divaportal.org/smash/get/diva2:462318/fulltext01.pdf. Accessed: Mar. 6, 2017.

DAC Top Level Simplified Schematic Picture from: R. Hedayati, "A Study of Successive Approximation Registers and Implementation of an Ultra- Low Power 10-bit SAR ADC in 65nm CMOS Technology," 2011. [Online]. Available: http://www.divaportal.org/smash/get/diva2:462318/fulltext01.pdf. Accessed: Mar. 6, 2017.

DAC and Sample and Hold Output

ADC Characteristics and DNL and INL Plots Parameter Supply Voltage INL (Worst Case) DNL (Case) f sampling f CLK ENOB SFDR P Average VALUE 3V.5 LSB.3 LSB 50 khz 1 MHz 7.45 bits 47.29 db 114.9 μw FOM 657 fj/conversionstep

Comparator and Switch Layout Comparator (Left), Set of switches (Right)

Full ADC Layout

Linear Regulator and Peripheral Biasing

LDO and BMR Schematic Cascode BMR Error Amplifier

LDO Schematic and Characteristics Parameter VALUE V out 3.02 V Dropout Voltage.2 V Output Current 10.08 ma V Battery sensitivity 188 ppm Temperature sensitivity 437 ppm Power Supply Gain + -28.2 db Power Supply Gain - -.275 db Output Noise 7.178µV rms Efficiency 77.5% Startup Delay 2.59 s

V CM Generator Schematic and Characteristics Parameter VALUE V out 1.51 V Output Current 800 µa V Battery sensitivity 225 ppm Temperature sensitivity 689 ppm Power Supply Gain + -34.22 db Power Supply Gain - -.448 db Output Noise 11µV rms Startup Delay 2.45 s

LDO and V CM Line and Load Regulation Line Regulation Load Regulation

LDO and V CM Output Voltage and Current Voltage Transfer Output Current

Peripheral BMR Bias Schematic and Characteristics Parameter VALUE V Supply 3.02 V V biasn.8 V V Supply sensitivity (V biasn ) 32 ppm I bias 5.96 µa V Supply sensitivity (I bias ) 485 ppm

Putting it all Together

Top Level Schematic

Floor Plan D7 D6 D5 D4 D3 D2 D1 D0 NC RFB11 RFB12 ADC S/H CLK RESET RFB13 VBAT RFB21 RFB22 RFB23 AFE PMIC GND CLDO NC CFB11 VIN CFB 12 CFB 13 CFB 21 CFB 22 CFB 23 CFB 31 CFB 32 CFB 33

Future Work

Future Work Input logic for Variable Gain Amplifier. Variable cutoff frequencies for filter. Designing antenna and on chip clock signals. Higher resolution ADC.

Thanks! Questions?