Applications Switch Mode Power Supply ( SMPS ) Uninterruptable Power Supply High speed power switching Lead-Free Benefits Low Gate Charge Qg results in Simple Drive Requirement Improved Gate, Avalanche and dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche Voltage and Current Effective Coss specified ( See AN 00) SMPS MOSFET IRF830APbF HEXFET Power MOSFET V DSS Rds(on) max I D 500V.40Ω 5.0A TO-220AB G D S PD- 94820 Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 5.0 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 3.2 A I DM Pulsed Drain Current 20 P D @T C = 25 C Power Dissipation 74 W Linear Derating Factor 0.59 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt 3 5.3 V/ns T J Operating Junction and -55 to 50 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting torqe, 6-32 or M3 screw 0 lbf in (.N m) Typical SMPS Topologies: Two transistor Forward Half Bridge and Full Bridge Notes through 5 are on page 8 www.irf.com /5/03
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 500 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.60 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance.4 Ω V GS = 0V, I D = 3.0A 4 V GS(th) Gate Threshold Voltage 2.0 4.5 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 500V, V GS = 0V 250 V DS = 400V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 00 V GS = 30V na Gate-to-Source Reverse Leakage -00 V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 2.8 S V DS = 50V, I D = 3.0A Q g Total Gate Charge 24 I D = 5.0A Q gs Gate-to-Source Charge 6.3 nc V DS = 400V Q gd Gate-to-Drain ("Miller") Charge V GS = 0V, See Fig. 6 and 3 4 t d(on) Turn-On Delay Time 0 V DD = 250V t r Rise Time 2 ns I D = 5.0A t d(off) Turn-Off Delay Time 2 R G = 4Ω t f Fall Time 5 R D = 49Ω,See Fig. 0 4 C iss Input Capacitance 620 V GS = 0V C oss Output Capacitance 93 V DS = 25V C rss Reverse Transfer Capacitance 4.3 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 886 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 27 V GS = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 39 V GS = 0V, V DS = 0V to 400V 5 Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy2 230 mj I AR Avalanche Current 5.0 A E AR Repetitive Avalanche Energy 7.4 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.7 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 5.0 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 20 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S = 5.0A, V GS = 0V 4 t rr Reverse Recovery Time 430 650 ns T J = 25 C, I F = 5.0A Q rr Reverse RecoveryCharge.62 2.4 µc di/dt = 00A/µs 4 t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) 00 0 0. VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T J = 25 C 0. 0 00 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH 0. T J = 50 C 0 00 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 50 C T J = 25 C V DS = 50V 20µs PULSE WIDTH 0. 4.0 5.0 6.0 7.0 8.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 5.0A 2.0.5.0 0.5 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 T J, Junction Temperature( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 0000 000 00 0 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd C oss = C ds Cgd C iss C oss C rss A 0 00 000 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 5.0A V DS = 400V V DS = 250V V DS = 00V FOR TEST CIRCUIT SEE FIGURE 3 0 0 4 8 2 6 20 24 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 T J = 50 C T J = 25 C V GS = 0 V 0. 0.2 0.4 0.6 0.8.0.2 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us 00us ms 0ms TC = 25 C TJ = 50 C Single Pulse 0. 0 00 000 0000 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
5.0 V DS R D I D, Drain Current (A) 4.0 3.0 2.0.0 Fig 0a. Switching Time Test Circuit V DS 90% R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. - V DD 0.0 25 50 75 00 25 50 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms 0 Thermal Response (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) 0.0 0.0000 0.000 0.00 0.0 t, Rectangular Pulse Durat Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
5V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) 500 400 300 200 00 I D TOP 2.2A 3.2A BOTTOM 5.0A 0 25 50 75 00 25 50 Starting T, Junction Temperature( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Q GS Q GD 790 V G 2V V GS Current Regulator Same Type as D.U.T..2µF 50KΩ 3mA.3µF Charge Fig 3a. Basic Gate Charge Waveform D.U.T. V - DS V DSav, Avalanche Voltage (V) 785 780 775 770 A 0.0.0 2.0 3.0 4.0 5.0 I av, Avalanche Current (A) I G I D Current Sampling Resistors Fig 2d. Typical Drain-to-Source Voltage Fig 3b. Gate Charge Test Circuit Vs. Avalanche Current 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T 3 - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer 2 - - 4 R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS www.irf.com 7
TO-220AB Package Outline 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) - A - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 2 3 4 6.47 (.255) 6.0 (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK - GATE - GATE 2 - DRAIN - GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR.40 (.055) 3X.5 (.045) 2.54 (.00) 2X 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF00 LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) 2 Starting T J = 25 C, L = 8mH R G = 25Ω, I AS = 5.0A. (See Figure 2) 3 I SD 5.0A, di/dt 370A/µs, V DD V (BR)DSS, T J 50 C 4 Pulse width 300µs; duty cycle 2%. 5 C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) 252-705 TAC Fax: (30) 252-7903 Visit us at www.irf.com for sales contact information./03 8 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/