June 7-10, 2009 San Diego, CA Optimization of Wafer Level Test Hardware using Signal Integrity Simulation Jason Mroczkowski Ryan Satrom
Agenda Industry Drivers Wafer Scale Test Interface Simulation Simulation Techniques Capturing Interfaces Full Test Interface Simulation Example Components that most impact performance Optimization of interfaces Full system results IEEE SW Test Workshop 2
Wafer Scale Test - Industry Drivers Industry Expectations Short lead-times Low cost - varies with complexity High quality - First Pass Success! Challenges DUT complexity - faster, smaller, integrated Test hardware complexity - fine pitch, low inductance, matched impedance Don t let this happen to you IEEE SW Test Workshop 3
Lowering the Cost of Test Eliminate Guesswork Through Signal Integrity Simulation Ensure performance prior to fabrication Eliminate re-spins and time consuming lab analysis Simulate All Structures in the Path from the Tester to the DUT Tester Probe Card IC Device (DUT) IEEE SW Test Workshop 4
Test Interface Simulation Focus on Critical Nets Full PCB signal integrity simulation not necessary Critical High Not all traces are high speed Speed Nets Similar layouts require single simulation Good isolation in multilayer PCB minimizes crosstalk IEEE SW Test Workshop 5
Simulation Techniques Lumped Element Models (SPICE) Generic (not pinout specific) No physical length Ideal elements Must be highly distributed to be accurate into GHz range Appropriate for component (capacitor, inductor, balun) models IEEE SW Test Workshop 6
Simulation Techniques Transmission Line Models Cross-sectional per unit length model Captures physical properties of materials Appropriate for straight traces IEEE SW Test Workshop 7
Simulation Techniques 2.5D Electromagnetics Captures effects of bends and cross-talk Makes approximations for vias, conductor thickness, etc. Appropriate for planar geometries IEEE SW Test Workshop 8
Simulation Techniques Full 3D Electromagnetic Simulation Probe Cards Connectors Vias Packages Most Rigorous Simulation Technique Captures All Losses of Physical Environment IEEE SW Test Workshop 9
Interface Simulation Sum of Pieces: 1dB Contactor 1dB Board 1dB Connectors, Launches 3dB @ n GHz Collection of Pieces Approach Does Not Account for Transitions + Loss (db) 0-0.5-1 -1.5-2 -2.5 FULL SYSTEM MODELING - INSERTION LOSS (db) Case 3 : 4.4 GHz Case1: Trace + HFSS PROBE ONLY Case2: Trace + SPICE Launch + HFSS PROBE ONLY Case3: HFSS Full Model -3 0 5 10 15 20 Case 2 : 5.2 GHz Frequency (GHz) Case 1: 8.0 GHz IEEE SW Test Workshop 10
Case Study: High Speed Probe Card Test Testing of RF Input to DUT 2.4 GHz Test Requirement Will a Probe Card Support This? IEEE SW Test Workshop 11
Probe Card Test Interface Physical Description of Components IEEE SW Test Workshop 12
Connector Optimization Signal Pin Creates Impedance Mismatch with Standard Footprint Optimizing PCB Ground Clearance Diameter Improves Results Worst Case 1dB @ 1.5Ghz Best Case 1dB @ 6GHz Loss (db) 0-0.5-1 -1.5-2 -2.5-3 -3.5-4 -4.5-5 0-5 -10 INSERTION LOSS (db) Initial Design Optimized Design 0 2 4 6 8 10 12 Frequency (GHz) RETURN LOSS (db) Initial Design Loss (db) -15-20 -25-30 -35 Initial Design Optimized Design Increased Clearance -40 0 2 4 6 8 10 12 Frequency (GHz) Optimized Design IEEE SW Test Workshop 13
Trace Length Loss Often Major Contributor to Overall Loss Must Correlate with Manufacturing Process Worst Case (16 ) 1dB @ 300 MHz Best Case (2 ) 1dB @ 5 GHz IEEE SW Test Workshop 14
Optimization: Stub Removal Stub Full Length Via and Inner Layer Trace Backdrill Remove Via to Trace Layer Worst Case 1dB @ 2 GHz Best Case 1dB @ 8 GHz IEEE SW Test Workshop 15
Probe Needle Optimization The needles have very high impedance, above 300 Ohms. Impedance can be lowered with epoxy to improve performance Worst Case 1dB @ 1 GHz Best Case 1dB @ 1.4 GHz IEEE SW Test Workshop 16
System Simulation Model Includes: Connector 3D EM simulation PCB traces Transmission line models Balun Manufacturer SPICE model Capacitors Vias Manufacturer SPICE model 3D EM simulation Probe card 3D EM simulation IEEE SW Test Workshop 17
System Performance Total System 3dB Loss point @ 1.9 GHz Probe needles account for majority of loss IEEE SW Test Workshop 18
Probe Needle Alternative Spring Probe Probes 3mm vs needles 50mm Probe impedance 80-120 Needle impedance 125-300 Probes 1dB @ 21.4 GHz Probes w/ 50mm trace 1dB @ 8.0GHz IEEE SW Test Workshop 19
Probe Card vs. Contactor System Simulation Results Bandwidth Probe Card 3dB @ 1.9 GHz Spring Probe 3dB @ 6.1 GHz 10GB/s Eye Diagram Probe Card 44ps rise-time Spring Probe 24ps rise-time IEEE SW Test Workshop 20
Going Forward Other Variables Not Optimized: Via diameter, trace width, board material, clearance diameters, ground vias, package, etc. Future Work Performance matrix for Engineers to quickly determine loss given tester, probe type, board material Insertion Loss 20-80 Output Rise Time S12 10ps 50ps 100ps VIEW Pitch Probe PCB GND Trace Length -1dB -3dB INPUT INPUT INPUT X 0.4mm Gem040 N4000-13 GSSG Stripline 02in 3.8 12.1 15.9 53.9 103.7 X 0.4mm Gem040 N4000-13 GSSG Stripline 12in 0.4 1.8 81.8 116.2 153.3 IEEE SW Test Workshop 21
Summary System Performance Impacted by Choice of Hardware Components and Design of Performance Board Simulation Can Optimize Performance Before Fabrication Simulation Reduces Lab Characterization and Re-spins and Provides Fastest Path to Production IEEE SW Test Workshop 22