ADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION

98 Chapter-5 ADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION

99 CHAPTER-5 Chapter 5: ADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION S.No Name of the Sub-Title Page No. 5.1 Advanced Embedded Electromagnetic Radiation 99 Monitoring System 5.1.1 RF 2052 100 5.1.2 Estimation of Signal Strength Using Si 4362 103 5.1.3 ARM Controller 114 5.1.4 Data Transfer Module 118 5.1.5 Display Section 119 5.1.6 GSM Module 123 5.2 Chapter Summary 123

100 5. ADVANCED EMBEDDED MONITORING SYSTEM FOR ELECTROMAGNETIC RADIATION This Chapter describes an embedded monitoring system, which is a combination of both hardware (Embedded RF Unit) and software (Visual Basic 2010) to estimate the radiation power level. 5.1 ADVANCED EMBEDDED ELECTROMAGNETIC RADIATION MONITORING SYSTEM The primary objective of this research work is to monitor the electromagnetic radiations that are radiated by cellular base station antennas as well as mobile units and other RF sources. A system called Advanced Embedded Electromagnetic Radiation Monitoring System (AEERMS) is proposed to monitor this electromagnetic radiation and intimate to the concerned authorities, if the radiation level is above the safety limits prescribed by FCC and ICNRP. The Advanced Embedded Electromagnetic Radiation Monitoring System (AEERMS) has been designed for easy detection of radiation levels at a given point in the cellular base station premises (residential areas or offices). It is a broadband instrument and accurately detects the cumulative radiation in the range of 30 MHZ to 1700MHZ in one band and 1700 MHz to 2.5 GHz in another band, which covers the frequencies used by most modern communication systems (CDMA, GSM1800, 3G and WI-FI/WLAN/BLUETOOTH frequency bands) that are encountered in our daily life. By using this system, the radiation

101 levels can be measured corresponding to each frequency of a single network. Also, the total radiated power for all the frequencies of different networks can be measured using this AEERMS. If the radiation level is more than -30 dbm, then the monitoring system detects it as a danger level of radiation and it sends short messages to the concerned authorities informing about the hazardous radiation from the particular frequency band at the particular place. Figure 5.1 Block Diagram of advanced embedded electromagnetic radiation monitoring system The block diagram of advanced embedded electromagnetic radiation monitoring system is shown in Figure 5.1. The receiving antenna is capable of receiving the signals with frequency in the range of 80 MHz and 2.5 GHz. AEERMS receives the center frequency and span values from the user using the display section. The selected

102 center frequency and span in the display section is fed to the ARM controller through USB cable. The ARM controller which is loaded with fractional-n algorithm, will convert the selected center frequency and span into its corresponding digital value and is given to the RF 2052 [74]. The RF 2052 will tune the wide band input signal to the band of desired frequencies and sends this tuned signals to Si 4362 [78] to estimate the signal strength. The Si 4362 converts the estimated radiation levels into digital format and the digital data is sent to the ARM controller [75, 76]. The ARM controller compares the received power level from Si 4362 with the FCC standard power level. If the power level is more than that of the FCC standards, AEERMS will treat it as dangerous level and the GSM Module section will be activated to send a message to the corresponding authorities. AEERMS. The Figure 5.2 shows the prototype hardware components of Figure 5.2 Prototype Hardware of AEERMS

103 The different blocks in this system are: 1. RF2052 2. Si4362 3. ARM 4. Data Transfer Modules (CP2102, USB) 5. GSM Module 6. Display 5.1.1 RF 2052 Figure 5.3 Functional Block Diagram of RF 2052 The RF2052 IC is internally connected to an antenna. The RF2052 is a low power, high performance and wideband RF frequency conversion chip with integrated local oscillator (LO) generation and RF

104 mixer. The RF synthesizer includes an integrated fractional-n phase locked loop with voltage controlled oscillators (VCOs) and dividers to produce a low-phase noise LO signal with a very fine frequency resolution. The buffered LO output drives the built-in RF mixer which converts the signal into the required frequency band. The mixer bias current can be programmed dependent on the required performance and available supply current. The LO generation blocks have been designed to continuously cover the frequency range from 30 MHz to 2500MHz. The RF mixer is a very broad band and operates from 30MHz to 2500MHz at the input and output, enabling both up and down conversion. An external crystal of frequency between 10MHz and 52MHz or an external reference source of frequency between 10MHz and 104MHz can be used with the RF2052 to accommodate a variety of reference frequency options [70]. For the input port, the input frequency should always be about 30 MHz; the matching circuit will be tuned to work well at 30 MHz to 2.5GHZ. To get the best performance from the RF2052 mixer, the matching circuits for the input and output ports should be tuned for the specific frequency required ranges for a particular application. Since the widest range possible is desired for the final design, the simplest wideband matching circuits for the output port was chosen. The RF2051 chip is capable of synthesizing a local oscillator frequency between 30 MHz to 2500 MHz, the RF mixer is also integrated into the chip that can mix an RF signal between 30 MHz to

105 2.5 GHz with the local oscillator. The RF2051 is almost identical to the RF2052 except that it has two mixers. An external crystal of between 10MHz to 52MHz or an external reference source of between 10 MHz to 104 MHz can be used with the RF2052 to accommodate a variety of reference frequency options. The programmed register (R) in RF2052 section is required to capture the frequency values with internal circuitry, and then the frequency values are sent to the frequency synthesizer section where the Phased Locked loop (PLL) is locked to required frequency. It sends the obtained frequency values to the mixer. The mixer mixes the required frequency and antenna frequency and it down convert by four and the resultant signal is fed to SI4362 section. Voltage Controlled Oscillator (VCO) The VCO core in the RF2052 consists of three VCOs in conjunction with the integrated 2/4 LO divider, that covers the LO range from 300MHz to 2400MHz. VCO 1, 2, and 3 are selected using the Phase locked loop (PLL) PLL2x0:P2_VCOSEL control word. Each VCO has 128 overlapping bands to achieve an acceptable VCO gain and hence a good phase noise performance across the whole tuning range. The chip automatically selects the correct VCO band ( VCO coarse tuning ) to generate the desired LO frequency based on the values programmed into the PLL2 registers bank.

106 Once the band has been selected, the PLL will lock onto the correct frequency. During the band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO oscillates approximately at the correct frequency. For applications where the synthesizer is always ON and the LO frequency is fixed, the synthesizer will maintain lock over a +/-60 C temperature range. Fractional-N PLL To control the three VCOs, the IC contains a charge-pump based fractional-n phase locked loop (PLL). The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. The PLL will lock the VCO to the frequency FVCO according to [70]: FVCO=NEFF*FOSC/R Where NEFF = Programmed fractional N divider value FOSC= Reference input frequency R= Programmed R divider value (1 to 7). The N divider is a fractional divider, containing a dual-modulus pre-scalar and a digitally spur-compensated fractional sequence generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows: first determine the desired, effective N divider value, NEFF, NEFF = FVCO *R / FOSC

107 N (9:0) should be set to the integer part of NEFF.NUM should be set to the fractional part of NEFF multiplied by 2^24=16777216. Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is: NEFF = FVCO *R / FOSC =2220 *1 / 23.92=92.80936454849. The N value is set to 92, which is the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2 24 : NUM=0.80936454895 * 2 24 =13,578,884. Converting N and NUM into binary results in the following: N=0 0101 1100 NUM=1100 1111 0011 0010 1000 0100 So the registers would be programmed: P2_N=0 0101 1100 P2_NUM_MSB=1100 1111 0011 0010 P2_NUM_LSB=1000 0100 The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode. The minimum step size is FOSC/R*2 24. Thus for a 23.92MHz reference, the frequency step size would be 1.4 Hz. The minimum reference frequency that could be used to program a frequency of 2400 MHz (using VCO1) is 2400/511, (= 4.697 MHz) For VCO frequency 1800 MHz: FVCO =1800 MHz FOSC =23.92 MHz NEFF = FVCO *R / FOSC = 1800 *1 / 23.92

108 =75.25083612 The N value is set to 75, the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24: NUM=0.25083612* 2^24=4208331 Converting N and NUM into binary results in the following N=0 0100 1011 NUM=0100 0000 0011 0110 1100 1011 So the registers would be programmed P2_N=0 0100 1011 P2_NUM_MSB=0100 0000 0011 0110 P2_NUM_LSB=1100 1011 For VCO frequency 1830 MHz FVCO =1830 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC =1830 *1 / 23.92 =76.50501672 The N value is set to 76, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24 NUM=0.50501672* 2^24=8472774 Converting N and NUM into binary results in the following N=0 0100 1100 NUM=1000 0001 0100 1000 1100 0110 So the registers would be programmed P2_N=0 0100 1100

109 P2_NUM_MSB=1000 0001 0100 1000 P2_NUM_LSB=1100 0110 For VCO frequency 1860 MHz FVCO =1860 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC =1860 *1 / 23.92 =77.75919732 The N value is set to 77, equals to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24: NUM=0.75919732* 2^24=12737217 Converting N and NUM into binary results in the following N=0 0100 1101 NUM=1100 0010 0101 1010 1100 0001 So the registers would be programmed P2_N=0 0100 1101 P2_NUM_MSB=1100 0010 0101 1010 P2_NUM_LSB=1100 0001 For VCO frequency 1900 MHz: FVCO =1900 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC =1900 *1 / 23.92 =79.43143813

110 The N value is set to 79, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24: NUM=0.43143813* 2^24=7238330. Converting N and NUM into binary results in the following: N=0 0100 1111 NUM=0110 1110 0111 0010 1011 1010 So the registers would be programmed: P2_N=0 0100 1111 P2_NUM_MSB=0110 1110 0111 0010 P2_NUM_LSB=1011 1010 For VCO frequency 1930 MHz: FVCO =1930 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC=1930 *1 / 23.92 =80.68561873 The N value is set to 80, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24 NUM=0.68561873* 2^24=11502773. Converting N and NUM into binary results in the following N=0 0101 0000 NUM=1010 1111 1000 0100 1011 0101 So the registers would be programmed P2_N=0 0101 0000

111 P2_NUM_MSB=1010 1111 1000 0100 P2_NUM_LSB=1011 0101 For VCO frequency 1960 MHz: FVCO =1960 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC=1960 *1 / 23.92 =81.93979933 The N value is set to 81, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24: NUM=0.93979933* 2^24=15767216. Converting N and NUM into binary results in the following N=0 0101 0001 NUM=1111 0000 1001 0110 1011 0000 So the registers would be programmed P2_N=0 0101 0001 P2_NUM_MSB=1111 0000 1001 0110 P2_NUM_LSB=1011 0000 For VCO frequency 2.1 GHz: FVCO =2100 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC =2100 *1 / 23.92 =87.79264214

112 The N value is set to 87, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24: NUM=0.79264214* 2^24=13298328. Converting N and NUM into binary results in the following N=0 0101 0111 NUM=1100 1010 1110 1010 1001 1000 So the registers would be programmed P2_N=0 0101 0111 P2_NUM_MSB=1100 1010 1110 1010 P2_NUM_LSB=1001 1000 For VCO frequency 2.56 GHz FVCO =2560 MHz FOSC =23.92 MHz NEFF=FVCO *R / FOSC =2560 *1 / 23.92 =107.0234114 The N value is set to 107, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 2^24: NUM=0.0234114* 2^24=392777 Converting N and NUM into binary results in the following: N=0 0110 1011 NUM=0101 1111 1110 0100 1001

113 So the registers would be programmed: P2_N=0 0110 1011 P2_NUM_MSB=0000 0101 1111 1110 P2_NUM_LSB=0100 1001 Figure 5.4 Data Format send to RF2052 from ARM Controller

114 Figure 5.4 shows the data transmitted to RF2052 from ARM Controller. This hexadecimal numbers are computed values of N and NUM (integer and fractional value multiplied by 2 24, of NEFF) for the different frequencies. In the RF2052, these values are decoded to get the frequency value to be tuned. 5.1.2 Estimation of Signal Strength using Si 4362 The Si4362 is a high performance, low current, wireless ISM receiver that covers major sub-ghz bands. The wide operating voltage range of 1.8 3.6 V and low current consumption make the Si4362 an ideal solution for battery powered applications. This device uses a single-conversion mixer to down convert the 2/4-level FSK/GFSK or OOK/ASK modulated receive signals to a low intermediate frequency (IF). Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance ΔΣ ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receiver s performance and flexibility versus analog based architectures. The demodulated signal is output to the system ARM processor through a programmable GPIO or via the standard Serial periparal interface(spi) bus by reading the 64-byte RX FIFO. The computed signal strength values and the corresponding frequency values using Si4362 are sending to the ARM Processor using SPI bus. A sample data format received by ARM controller from

115 Si4362 is shown in Figure.5.5. The signal strength and the frequency values are coded in hexadecimal number system. Figue.5.5 Signal strength and frequency values (coded in hexadecimal system) received by ARM Controller from Si4362

116 5.1.3 ARM Controller In the proposed system, ARM 32-bit (LPC2148) controller is used. The LPC2148 is an ARM based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM is a next generation core that offers system enhancements such as modernized debug features and a higher level of support block integration. The ARM offers many new features, including a powerful instruction set, low interrupt latency, hardware divide, interruptible/continual multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. The ARM Central Processing Unit (CPU) incorporates a 3-stage pipeline and uses Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. This microcontroller has a clock speed up to 120 MHz which is sufficient for real time and industrial applications. The LPC2148 contains up to 512-Kbyte of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. Advanced Microcontroller Bus Architecture (AMBA) and Advanced High Performance Bus (AHB) are used for sending and receiving data. It supports low power on-chip communication. The LPC2148 contain a total of 64-kbyte on-chip static RAM memory. This includes the main 32-Kbyte SRAM, accessible by the

117 CPU and DMA controller on a higher-speed bus, and two additional 16 Kbyte each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. The LPC2148 has a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. In the proposed work, this ARM controller is used to, 1. Get the values of centre frequency and frequency span from the Display section the display section provides the interface between the user and the system. When the user enters a centre frequency and frequency span, then these values are received by the ARM controller to process the user request. 2. Compute the tuning frequency value using fractional N algorithm, and will send this to RF2052 from the centre frequency and frequency span values needed by the user, the ARM computes the frequency to which the received RF signal is to be tuned, using fractional N algorithm. The fractional N algorithm results in N and NUM (corresponding to integer and floating values of NEFF) values which are the coded values to represent the tuning frequency value. The computed N and NUM values (computations are presented in Figure 5.4 fractional N PLL) will be sent to RF2052 which can determine the tuning frequency from the reverse operation of fractional N algorithm, from N and NUM (Figure 5.4).

118 3. Receive the signal strength and frequency values from the Si4362 and send the same details to display section the Si4362 estimates the strength of the signal fed by RF2052, and sends the signal strength values coded in digital format (Figure.5.5) to the ARM controller. 1. Compare the received signal strength values with the safety radiation standards prescribed by the FCC, and it transmits the same data to the display section. 5.1.4 Data Transfer Module The data transfer from the ARM controller and the display section and vice versa, by using CP2102. CP 2102 The CP2102 is a highly-integrated USB-to-UART Bridge Controller providing a simple solution for updating RS-232 designs to USB using a minimum of components and PCB space. The CP2102 includes a USB 2.0 full speed function controller [77], USB transceiver, oscillator, EEPROM or EPROM, and asynchronous serial data bus (UART) with full modem control signals in a compact 5 x 5 mm QFN-28 package. The Universal Serial Bus function controller in the CP2102/9 is a USB 2.0 compliant full-speed device with integrated transceiver and on-chip matching and pull-up resistors. The USB function controller manages all data transfers between the USB and the UART as well as

119 command requests generated by the USB host controller and commands for controlling the function of the UART. The CP2102 is, a bridge connecting UART of the microcontroller and USB connector of PC. The device connects to the universal asynchronous receive, transmit (UART) of the microcontroller and the UART signals are converted to conform to the USB2 standard and transmitted through a Type B USB connector interfaced with PC. 5.1.5 Display section The display section completely related to CDEEC-RF PC Client (Visual Basic 2010) software. The CP2102 through USB cable is connected to the computer system. In computer system virtual communication port is connected to the USB through which computer system accesses the data.

120 Figure 5.6 CDEEC-RF PC Client (visual basic 2010) Once the Advanced embedded electromagnetic radiation monitoring system is connected, the data is accessed through serial communication port with a band rate of 50 kbps. The accessed data is fed to visual basic software which process the received data to interpret the data as graphs plotted between the signal strength and the frequency. The display module is sectioned into the following: (a) Mode Selection section (b) Frequency Selector section (c) RF Live Data

121 (a) Mode Selection section The mode selection is a part of the display section to select the running time data and hold time data. The running time selection is to select Real time/average/max peak/minimum modes of data. 1. In the real time mode, the system plots the graph of currently receiving signal strength versus the frequency selected by the user. 2. The system presents the graphical interpretation of the computed average value of the signal strength over some sort of time as a function frequency of operation. 3. The maximum or peak value of the received signal strength in a fixed duration of time, will be displayed as a function of frequency requested by the user. 4. The system displays the minimum level of signal strength observed over a fixed time, as a function of frequency needed by the user. In this manner, the mode selection of running time data displays the appropriate graph of signal strength and frequency. By selecting the hold time data mode, the running display of graphical representation of radiation will be paused.

122 (b) Frequency Selector section The frequency selector section is the crucial part of the AEERMS. In this section, the user is allowed to request the desired central frequency and the frequency span, to measure the radiation level at that particular frequency. On providing the centre frequency and frequency span, the system will automatically selects the starting and ending frequencies. For example, if the centre frequency and frequency span are selected as 1800 MHz and 40 MHz respectively, the system computes the starting frequency as 1780 MHz (= 1800 40/2) and the ending frequency as 1820 MHz (=1800+40/2). These frequency values are sent to RF2052 via ARM controller using fractional N algorithm, to tune the receiving signal to be in this range. The signal strength and the corresponding frequency values are estimated using the IC Si4362 and send these values to ARM controller. The ARM controllers send this information to display section via CP2102 and USB to process further. (c) RF-Live Data The signal strength and frequency values sent from ARM controller, will be stored in the excel files. The RF-LIVE Data section interprets this data graphically by plotting the running graph between the signal strength values in dbm (Y axis) and the selected frequency in MHz (X axis). Also, it is capable of plotting the total radiated power (dbm) in the complete frequency band (MHz) of the antenna.

123 5.1.6 GSM Module The GSM module is connected to the system through virtual serial communication in similar to ARM controller interfacing with PC. The GSM module consists of a subscriber identity module (SIM) to facilitate sending Short Message Service (SMS) from this unit to the concerned officers informing danger level of radiation [79]. The ARM controller continuously compares the received signal strength values from the Si4363, with the safety radiation limits prescribed by the FCC. If it founds the received signal strength value exceeds the safety limit, it will automatically activate the GSM module to send an SMS to the concern authorities about the hazardous level of radiation of a particular frequency at a particular place. 5.2 CHAPTER SUMMARY In this chapter, a detailed discussion about the each component of the designed Advanced Embedded Electromagnetic Radiation Monitoring System (AEERMS) is carried out. Also, explained clearly the functionality of the proposed system. Results obtained by using this device will be discussed in the next chapter.