Programmable Timing Control Hub for P4

ICS9598 Programmable Timing Control Hub for P4 Recommended Application: VIA Pro266/PN266/CLE266/CM4 chipset for PIII/Tualatin/C3 Processor Output Features: - Pair of differential CPU clocks @ 3.3V (CK48)/ - Pair of differential open drain CPU clocks (K7) 2 - Push pull CPUT_CS clocks @ 2.5V 3 - AGP @ 3.3V 7 - PCI @ 3.3V - 48MHz @ 3.3V fixed - 24_48MHz @ 3.3V 2 - REF @ 3.3V, 4.38MHz Key Specifications: CPU_CS - CPUT/C: <±25ps CPU_CS - AGP: <±25ps CPU - DDR/SD: <±25ps PCI - PCI: <5ps Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Frequency Table FS3 FS2 FS FS MULTISEL Board Target Trace/Term Z 5 ohms 5 ohms CPUCLK MHz Reference R, Iref = /(3*Rr V D D ) Rr = 22 %, Iref = 5.mA Rr = 475 %, Iref = 2.32mA AGP MHz Output Current PCICLK MHz 6. 8. 4. 64. 82. 4. 66.6 66.6 33.3 7. 68. 34. 75. 7. 35. 8. 72. 36. 85. 74. 37. 9. 76. 38. 66.8 66.8 33.4.9 67.27 33.63 33.6 66.8 33.4 2.4 66.8 33.4 66.6 66.6 32.3. 66.6 33.3 2. 66.6 33.3 33.3 66.6 33.3 Voh @ Z Ioh = 4* I REF.V @ 5 Ioh = 6* I REF.7V @ 5 *FS/REF GND 2 3 2 4 VDDAGP 5 *MODE/AGPCLK 6 *SEL_48/K7/AGPCLK 7 *(PCI_STOP#)AGPCLK2 8 GNDAGP 9 **FS/PCICLK_F **SEL_SDR/DDR#/PCICLK *MULTSEL/PCICLK2 2 GNDPCI 3 PCICLK3 4 PCICLK4 5 VDDPCI 6 PCICLK5 7 *(CLK_STOP#)/PCICLK6 8 GND48 9 *FS3/48MHz 2 *FS2/24_48MHz 2 AVDD48 22 VDD 23 GND 24 IREF 25 *(PD#)RESET# 26 SCLK 27 SDATA 28 Pin Configuration ICS9598 56 Vtt_PWRGD#**/REF 55 VDDREF 54 GND 53 CPUCLKT/CPUCLKODT 52 CPUCLKC/CPUCLKODC 5 VDDCPU3.3 5 VDDCPU2.5 49 CPUT_CS 48 CPUT_CS 47 GND 46 FBOUT 45 BUF_IN 44 DDRT/SDRAM 43 DDRC/SDRAM 42 DDRT/SDRAM2 4 DDRC/SDRAM3 4 VDD3.3_2.5 39 GND 38 DDRT2/SDRAM4 37 DDRC2/SDRAM5 36 DDRT3/SDRAM6 35 DDRC3/SDRAM7 34 VDD3.3_2.5 33 GND 32 DDRT4/SDRAM8 3 DDRC4/SDRAM9 3 DDRT5/SDRAM 29 DDRC5/SDRAM * Internal 2K pull-up resistor to VDD. ** Internal 2K pull-down resistor to GND. 56-Pin 3-mil SSOP 653A 7/26/4 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

ICS9598 General The ICS9598 is a single chip clock solution for desktop designs using the VIA Pro266/PN266/CLE266/CM4 chipset with PC33 or DDR memory. The ICS9598 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to.mhz increment. Block Diagram (:) FBOUT Mode SEL_SDR/DDR# BUF_IN SEL_48/K7# Power Groups Pin Number VDD GND 55 2 tal, Ref 5 9 AGP [:2], CPU digital, CPU PLL 6 3 PCI [:5], PCI_F outputs 22 9 48MHz, Fix Digital, Fix Analog 23 24 Master clock, CPU Analog 34, 4 33, 39 DDR/SDR outputs 5 47 2.5V CPUT_CS output 5 54 3.3V CPUT/C & CPUOD_T/C 653A 7/26/4 2

ICS9598 Pin PIN PIN PIN # NAME TYPE DESCRIPTION *FS/REF I/O Frequency select latch input pin / 4.38 MHz reference clock. 2 GND PWR Ground pin. 3 IN Crystal input, Nominally 4.38MHz. 4 2 OUT Crystal output, Nominally 4.38MHz 5 VDDAGP PWR Power supply for AGP clocks, nominal 3.3V 6 *MODE/AGPCLK I/O Function select latch input pin, =Desktop Mode, =Mobile Mode / AGP clock output. 7 *SEL_48/K7/AGPCLK I/O CPU output type select latch input pin = K7, = CK48 / AGP clock output. 8 *(PCI_STOP#)AGPCLK2 I/O Stops all PCICLKs besides the PCICLK_F clocks at logic level, when input low. This input is activated by the MODE selection pin / AGP clock output. 9 GNDAGP PWR Ground pin for the AGP outputs **FS/PCICLK_F I/O Frequency select latch input pin / 3.3V PCI free running clock output. **SEL_SDR/DDR#/PCICLK I/O Memory type select latch input pin = DDR, = PC33 SDRAM / 3.3V PCI clock output. 2 *MULTSEL/PCICLK2 I/O 3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock output. 3 GNDPCI PWR Ground pin for the PCI outputs 4 PCICLK3 OUT PCI clock output. 5 PCICLK4 OUT PCI clock output. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK5 OUT PCI clock output. 8 *(CLK_STOP#)/PCICLK6 I/O Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic level, when input low. This input is activated by the MODE selection pin / PCI clock output. 9 GND48 PWR Ground pin for the 48MHz outputs 2 *FS3/48MHz I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 2 *FS2/24_48MHz I/O Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V. 22 AVDD48 PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V 23 VDD PWR Power supply, nominal 3.3V 24 GND PWR Ground pin. 25 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 26 *(PD#)RESET# I/O Asynchronous active low input pin used to power down the device into a low power state. This input is activated by the MODE selection pin / Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 27 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 28 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2 drive strength Pin description continued on next page. 653A 7/26/4 3

ICS9598 Pin Continued PIN PIN PIN # NAME TYPE DESCRIPTION 29 DDRC5/SDRAM OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 3 DDRT5/SDRAM OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 3 DDRC4/SDRAM9 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 32 DDRT4/SDRAM8 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 33 GND PWR Ground pin. 34 VDD3.3_2.5 PWR 2.5V or 3.3V nominal power supply voltage. 35 DDRC3/SDRAM7 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 36 DDRT3/SDRAM6 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 37 DDRC2/SDRAM5 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 38 DDRT2/SDRAM4 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 39 GND PWR Ground pin. 4 VDD3.3_2.5 PWR 2.5V or 3.3V nominal power supply voltage. 4 DDRC/SDRAM3 OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 42 DDRT/SDRAM2 OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 43 DDRC/SDRAM OUT "Complimentary" Clock of differential memory output / 3.3V SDRAM clock output 44 DDRT/SDRAM OUT "True" Clock of differential memory output / 3.3V SDRAM clock output 45 BUF_IN IN Input Buffers for memory outputs. 46 FBOUT OUT Memory feed back output. 47 GND PWR Ground pin. 48 CPUT_CS OUT True clock of differential pair 2.5V push-pull CPU outputs. 49 CPUT_CS OUT True clock of differential pair 2.5V push-pull CPU outputs. 5 VDDCPU2.5 PWR Power pin for the CPUCLKs. 2.5V 5 VDDCPU3.3 PWR Power pin for the CPUCLKs. 3.3V 52 CPUCLKC/CPUCLKODC OUT "Complementary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias / "Complementary" clocks of differential pair CPU outputs. These open drain outputs need an external.5v pull-up / 2.5V CPU clock output. 53 CPUCLKT/CPUCLKODT OUT "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias / "True" clocks of differential pair CPU outputs. These open drain outputs need an external.5v pull-up / 2.5V CPU clock output. 54 GND PWR Ground pin. 55 VDDREF PWR Ref, TAL power supply, nominal 3.3V 56 Vtt_PWRGD#**/REF I/O This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. / 4.38 MHz reference clock. Mode Pin - Power Management Input Control MODE, Pin 6 (Latched Input) Pin 26 Pin 8 Pin 8 PD# (Input) RESET# (Output) CPU_STOP# (Input) PCICLK5 (Output) PCI_STOP# (Input) AGP2 (Output) 653A 7/26/4 4

ICS9598 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) ACK ACK ACK ACK ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address D3 (H) RD ReaD ACK Data Byte Count = ACK Beginning Byte N ACK Byte N P Not acknowledge stop bit Byte N + - *See notes on the following page. 653A 7/26/4 5

ICS9598 Byte : Functionality and frequency select register (Default=) (2,7:4) 3 2 7 6 5 4 CPUCLK AGPCLK PCICLK FS3 FS2 FS FS MHz MHz MHz Spread % 2. 68. 34. +/-.3% Center Spread 5. 7. 35. +/-.3% Center Spread 8. 72. 36. +/-.3% Center Spread. 74. 27. +/-.3% Center Spread 4. 76. 38. +/-.3% Center Spread 7. 78. 39. +/-.3% Center Spread 2. 8. 4. +/-.3% Center Spread 23. 82. 4. +/-.3% Center Spread 26. 72. 36. +/-.3% Center Spread 3. 74.3 37. +/-.3% Center Spread 33.9 66.95 33.48 +/-.3% Center Spread 4. 7. 35. +/-.3% Center Spread 44. 72. 36. +/-.3% Center Spread 48. 74. 37. +/-.3% Center Spread 52. 76. 38. +/-.3% Center Spread 56. 78. 39. +/-.3% Center Spread 6. 8. 4. +/-.3% Center Spread 64. 82. 4. +/-.3% Center Spread 66.6 66.6 33.3 +/-.3% Center Spread 7. 68. 34. +/-.3% Center Spread 75. 7. 35. +/-.5% Center Spread 8. 72. 36. +/-.5% Center Spread 85. 74. 37. +/-.5% Center Spread 9. 76. 38. +/-.3% Center Spread 66.8 66.8 33.4 +/-.3% Center Spread.9 67.27 33.63 +/-.3% Center Spread 33.6 66.8 33.4 +/-.3% Center Spread 2.4 66.8 33.4 +/-.3% Center Spread 66.6 66.6 32.3 to -.6% Down Spread. 66.6 33.3 to -.6% Down Spread 2. 66.6 33.3 to -.6% Down Spread 33.3 66.6 33.3 to -.6% Down Spread - Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,7:4 - Normal - Spread spectrum enable - Running - Tristate all outputs Notes, 2 Notes:. Default at power-up will be for latched logic inputs to define frequency, as displayed by 3. 2. Bb2 default =. 653A 7/26/4 6

ICS9598 Byte : CPU Active/Inactive Register ( = enable, = disable) B it Pin# 7 29 SDRAM/DDRC5 (Active/Inactive ) 6 PCICLK_F (Active/Inactive ) 5 3 SDRAM/DDRT5 (Active/Inactive ) 4 3 SDRAM9/DDRC4 (Active/Inactive ) 3 49 CPUT_CS Free running control; = free running; = not free runnin g 2 32 SDRAM8/DDRT4 (Active/Inactive ) 53, 52 CPUCLKT/C (Active/Inactive ) 48 CPUCLKT_CS (Active/Inactive ) Byte 2: PCI Active/Inactive Register ( = enable, = disable) B it Pin# 7 46 FB_OUT Free running control; = free running; = not free runnin g 6 8 PCICLK5 (Active/Inactive ) 5 7 PCICLK4 (Active/Inactive ) 4 5 PCICLK3 (Active/Inactive ) 3 4 PCICLK2 (Active/Inactive ) 2 2 PCICLK (Active/Inactive ) PCICLK (Active/Inactive ) 53, 52 CPUCLKT/C Free running control; = free running; = not free runnin g Byte 3: Active/Inactive Register ( = enable, = disable) B it Pin# 7 46 F B_OUT (Active/Inactive ) 6 - SEL 24_48, =24Mhz =48MHz 5 - SD/DDR free running control; = free running; not free runnin g 4 56 R EF (Active/Inactive ) 3 48 CPUT_CS free running control; = free running; not free runnin g 2 8 A GPCLK 2 (Active/Inactive ) 7 AGPCLK (Active/Inactive ) 6 A GPCLK (Active/Inactive ) Byte 4: Frequency Select Active/Inactive Register ( = enable, = disable) B it Pin# 7 - Latched FS3 6 - Latched FS2 5 - Latched FS 4 - Latched FS 3 2 48MHz (Active/Inactive ) 2 2 24_48MHz (Active/Inactive ) 49 CPUT_CS (Active/Inactive ) REF (Active/Inactive ) 653A 7/26/4 7

ICS9598 Byte 5: Peripheral Active/Inactive Register ( = enable, = disable) B it Pin# 7 35 SDRAM7/DDRC3 (Active/Inactive ) 6 36 SDRAM6/DDRT3 (Active/Inactive ) 5 37 SDRAM5/DDRC2 (Active/Inactive ) 4 38 SDRAM4/DDRT2 (Active/Inactive ) 3 4 SDRAM3/DDRC (Active/Inactive ) 2 42 SDRAM2/DDRT (Active/Inactive ) 43 SDRAM/DDRC (Active/Inactive ) 44 SDRAM/DDRT (Active/Inactive ) Byte 6: Vendor ID Register ( = enable, = disable) 7 Revision ID 3 6 Revision ID 2 5 Revision ID 4 Revision ID 3 Vendor ID 3 (Reserved ) 2 Vendor ID 2 (Reserved ) Vendor ID (Reserved ) Vendor ID (Reserved ) Revision ID values will be based on individual device's revision Byte 7: Revision ID and Device ID Register 7 Device ID7 6 Device ID6 5 Device ID5 4 Device ID4 3 Device ID3 2 Device ID2 Device ID Device ID Device ID values will "h" in this case. be based on individual device Byte 8: Byte Count Read Back Register 7 Byte7 6 Byte6 5 Byte5 4 Byte4 3 Byte3 2 Byte2 Byte Byte Note: Writing to this register will configure byte count and how many bytes will be read back, default is F H = 5 bytes. 653A 7/26/4 8

ICS9598 Byte 9: Watchdog Timer Count Register 7 WD7 6 WD6 5 WD5 4 WD4 3 WD3 2 WD2 WD WD The decimal representation of these 8 bits correspond to 29ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 6 29ms = 4.6 seconds. Byte : Programming Enable bit 8 Watchdog Control Register 7 Programming Enable bit Program = no programming. Frequencies are selected by HW latches or Byte Enable 2 = enable all I C programing. 6 WD Enable Software Watchdog Enable bit. This bit will over write WDEN latched value. = disable, = Enable. 5 WD Alarm Watchdog Alarm Status = normal = alarm status 4 SF4 3 SF3 Watchdog safe frequency bits. Writing to these bits will configure the safe 2 SF2 frequency corrsponding to Byte 2, 7:4 table SF SF Byte : VCO Frequency M Divider (Reference divider) Control Register 7 Ndiv 8 N divider bit 8 6 Mdiv 6 5 Mdiv 5 4 Mdiv 4 The decimal respresentation of Mdiv (6:) corresposd to the 3 Mdiv 3 reference divider value. Default at power up is equal to the 2 Mdiv 2 latched inputs selection. Mdiv Mdiv Byte 2: VCO Frequency N Divider (VCO divider) Control Register 7 Ndiv 7 6 Ndiv 6 5 Ndiv 5 4 Ndiv 4 3 Ndiv 3 2 Ndiv 2 Ndiv Ndiv The decimal representation of Ndiv (8:) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte. 653A 7/26/4 9

ICS9598 Byte 3: Spread Spectrum Control Register 7 SS 7 6 SS 6 5 SS 5 4 SS 4 3 SS 3 2 SS 2 SS SS The Spread Spectrum (2:) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider. Byte 4: Spread Spectrum Control Register 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 SS 2 Spread Spectrum 2 3 SS Spread Spectrum 2 SS Spread Spectrum SS 9 Spread Spectrum 9 SS 8 Spread Spectrum 8 Byte 5: Output Divider Control Register 7 CPU Div 3 6 CPU Div 2 5 CPU Div 4 CPU Div 3 CPU Div 3 2 CPU Div 2 CPU Div CPU Div CPUCLKC/T clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. CPUCLKT_CS clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. Byte 6: Output Divider Control Register 7 AGP Div 3 6 AGP Div 2 5 AGP Div 4 AGP Div 3 Reserved - 2 Reserved - Reserved - Reserved - AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table. Default at power up is latched FS divider. Reserved 653A 7/26/4

ICS9598 Byte 7: Output Divider Control Register 7 AGP_INV AGP Phase Inversion bit 6 Reserved Reserved 5 CPU_INV CPU T/C Phase Inversion bit 4 CPU_INV CPUT/C_CS Phase Inversion bit 3 PCI Div 3 2 PCI Div 2 PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. PCI Div Default at power up is latched FS divider. PCI Div Table Table 2 Div (3:2) Div (:) / 2 / 4 / 8 /6 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 7 / 4 / 28 /56 Div (3:2) Div (:) / 4 / 8 / 6 /32 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 9 / 8 / 36 /72 Byte 8: Group Skew Control Register 7 CPUCLKT_CS These 2 bits delay the CPUCLKT/C_CS with respect to Group Skew CPUCLKT_CS 6 Control = ps = 25ps = 5ps =75ps 5 CPUCLKT/ C hese 2 bits delay the CPUCLKT/ C clock with respect to Group Skew CPUCLKT/C_CS 4 Control = ps = 25ps = 5ps = 75ps 3 AGPCLK These 2 bits delay the AGPCLK clocks with respect to CPUCLK Group Skew 2 = ps = 25ps = 5ps = 75ps Control Reserved Reserved Reserved Reserved Byte 9: Group Skew Control Register 7 6 Reserved 5 Reserved 4 3 PCICLK(5:) These 4 bits can change the CPU to PCI (5:) skew from.4ns - 2 2.9ns. Default at power up is - 2.5ns. Each binary increment or Group Skew decrement of s (3:) will increase or decrease the delay of the Control PCI clocks by ps. 653A 7/26/4

ICS9598 Byte 2: Group Skew Control Register 7 These 4 bits can change the CPU to PCIF skew from.4ns - PCICLK_F 6 2.9ns. Default at power up is - 2.5ns. Each binary increment or Group Skew 5 decrement of (3:) will increase or decrease the delay of the Control 4 PCI clocks by ps. 3 2 Reserved Reserved Byte 2: Slew Rate Control Register 7 6 Reserved 5 Reserved 4 3 CPUCLKT/ C CPUCLKT/C OD/CS clock slew rate control bits. 2 OD/CS = strong: = normal; = weak AGP_ AGP_ clock slew rate control bits. Slew Rate Control = strong: = normal; = weak Byte 22: Slew Rate Control Register B it 7 AGP(2:) AGP(2:) clock slew rate control bits. 6 Slew Rate Control = strong: = normal; = weak 5 PCICLK_ F PCICLK_F clock slew rate control bits. 4 Slew Rate Control = strong: = normal; = weak B it 3 PCICLK(7:4 ) PCICLK(7:4) clock slew rate control bits. 2 Slew Rate Control = strong: = normal; = weak B it PCICLK(3: ) PCICLK(3:) clock slew rate control bits. Slew Rate Control = strong: = normal; = weak Byte 23: Slew Rate Control Register B it 7 REF (:) REF clock slew rate control bits. 6 Slew Rate Control = strong: = normal; = weak 5 Reserved 4 Reserved 3 48MHz 48MHz clock slew rate control bits. 2 Slew Rate Control = strong: = normal; = weak 24_48MHz 24_48MHz clock slew rate control bits. Slew Rate Control = strong: = normal; = weak 653A 7/26/4 2

ICS9598 Absolute Maximum Ratings Supply Voltage................................ 5.5 V Logic Inputs.................................. GND.5 V to V DD +.5 V Ambient Operating Temperature................. C to +7 C Case Temperature............................. 5 C Storage Temperature........................... 65 C to +5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS -.3.8 V Input High Current I IH V IN = V DD -5 5 ma Input Low Current I IL V IN = V; Inputs with no pull-up resistors -5 ma Input Low Current I IL2 V IN = V; Inputs with pull-up resistors -2 ma Operating C L = pf; Select @ 66M ma I DD3.3OP Supply Current C L = Full load 28 ma Power Down IREF=2.32 2 ma I Supply Current DD3.3PD IREF= 5mA 37 ma Input frequency F i V DD = 3.3 V; MHz Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C out Out put pin capacitance 6 pf C IN & 2 pins 27 45 pf Transition Time T trans To st crossing of target Freq. 3 ms Settling Time T s From st crossing to % target Freq. 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target Freq. 3 ms Delay t PZH,t PZH output enable delay (all outputs) ns t PLZ,t PZH output disable delay (all outputs) ns Guaranteed by design, not % tested in production. 653A 7/26/4 3

ICS9598 Electrical Characteristics - CPUCLKC/T T A = - 7º C; V DD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Current Source Output Impedance Z O V O = V 3 W Output High Voltage V OH.7.2 V V R = 475Ω +%; IREF = 2.32mA; I OH = 6*IREF Output High Current I OH -3.92 ma Rise Time t r V OL = 2%, V OH = 8% 75 7 ps Differential Crossover Voltage V Note 3 45 5 55 % Duty Cycle d t V T = 5% 45 5 55 % Skew, CPU to CPU t sk V T = 5% 5 ps Jitter, Cycle-to-cycle t jcyc-cyc V T = V 2 ps Notes: - Guaranteed by design, not % tested in production. Electrical Characteristics - CPUCLKT/C_CS T A = - 7ÜC; V DD = 2.5 V +/-5%; C L = 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH2B I OH = -2. ma 2 V Output Low Voltage V OL2B I OL = 2 ma.4 V Output High Current I OH2B V OH =.7 V -9 ma Output Low Current I OL2B V OL =.7 V 9 ma Rise Time t r2b V OL =.4 V, V OH = 2. V.6 ns Differential Crossover Voltage V Note 3 45 5 55 % Duty Cycle d t2b V T =.25 V 45 55 % Skew t sk2b V T =.25 V 75 ps Jitter, Cycle-to-cycle t jcyc-cyc2b V T =.25 V 25 ps Jitter, One Sigma t js2b V T =.25 V 5 ps Jitter, Absolute t jabs2b V T =.25 V -25 +25 ps Guaranteed by design, not % tested in production. 653A 7/26/4 4

ICS9598 Electrical Characteristics - SDRAM T A = - 7 C; V DD = 3.3V +/-5%, V DDL = 2.5V +/-5%; C L = 3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH3 I OH = -28 ma 2.4 V Output Low Voltage V OL3 I OL = 2 ma.4 V Output High Current I OH3 V OH = 2. V -4 ma Output Low Current I OL3 V OL =.8 V 4 ma Rise Time t r3 V OL =.4 V, V OH = 2.4 V 2 ns Fall Time t f3 V OH = 2.4 V, V OL =.4 V 2 ns Duty Cycle d t3 V T =.5 V 45 55 % Skew window t sk3 V T =.5 V 25 ps Propagation Time (Buffer In to Output) Tprop V T =.5 V 5 ns Guaranteed by design, not % tested in production. Electrical Characteristics - DDRT/C T A = - 7 C; V DDL = 2.5 V +/-5%, C L = 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH3 I OH = - ma 2 V Output Low Voltage V OL3 I OL = ma.4 V Output High Current I OH3 V OH = 2. V -2 ma Output Low Current I OL3 V OL =.8 V 2 ma Rise Time T r3 2% to 8% 2.2 ns Fall Time T f3 8% to 2% 2.2 ns Duty Cycle D t3 V T = 5% 47 53 % Skew (window) T sk VT = 5% 25 ps Jitter t jcyc-cyc V T =.25 V 25 ps 653A 7/26/4 5

ICS9598 Electrical Characteristics - PCICLK T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F 33.33 MHz Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V -33-33 ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA=.4 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V 45 55 % Skew t sk V T =.5 V 5 ps Jitter t jcyc-cyc V T =.5 V 25 ps Guaranteed by design, not % tested in production. Electrical Characteristics - AGP T A = - 7 C; V DD = 3.3 V +/-5%; C L =-3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O 66.66 MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V -33-33 ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA=.4 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V 45 55 % Skew t sk V T =.5 V 5 ps Jitter tjcyc-cyc V T =.5 V 25 ps Guaranteed by design, not % tested in production. 653A 7/26/4 6

ICS9598 Electrical Characteristics - 48MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O V O = V DD *(.5) 48 MHz Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V -29-23 ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA=.4 29 27 ma 48DOT Rise Time t r V OL =.4 V, V OH = 2.4 V.5 ns 48DOT Fall Time t f V OH = 2.4 V, V OL =.4 V.5 ns VCH 48 USB Rise Time t r V OL =.4 V, V OH = 2.4 V 2 ns VCH 48 USB Fall Time tf V OH = 2.4 V, V OL =.4 V 2 ns 48 DOT to 48 USB Skew tskew VT=.5V ns Duty Cycle d t V T =.5 V 45 55 % Jitter t jcyc-cyc V T =.5 V 35 ps Guaranteed by design, not % tested in production. Electrical Characteristics - REF T A = - 7 C; V DD = 3.3 V +/-5%; C L =-2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 6 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH VOH@ MIN =. V, VOH@ MA = 3.35 V -29-23 ma Output Low Current I OL VOL@ MIN =.95 V, VOL@ MA=.4 29 27 ma Rise Time t r V OL =.4 V, V OH = 2.4 V 4 ns Fall Time t f V OH = 2.4 V, V OL =.4 V 4 ns Duty Cycle d t V T =.5 V 45 55 % Jitter t jcyc-cyc V T =.5 V 5 ps Guaranteed by design, not % tested in production. 653A 7/26/4 7

ICS9598 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 653A 7/26/4 8

ICS9598 Power Down Waveform ns 25ns 5ns VCO Internal 2 CPU MHz 3.3V 66MHz PCI 33MHz APIC 6.7MHz PD# SDRAM MHz REF 4.38MHZ 48MHZ Note. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for MHz 653A 7/26/4 9

ICS9598 ns ns 2ns 3ns 4ns Cycle Repeats CPU 66MHz CPU MHz CPU 33MHz SDRAM MHz SDRAM 33MHz 3.5V 66MHz PCI 33MHz APIC 6.7MHz REF 4.38MHz USB 48MHz Group Offset Waveforms 653A 7/26/4 2

ICS9598 INDE AREA N 2 D E A E h x 45 c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A 2.4 2.8.95. A.2.4.8.6 b.2.34.8.35 c.3.25.5. D SEE VARIATIONS SEE VARIATIONS E.3.68.395.42 E 7.4 7.6.29.299 e.635 BASIC.25 BASIC h.38.64.5.25 L.5.2.2.4 N SEE VARIATIONS SEE VARIATIONS α 8 8 e b A -C- - SEATING PLANE. (.4) C VARIATIONS D mm. D (inch) N MIN MA MIN MA 56 8.3 8.55.72.73 Reference Doc.: JEDEC Publication 95, MO-8-34 Ordering Information Example: 653A 7/26/4 ICS9598yFLF-T ICS y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 2

ICS9598 INDE AREA A2 e N 2 D b E E A A c -C- - SEATING PLANE aaa C α L 56-Lead 6. mm. Body,.5 mm. Pitch TSSOP (24 mil) (2 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A --.2 --.47 A.5.5.2.6 A2.8.5.32.4 b.7.27.7. c.9.2.35.8 D E SEE VARIATIONS 8. BASIC SEE VARIATIONS.39 BASIC E 6. 6.2.236.244 e.5 BASIC.2 BASIC L.45.75.8.3 N SEE VARIATIONS SEE VARIATIONS a 8 8 aaa --. --.4 VARIATIONS D mm. D (inch) N MIN MA MIN MA 56 3.9 4..547.555 Reference Doc.: JEDEC Publication 95, MO-53-39 Ordering Information Example: ICS9598yGLF-T ICS y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 653A 7/26/4 22