Programmable Timing Control Hub for PII/III

Transcription

1 ICS9558 Programmable Timing Control Hub for PII/III Recommended Application: 8/8E/85 and 85 B-Step type chipset Output Features: V V 3.3V /48MHz@ 3.3V - 3.3V fixed MHz Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Key Specifications: CPU Output Jitter: <25ps IOAPIC Output Jitter: <5ps 48MHz, 3V66, PCI Output Jitter: <5ps Ref Output Jitter. <ps CPU Output Skew: <75ps PCI Output Skew: <5ps 3V66 Output Skew <75ps For group skew timing, please refer to the Group Timing Relationship Table. VDDREF X X2 3V66_ 3V66_ 3V66_2 VDD3V66 VDDPCI *FS/PCICLK *FS/PCICLK *SEL24_48#/PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 Vtt_PWRGD/PD# SCLK SDATA VDDSDR SDRAM SDRAM Block Diagram X X2 Pin Configuration ICS REF/FS4 * VDDLAPIC IOAPIC VDDLCPU CPUCLK CPUCLK SDRAM SDRAM SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM_F VDDSDR 24_48MHz/FS2* 48MHZ/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 56-Pin 3-mil SSOP. These pins will have.5 to 2X drive strength. * Internal Pull-up resistor of 2K to VDD PLL2 XTAL OSC / 2 48MHz 24_48MHz REF PLL Spread Spectrum CPU DIVDER 2 CPUCLK (:) SDRAM DIVDER 2 SDRAM (:) FS(4:) PD# SEL24_48# Vtt_PWRGD SDATA SCLK Control Logic Config. Reg. IOAPIC DIVDER PCI DIVDER 8 SDRAM_F IOAPIC PCICLK (7:) 3V66 DIVDER 3 3V66 (2:) 47E 4/6/5

2 ICS9558 General The ICS9558 is a single chip clock solution for desktop designs using the 8/8E, 85 and 85 B-Step style chipset. It provides all necessary clock signals for such a system. The ICS9558 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to.mhz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple. Pin PIN 47E 4/6/5 NUMBER, 9,, 8, 25, 32, 33, 37, 45 VDD 2 X 3 X2 PIN NAME TYPE PWR IN OUT 4, 5, 4, 2, 28, 29, 36, 4, 49 PWR 8, 7, 6 3V66 (2:) OUT 2 3 PCICLK OUT FS PCICLK OUT FS SEL_24_48# PCICLK2 OUT 2, 9, 7, 6, 5 PCICLK (7:3) 3.3V power supply DESCRIPTION Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 4.38MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3.3V Fixed 66MHz clock outputs for HUB 3.3V PCI clock output, with Synchronous CPUCLKs I N Logic input frequency select bit. Input latched at power on. 3.3V PCI clock output, with Synchronous CPUCLKs I N Logic input frequency select bit. Input latched at power on. I N Logic input to select output. OUT 3.3V PCI clock output, with 3.3V PCI clock outputs, with Synchronous CPUCLKs Synchronous CPUCLKs PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down 22 will not be greater than 3ms. This pin acts as a dual function input pin for Vtt_PWRGD and Vtt_PWRGD IN PD# signal. When Vtt_PWRGD goes high the frequency select will be latched at power on; thereafter the pin is an asynchronous active low power down pin. 23 SCLK IN 2 Clock pin for I C circuitry 5V tolerant 24 SDATA I/ O 2 Data pin for I C circuitry 5V tolerant 34 FS3 I N Logic input frequency select bit. Input latched at power on. 48MHz OUT 3.3V Fixed 48MHz clock output for USB FS2 I N Logic input frequency select bit. Input latched at power on V 24_48MHz output, selectable through pin 3, default is 24_48MHz OUT 24MHz. 38 SDRAM_ F OUT 3.3V SDRAM output can be turned off through I 2 C 48, 46, 47, 44, 43, 42, 4, 39, 3, 3, 27, 26 SDRAM (:) OUT 3.3V output. All SDRAM outputs can be turned off through I 2 C 5 L PWR Ground for 2.5V power supply for CPU & APIC 5, 52 CPUCLK (:) OUT 2.5V Host bus clock output. Output frequency derived from FS pins. 53, 55 VDDL PWR 2.5V power suypply for CPU, IOAPIC 54 IOAPIC O UT 2.5V clock outputs running at 6.67MHz. 56 FS4 I N Logic input frequency select bit. Input latched at power on. REF O UT 3.3V, 4.38MHz reference clock output. 2

3 ICS9558 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X - ICS clock sends Byte through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Byte N + X - P stop bit X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD Data Byte Count = X Beginning Byte N X Byte N P Not acknowledge stop bit Byte N + X - *See notes on the following page. 47E 4/6/5 3

4 ICS9558 Byte : Functionality and frequency select register (Default=) (2,7:4) FS4 FS3 FS2 FS FS CPUCLK MHz SDRAM MHz Notes:. Default at power-up will be for latched logic inputs to define frequency, as displayed by 3. 3V66 MHz PCICLK MHz IOAPIC MHz Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,7:4 - Normal - Spread spectrum enable ±.35% Center Spread - Running - Tristate all outputs Note 47E 4/6/5 4

5 ICS9558 Byte : Output Control Register ( = enable, = disable) B it Pin# 7 - X Readback FS3# 6 - X Readback FS# 5 - X Readback FS2# MHz 3 - (Reserved) MHz - (Reserved) 38 SDRAM_ F Byte 2: Output Control Register ( = enable, = disable) B it Pin# 7 39 SDRAM7 6 4 SDRAM SDRAM SDRAM SDRAM SDRAM2 47 SDRAM 48 SDRAM Byte 3: Output Control Register ( = enable, = disable) B it Pin# 7 2 PCICLK7 6 9 PCICLK6 5 7 PCICLK5 4 6 PCICLK4 3 5 PCICLK3 2 3 PCICLK2 2 PCICLK PCICLK Byte 4: Output Control Register ( = enable, = disable) B it Pin# 7 8 3V66_ V66_ 5 7 3V66_ 4 - X Readback FS4# 3 54 IOAPIC 2 - X Readback FS# 5 CPUCLK 52 CPUCLK 47E 4/6/5 5

6 ICS9558 Byte 5: Output Control Register B it Pin# 7 - X Readback (SEL24, 48#) # 6 - (Reserved) 5 - (Reserved) 4 - (Reserved) 3 26 SDRAM 2 27 SDRAM 3 SDRAM9 3 SDRAM8 Byte 6: Vendor ID Register 7 - X (Reserved) 6 - X (Reserved) 5 - X (Reserved) 4 - X (Reserved) 3 - X (Reserved) 2 Vendor ID2 Vendor ID ICS vendor ID is as in number in frequency timing generation. Vendor ID Byte 7: Revision ID and Device ID Register 7 Revision ID2 6 Revision ID 5 Revision ID 4 Device ID4 3 Device ID3 2 Device ID2 Device ID Device ID Device ID and Revision ID values will be based on individual device and it's revisio, "h" in this case. Byte 8: Byte Count Read Back Register 7 Byte7 6 Byte6 5 Byte5 4 Byte4 3 Byte3 2 Byte2 Byte Byte Note: Writing to this register will configure byte count and how many bytes will be read back, default is FH = 5 bytes. 47E 4/6/5 6

7 ICS9558 Byte 9: Watchdog Timer Count Register 7 WD7 6 WD6 5 WD5 4 WD4 3 WD3 2 WD2 WD WD The decimal representation of these 8 bits correspond to X 29ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 6 29ms = 4.6 seconds. Byte : Programming Enable bit 8 Watchdog Control Register 7 Programming Enable bit Program Enable = no programming. Frequencies are selected by HW latches or Byte 2 = enable all I C programing. 6 WD Enable Watchdog Enable bit 5 WD Alarm Watchdog Alarm Status = normal = alarm status 4 SF4 3 SF3 Watchdog safe frequency bits. Writing to these bits 2 SF2 will configure the safe frequency corrsponding to SF Byte 2, 7:4 table SF Byte : VCO Frequency M Divider (Reference divider) Control Register 7 Ndiv 8 X N divider bit 8 6 Mdiv 6 X 5 Mdiv 5 X 4 Mdiv 4 X The decimal respresentation of Mdiv (6:) corresposd to the 3 Mdiv 3 X reference divider value. Default at power up is equal to the latched 2 Mdiv 2 X inputs selection. Mdiv X Mdiv X Byte 2: VCO Frequency N Divider (VCO divider) Control Register 7 Ndiv 7 6 Ndiv 6 5 Ndiv 5 4 Ndiv 4 3 Ndiv 3 2 Ndiv 2 Ndiv Ndiv X X X X X X X X The decimal representation of Ndiv (8:) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte. 47E 4/6/5 7

8 ICS9558 Byte 3: Spread Spectrum Control Register 7 S S 7 X The Spread Spectrum (2:) bit wil 6 SS 6 X program the spread precentage. Spread l 5 SS 5 X precent needs to be calculated based on 4 SS 4 X the VCO frequency, spreading profile, spreading amount and spread frequency. It 3 SS 3 X is recommended to use the ICS spread 2 SS 2 X programming guide for spread SS X programming. Default power on is latched SS X FS divider. Byte 4: Spread Spectrum Control Register 7 Reserved X Reserved 6 Reserved X Reserved 5 Reserved X Reserved 4 SS 2 X Spread Spectrum 2 3 SS X Spread Spectrum 2 SS X Spread Spectrum SS 9 X Spread Spectrum 9 SS 8 X Spread Spectrum 8 Byte 5: Output Divider Control Register 7 SD Div 3 X SDRAM clock divider ratio can be 6 SD Div 2 X configured via these 4 bits individually. For divider selection table refer to 5 SD Div X Table. Default at power up is latched 4 SD Div X FS divider. 3 CPU Div 3 X CPU clock divider ratio can be 2 CPU Div 2 X configured via these 4 bits individually. For divider selection table refer to CPU Div X Table. Default at power up is latched CPU Div X FS divider. Byte 6: Output Divider Control Register 7 PCI Div 3 X PCI clock divider ratio can be 6 PCI Div 2 X configured via these 4 bits individually. For divider selection table refer to 5 PCI Div X Table 2. Default at power up is latched 4 PCI Div X FS divider. 3 AGP Div 3 X AGP clock divider ratio can be 2 AGP Div 2 X configured via these 4 bits individually. For divider selection table refer to AGP Div X Table. Default at power up is latched AGP Div X FS divider. 47E 4/6/5 8

9 ICS9558 Byte 7: Output Divider Control Register 7 PCI_INV X PCICLK Phase Inversion bit 6 3V66_INV X 3V66 Phase Inversion bit 5 SD_INV X SDRAM Phase Inversion bit 4 CPU_INV X CPUCLK Phase Inversion bit 3 APIC Div 3 X IOAPIC clock divider ratio can be 2 APIC Div 2 X configured via these 4 bits individually. For APIC Div X divider selection table refer to table 2. APIC Div X Default at power up is latched FS divider. Table Table 2 Div (3:2) Div (:) / 2 / 4 / 8 /6 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 7 / 4 / 28 /56 Div (3:2) Div (:) / 4 / 8 / 6 /32 / 3 / 6 / 2 /24 / 5 / / 2 /4 / 9 / 8 / 36 /72 Byte 8: Group Skew Control Register it 7 SD_Skew These 2 bits delay the SDRAM with respect to CPUCLK SD_Skew = ps = 25ps = 5ps =75ps Reserved Reserved Reserved Reserved CPU_Skew These 2 bits delay the CPU clock with respect to all other clocks. CPU_Skew = ps = 25ps = 5ps = 75ps Reserved Reserved Reserved Reserved B Byte 9: Group Skew Control Register 7 PCI_Skew 3 These 4 bits can change the 3V66 to PCI 6 PCI_Skew 2 skew from.4ns - 2.9ns. Each binary increment or decrement of PCI_SKEW (3:) 5 PCI_Skew will increase or decrease the delay of the PCI 4 PCI_Skew clocks by ps. 3 3V66_Skew These 2 bits delay the 3V66 with respect to CPUCLK 2 3V66_Skew = ps = 25ps = 5ps =75ps Reserved Reserved Reserved Reserved 47E 4/6/5 9

10 ICS9558 Byte 2: Group Skew Control Register 7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 Reserved Reserved 3 APIC_Skew 3 These 4 bits can change the 3V66 to APIC skew from.4ns - 2.9ns. Default at power 2 APIC_Skew 2 up is - 2.5ns. Each binary increment or APIC_Skew decrement of APIC_SKEW (3:) will increase or decrease the delay of the PCI APIC_Skew clocks by ps. Byte 2: Slew Rate Control Register 7 24/48_Slew 24/48 MHz clock slew rate control bits. 6 24/48_Slew = strong: = normal; = weak 5 3V66_Slew 3V66 clock slew rate control bits. 4 3V66_Slew = strong: = normal; = weak 3 APIC_Slew IOAPIC clock slew rate control bits. 2 APIC_Slew = strong: = normal; = weak REF_Slew REF clock slew rate control bits. REF_Slew = strong: = normal; = weak Byte 22: Slew Rate Control Register 7 SD_F Slew SDRAM_F clock slew rate control bits. 6 SD_F Slew = strong: = normal; = weak 5 SD(:8) Slew SDRAM (:8) clock slew rate control bits. 4 SD(:8) Slew = strong: = normal; = weak B it 3 SD(7:4) Slew SDRAM (7:4) clock slew rate control bits. B it 2 SD(7:4) Slew = strong: = normal; = weak B it SD(3:) Slew SDRAM (3:) clock slew rate control bits. B it SD(3:) Slew = strong: = normal; = weak Byte 23: Slew Rate Control Register 7 PCI (7:4) Slew PCI (7:4) clock slew rate control bits. 6 PCI (7:4) Slew = strong: = normal; = weak 5 PCI (3:) Slew PCI (3:) clock slew rate control bits. 4 PCI (3:) Slew = strong: = normal; = weak 3 CPU Slew CPUCLK clock slew rate control bits. 2 CPU Slew = strong: = normal; = weak CPU Slew CPUCLK clock slew rate control bits. CPU Slew = strong: = normal; = weak 47E 4/6/5

11 ICS9558 Absolute Maximum Ratings Core Supply Voltage V I/O Supply Voltage V Logic Inputs V to V DD +.5 V Ambient Operating Temperature C to +7 C Storage Temperature C to +5 C Case Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table CPU to Group CPU to SDRAM to SDRAM 3V66 3V66 CPU 66MHz SDRAM MHz Offset Tolerance CPU MHz SDRAM MHz Offset Tolerance CPU 33MHz SDRAM MHz Offset Tolerance CPU 33MHz SDRAM 33MHz Offset Tolerance 2.5ns 5ps 5.ns 5ps.ns 5ps 3.75ns 5ps 7.5ns 5ps 5.ns 5ps.ns 5ps.ns 5ps.ns 5ps.ns 5ps.ns 5ps 3.75ns 5ps 3V66 to PCI.5-3.5ns 5ps.5-3.5ns 5ps.5-3.5ns 5ps PCI to PCI USB & DOT.5-3.5ns 5ps.ns.ns.ns.ns.ns.ns.ns.ns Asynch N/ A Asynch N/ A Asynch N/ A Asynch N/ A Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD -5 5 Input Low Current I IL V IN = V; Inputs with no pull-up resistors -5 Input Low Current I IL2 V IN = V; Inputs with pull-up resistors -2 Operating I DD3.3OP C L = pf; 66M Supply Current Power Down I DD3.3PD C L = pf; With input address to Vdd or 6 Supply Current Input frequency F i V DD = 3.3 V; 4.38 MHz Pin Inductance L pin 7 nh Input Capacitance C IN Logic Inputs 5 pf C out Out put pin capacitance 6 pf C INX X & X2 pins pf Transition Time T trans To st crossing of target Freq. 3 ms Settling Time T s From st crossing to % target Freq. 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target Freq. 3 ms Delay t PZH,t PZH output enable delay (all outputs) ns t PLZ,t PZH output disable delay (all outputs) ns Guaranteed by design, not % tested in production. 47E 4/6/5

12 ICS9558 Electrical Characteristics - CPU T A = - 7 C; V DDL = 2.5 V +/-5%; C L = - 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP2B Vo=V DD *(.5) Ω Output Impedance R DSN2B Vo=V DD *(.5) Ω Output High Voltage V OH2B I OH = V Output Low Voltage V OL2B I OL =.4.4 V Output High Current I OH2B V OH@MIN = V V OH@MAX = 2.375V Output Low Current I OL2B V OL@MIN =.2 V V OL@MAX =.3V 2 3 Rise Time t r2b V OL =.4 V, V OH = 2. V ns Fall Time t f2b V OH = 2. V, V OL =.4 V ns Duty Cycle d t2b V T =.25 V % Skew t sk2b V T =.25 V ps V T =.25 V, CPU 66, SDRAM 2 25 Jitter, Cycle-to-cycle t jcyc-cyc2b CPU, SDRAM CPU 33, SDRAM 4 45 ps CPU 33, SDRAM Guaranteed by design, not % tested in production. Electrical Characteristics - IOAPIC T A = - 7 C; V DDL = 2.5 V +/-5%; C L = - 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP4B Vo=V DD *(.5) 9 3 Ω Output Impedance R DSN4B Vo=V DD *(.5) 9 3 Ω Output High Voltage V OH4B I OH = V Output Low Voltage V OL4B I OL = 9.4 V Output High Current Output Low Current I OH4B I OL4B V OH@MIN =.4 V -2 V OH@MAX = 2.5V -36 V OL@MIN =. V 36 V OL@MAX =.2V 3 Rise Time t r4b V OL =.4 V, V OH = 2. V ns Fall Time t f4b V OH = 2. V, V OL =.4 V.4.6 ns Duty Cycle d t4b V T =.25 V % Jitter, Cycle-to-cycle t jcyc-cyc4b V T =.25 V 25 5 ps Guaranteed by design, not % tested in production. 47E 4/6/5 2

13 ICS9558 Electrical Characteristics - SDRAM T A = - 7 C; V DD = 3.3 V +/-5%, C L = 2-3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP3 Vo=V DD *(.5) 24 Ω Output Impedance R DSN3 Vo=V DD *(.5) 24 Ω Output High Voltage V OH3 I OH = V Output Low Voltage V OL3 I OL =.4 V Output High Current Output Low Current I OH3 I OL3 V OH@MIN = 2 V -46 V OH@MAX = 3.35V -54 V OL@MIN = V 54 V OL@MAX =.4V 53 Rise Time t r3 V OL =.4 V, V OH = 2.4 V ns Fall Time t f3 V OH = 2.4 V, V OL =.4 V ns Duty Cycle d t3 V T =.5 V % Skew t sk3 V T =.5 V ps Jitter, cycle-to-cycle t jcyc-cyc3 V T =.5 V ps Guaranteed by design, not % tested in production. Electrical Characteristics - 3V66 T A = - 7 C; V DD = 3.3 V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output Impedance R DSN V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = V Output Low Voltage V OL I OL =.55 V Output High Current Output Low Current I OH I OL V MIN =. V -33 V MAX = 3.35 V -33 V MIN =.95 V 3 V MAX =.4 V 38 Rise Time t r V OL =.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL =.4 V ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V ps Jitter, Cycle-to-cycle t jcyc-cyc V T =.5 V 35 5 ps Guaranteed by design, not % tested in production. 47E 4/6/5 3

14 ICS9558 Electrical Characteristics - PCI T A = - 7 C; V DD = 3.3 V +/-5%, C L = - 3 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP Vo=V DD *(.5) 2 55 Ω Output Impedance R DSN Vo=V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = V Output Low Voltage V OL I OL =.55 V Output High Current Output Low Current Rise Time Fall Time I OH I OL t r t f V OH@MIN = V -33 V OH@MAX = 3.35V -33 V OL@MIN =.95 V 3 V OL@MAX =.4V 38 V OL =.4 V, V OH = 2.4 V, PCI PCI V OL = 2.4 V, V OH =.4 V, PCI PCI ns ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 48 5 ps Jitter, cycle-to-cycle t jcyc-cyc V T =.5 V 3 5 ps Guaranteed by design, not % tested in production. Electrical Characteristics - REF, 24_48MHz, 48MHz T A = - 7 C; V DD = 3.3 V +/-5%; C L = -2 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance R DSP5 V O = V DD *(.5) 2 6 Ω Output Impedance R DSN5 V O = V DD *(.5) 2 6 Ω Output High Voltage V OH5 I OH = V Output Low Voltage V OL5 I OL =.4 V Output High Current Output Low Current I OH5 I OL5 V MIN =. V -23 V MAX = 3.35 V -29 V MIN =.95 V 29 V MAX =.4 V 27 Rise Time t r5 V OL =.4 V, V OH = 2.4 V.4 4 ns Fall Time t f5 V OH = 2.4 V, V OL =.4 V.4 4 ns Duty Cycle d t5 V T =.5 V % Jitter, cycle-to-cycle t jcyc-cyc5 V T =.5 V, 24, 48 MHz 25 5 V T =.5 V, Ref clocks 2 3 ps Guaranteed by design, not % tested in production. 47E 4/6/5 4

15 ICS9558 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 47E 4/6/5 5

16 ICS9558 Power Down Waveform ns 25ns 5ns VCO Internal 2 CPU MHz 3.3V 66MHz PCI 33MHz APIC 6.7MHz PD# SDRAM MHz REF 4.38MHZ 48MHZ Note. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for MHz 47E 4/6/5 6

17 ICS9558 ns ns 2ns 3ns 4ns Cycle Repeats CPU 66MHz CPU MHz CPU 33MHz SDRAM MHz SDRAM 33MHz 3.5V 66MHz PCI 33MHz APIC 6.7MHz REF 4.38MHz USB 48MHz Group Offset Waveforms 47E 4/6/5 7

18 ICS9558 INDEX AREA N 2 D E E h x 45 c L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS α 8 8 e b A A -C- - SEATING PLANE. (.4) C VARIATIONS D mm. D (inch) N MIN MAX MIN MAX Reference Doc.: JEDEC Publication 95, M O-8 Ordering Information ICS9558yFLF-T Example: ICS XXXX y F LF- T 47E 4/6/5 Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 8

19 ICS9558 Revision History Rev. Issue Date Page # D 3/5/25 Update default values of Bytes E 4/6/25 Update Byte 3 spread programming information 8 47E 4/6/5 9