Programmable Timing Control Hub for Next Gen P4 processor

Transcription

1 ICS9549 Programmable Timing Control Hub for Next Gen P4 processor Recommended Application: CK4 compliant clock Output Features: 2 -.7V current-mode differential CPU pairs -.7V current-mode differential SRC pair 6 - PCI (33MHz) 3 - PCICLK_F, (33MHz) free-running - USB, 48MHz - 24/48 MHz - DOT, 96MHz,.7V current differential pair 2 - REF, 4.38MHz 5 - PCI-Express.7V current differential pairs Key Specifications: CPU/SRC outputs cycle-cycle jitter < 85ps PCI outputs cycle-cycle jitter < 25ps +/- 3ppm frequency accuracy on CPU & SRC clocks Functionality Bit4 Bit3 Bit2 Bit Bit CPU PCIE SRC PCI FSLC FSLB FSLA MHz MHz MHz MHz * Entries & are 25MHz on the B & C revision /24/4 Features/Benefits: Programmable output frequencies Programmable output skew. Programmable spread percentage for EMI control. Programmable watch dog safe frequency. Supports tight ppm accuracy clocks for Serial-ATA Supports spread spectrum modulation, to -.5% down spread, ±.25% center spread, and ±.3% center spread Uses external 4.38MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management. Pin Configuration GND PCICLK3 2 PCICLK4 3 PCICLK5 4 GND 5 VDDPCI 6 PCICLK_F 7 FS L A/PCICLK_F 8 FS L B/PCICLK_F2 9 VDD48 **SEL24_48#/24_48MHz USB_48MHz 2 GND 3 DOTT_ 96MHz 4 DOTC_96MHz 5 Vtt_PwrGd#/PD 6 PCIET 7 PCIEC 8 VDDPCIE 9 GND 2 PCIET 2 PCIEC22 PCIET2 23 PCIEC224 GND 25 SRCCLKT 26 SRCCLKC 27 VDDSRC 28 ICS Pin SSOP 56 VDDPCI 55 PCICLK2 54 PCICLK 53 PCICLK 52 Reset# 5 REF/FS L C 5 REF 49 GND VDDREF 45 SCLK 44 SDATA 43 CPUCLKT 42 CPUCLKC 4 VDDCPU 4 CPUCLKT 39 CPUCLKC 38 GND 37 IREF 36 GNDA 35VDDA 34 VDDPCIE 33PCIET4 32 PCIEC4 3 PCIET3 3 PCIEC3 29 GND * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

2 ICS9549 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION GND PWR Ground pin. 2 PCICLK3 OUT PCI clock output. 3 PCICLK4 OUT PCI clock output. 4 PCICLK5 OUT PCI clock output. 5 GND PWR Ground pin. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK_F OUT Free running PCI clock not affected by PCI_STOP#. 8 FSLA/PCICLK_F I/O 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock output. 9 FSLB/PCICLK_F2 I/O 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock output. VDD48 PWR Power pin for the 48MHz output.3.3v **SEL24_48#/24_48MHz I/O Latched select input for 24/48MHz output / 24/48MHz clock output. =24MHz, = 48MHz. 2 USB_48MHz OUT 48.MHz USB clock 3 GND PWR Ground pin. 4 DOTT_ 96MHz OUT True clock of differential pair for 96.MHz DOT clock. 5 DOTC_96MHz OUT Complement clock of differential pair for 96.MHz DOT clock. 6 Vtt_PwrGd#/PD IN Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 7 PCIET OUT True clock of differential PCI_Express pair. 8 PCIEC OUT Complement clock of differential PCI_Express pair. 9 VDDPCIE PWR Power supply for PCI Express clocks, nominal 3.3V 2 GND PWR Ground pin. 2 PCIET OUT True clock of differential PCI_Express pair. 22 PCIEC OUT Complement clock of differential PCI_Express pair. 23 PCIET2 OUT True clock of differential PCI_Express pair. 24 PCIEC2 OUT Complement clock of differential PCI_Express pair. 25 GND PWR Ground pin. 26 SRCCLKT OUT True clock of differential pair for S-ATA support. +/- 3ppm accuracy required. 27 SRCCLKC OUT Complement clock of differential pair for S-ATA support. +/- 3ppm accuracy required. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 875 5/24/4 2

3 ICS9549 Pin Description PIN # PIN NAME TYPE DESCRIPTION 29 GND PWR Ground pin. 3 PCIEC3 OUT Complement clock of differential PCI_Express pair. 3 PCIET3 OUT True clock of differential PCI_Express pair. 32 PCIEC4 OUT Complement clock of differential PCI_Express pair. 33 PCIET4 OUT True clock of differential PCI_Express pair. 34 VDDPCIE PWR Power supply for PCI Express clocks, nominal 3.3V 35 VDDA PWR 3.3V power for the PLL core. 36 GNDA PWR Ground pin for the PLL core. 37 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 38 GND PWR Ground pin. 39 CPUCLKC OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 4 CPUCLKT OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 4 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 42 CPUCLKC OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 43 CPUCLKT OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 44 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 45 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 46 VDDREF PWR Ref, TAL power supply, nominal 3.3V 47 2 OUT Crystal output, Nominally 4.38MHz 48 IN Crystal input, Nominally 4.38MHz. 49 GND PWR Ground pin. 5 REF OUT 4.38 MHz reference clock. 5 REF/FSLC I/O 4.38 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 52 Reset# OUT Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 53 PCICLK OUT PCI clock output. 54 PCICLK OUT PCI clock output. 55 PCICLK2 OUT PCI clock output. 56 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 875 5/24/4 3

4 ICS9549 General Description ICS9549 follows Intel CK4 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9549 is driven with a 4.38MHz crystal. Block Diagram 24/48MHz 48MHz, USB PLL2 Frequency Dividers DOTT_96MHz DOTC_96MHz 2 TAL REF (:) CPUCLKT (:) CPUCLKC (:) SCLK SDATA Vtt_PWRGD#/PD FSLA FSLB FSLC Sel24/48 Control Logic Programmable Spread PLL Programmable Frequency Dividers STOP Logic SRCCLKT SRCCLKC PCICLK (5:) PCICLKF (2:) PCI-Express (4:) Reset# I REF Power Busing VDD GND Description 6,56 9, ,5 3 2, PCI pads and Prepad USB_48M Hz, DOT_96M Hz, Fix PLL Differnetial PCIE pair Differnetial SRC pair Analog Core, CPU PLL Differnetial CPU pair tal, Ref, CPU PLL Digital 875 5/24/4 4

5 ICS9549 General I 2 C serial interface information for the ICS9549 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD Data Byte Count = Beginning Byte N Byte N P Not acknowledge stop bit Byte N /24/4 5

6 ICS9549 Table: Frequency Selection Table Bit2 Bit Bit CPU PCIE SRC PCI Spread Bit4 Bit3 FSLC FSLB FSLA MHz MHz MHz MHz % to -.5% Down to -.5% Down to -.5% Down to -.5% Down to -.5% Down to -.5% Down to -.5% Down to -.5% Down /-.25% Center /-.25% Center /-.25% Center /-.25% Center /-.25% Center /-.25% Center /-.25% Center /-.25% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center /-.3% Center 875 5/24/4 6

7 ICS9549 I 2 C Table: Frequency Select Register Byte Pin # Name Control Function Type PWD Bit 7 - FS Source Frequency H/W IIC Select RW Latch Inputs IIC SS_EN PLL Spread RW OFF ON RW - - Bit4 Freq Select Bit 4 RW Bit3 Freq Select Bit 3 RW FSLC Freq Select Bit 2 RW See Table : PLL Frequency Selection Table Latch Bit - FSLB Freq Select Bit RW Latch Bit - FSLA Freq Select Bit RW Latch I 2 C Table: Output Control Register Byte Pin # Name Control Function Type PWD Bit 7 7 PCICLK_F Output Control RW Disable Bit 6 4,5 DOTT/C_96MHz Output Control RW Disable Bit 5 2 USB_48MHz Output Control RW Disable Bit 4 5 REF Output Control RW Disable Bit 3 5 REF Output Control RW Disable Bit 2 4,39 CPUCLKT/C Output Control RW Disable Bit 43,42 CPUCLKT/C Output Control RW Disable Bit - CPUCLK's PD Mode Output State Control RW Driven Hi-Z I 2 C Table: Output Control Register Byte 2 Pin # Name Control Function Type PWD Bit 7 4 PCICLK5 Output Control RW Disable Bit 6 3 PCICLK4 Output Control RW Disable Bit 5 2 PCICLK3 Output Control RW Disable Bit 4 55 PCICLK2 Output Control RW Disable Bit 3 54 PCICLK Output Control RW Disable Bit 2 53 PCICLK Output Control RW Disable Bit 9 PCICLK_F2 Output Control RW Disable Bit 8 PCICLK_F Output Control RW Disable I 2 C Table: Output Control Register Byte 3 Pin # Name Control Function Type PWD Bit 7 - PCIECLK's PD Mode Output State Control RW Driven Hi-Z RW - - Bit 5 33,32 PCIECLKT/C4 Output Control RW Disable Bit 4 3,3 PCIECLKT/C3 Output Control RW Disable Bit 3 27,26 SRCCLKT/C Output Control RW Disable Bit 2 24,23 PCIECLKT/C2 Output Control RW Disable Bit 22,2 PCIECLKT/C Output Control RW Disable Bit 8,7 PCIECLKT/C Output Control RW Disable I 2 C Table: Output Control Register Byte 4 Pin # Name Control Function Type PWD Bit 7 - PCI/SRC Stop EN Stop all PCI / PCIE / SRC clocks Disable PCICLK_F2 Stop Control RW Free Running Stoppable PCICLK_F Stop Control RW Free Running Stoppable PCICLK_F Stop Control RW Free Running Stoppable PCIECLKT/C (5:3) Stop Control RW Free Running Stoppable SRCCLKT/C Stop Control RW Free Running Stoppable Bit - PCIECLKT/C (2:) Stop Control RW Free Running Stoppable Bit - RW /24/4 7

8 ICS9549 I 2 C Table: Programmable Skew Control Register Byte 5 Pin # Name Control Function Type PWD PCISkw3 RW : :5 :3 :45 PCISkw2 CPU-PCI 7 Steps RW :N/A :N/A :N/A :6 PCISkw Skew Control (ps) RW :N/A :N/A :N/A :75 PCISkw RW :N/A :N/A :N/A :9 ASYNC RW = PLL = 37.7 PCI Async Freq ASYNC RW = 33. = 44. Bit - REF REF select RW TAL Fixed PLL Bit - RW - - I 2 C Table: Output Drive Control Register Byte 6 Pin # Name Control Function Type PWD RW - - RW - - RW - - RW - - RW - - RW - - Bit - RW - - Bit - RW - - I 2 C Table: Vendor ID Register Byte 7 Pin # Name Control Function Type PWD RW - - RW - - RW - - RW - - VID3 R - - VID2 R - - VENDOR ID Bit - VID R = ICS - Bit - VID R - - I 2 C Table: Byte Count Register Byte 8 Pin # Name Control Function Type PWD BC7 RW BC6 RW BC5 RW BC4 Byte Count RW Writing to this register will configure how many bytes will be read BC3 Programming b(7:) RW back, default is F = 5 bytes. BC2 RW Bit - BC RW Bit - BC RW I 2 C Table: WD Time Control Register Byte 9 Pin # Name Control Function Type PWD Bit 7 - WD_EN Watchdog Alarm RW Disable Bit 6 - WD_SEL Watchdog Hard/Soft Alarm Select RW Hard only Hard and Soft WD Hard Status WD Hard Alarm Status R Normal Alarm WD Soft Status WD Soft Alarm Status R Normal Alarm Bit 3 - WDTCtrl Watch Dog Time base Control RW 29ms Base 6ms Base WD2 WD Timer Bit 2 RW These bits represent *29ms (or.6s) the watchdog timer Bit - WD WD Timer Bit RW waits before it goes to alarm mode. Default is 7 29ms = 2s. Bit - WD WD Timer Bit RW 875 5/24/4 8

9 ICS9549 I 2 C Table: M/N Programming & WD Safe Frequency Control Register Byte Pin # Name Control Function Type PWD Bit 7 - M/N_EN PLL M/N Programming RW Disable RW - - WD Safe Freq Source WD Safe Freq Source RW Bb(4:) Latch Inputs WD SF4 RW WD SF3 RW Watch Dog Safe Freq Writing to these bit will configure the safe frequency as Byte bit WD SF2 RW Programming bits (4:). Bit - WD SF RW Bit - WD SF RW I 2 C Table: PLL Frequency Control Register Byte Pin # Name Control Function Type PWD N Div8 N Divider Prog bit 8 RW N Div9 N Divider Prog bit 9 RW M Div5 RW The decimal representation of M and N Divier in Byte and 2 M Div4 RW will configure the PLL VCO frequency. Default at power up = M Div3 M Divider Programming RW latch-in or Byte Rom table. VCO Frequency = 4.38 x M Div2 bit (5:) RW [NDiv(9:)+8] / [MDiv(5:)+2] Bit - M Div RW Bit - M Div RW I 2 C Table: PLL Frequency Control Register Byte 2 Pin # Name Control Function Type PWD N Div7 RW N Div6 RW N Div5 RW The decimal representation of M and N Divier in Byte and 2 N Divider Programming N Div4 RW will configure the PLL VCO frequency. Default at power up = Byte2 bit(7:) and N Div3 Byte bit(7:6) RW latch-in or Byte Rom table. VCO Frequency = 4.38 x N Div2 RW [NDiv(9:)+8] / [MDiv(5:)+2] Bit - N Div RW Bit - N Div RW I 2 C Table: PLL Spread Spectrum Control Register Byte 3 Pin # Name Control Function Type PWD SSP7 RW SSP6 RW SSP5 RW SSP4 Spread Spectrum RW These Spread Spectrum bits in Byte 3 and 4 will program the SSP3 Programming bit(7:) RW spread pecentage of PLL SSP2 RW Bit - SSP RW Bit - SSP RW I 2 C Table: PLL Spread Spectrum Control Register Byte 4 Pin # Name Control Function Type PWD R - - SSP4 RW SSP3 RW SSP2 RW Spread Spectrum These Spread Spectrum bits in Byte 3 and 4 will program the SSP RW Programming bit(4:8) spread pecentage of PLL SSP RW Bit - SSP9 RW Bit - SSP8 RW 875 5/24/4 9

10 ICS9549 I 2 C Table: Register Byte 5 Pin # Name Control Function Type PWD Bit - Bit - I 2 C Table: Register Byte 6 Pin # Name Control Function Type PWD Bit - Bit - I 2 C Table: Register Byte 7 Pin # Name Control Function Type PWD Bit - Bit - I 2 C Table: Register Byte 8 Pin # Name Control Function Type PWD RW Bit - Bit - I 2 C Table: Programmable Output Divider Register Byte 9 Pin # Name Control Function Type PWD CPUDiv3 RW :/2 :/4 :/8 :/6 CPUDiv2 CPU Divider Ratio RW :/3 :/6 :/2 :/24 CPUDiv Programming Bits RW :/5 :/ :/2 :/4 CPUDiv RW :/7 :/4 :/28 :/56 PCIEDiv3 RW :/2 :/4 :/8 :/6 PCIEDiv2 PCIE Divider Ratio RW :/3 :/6 :/2 :/24 Bit - PCIEDiv Programming Bits RW :/5 :/ :/2 :/4 Bit - PCIEDiv RW :/7 :/4 :/28 :/ /24/4

11 ICS9549 I 2 C Table: Programmable Output Divider Register Byte 2 Pin # Name Control Function Type PWD PCIDiv3 RW :/2 :/4 :/8 :/6 PCIDiv2 PCI Divider Ratio RW :/3 :/6 :/2 :/24 PCIDiv Programming Bits RW :/5 :/ :/2 :/4 PCIDiv RW :/5 :/3 :/6 :/2 RW - - RW - - Bit - RW - - Bit - RW /24/4

12 ICS9549 Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes 3.3V Core Supply Voltage VDD_A - V DD +.5V V 3.3V Logic Input Supply Voltage VDD_In - GND -.5 V DD +.5V V Storage Temperature Ts C Ambient Operating Temp Tambient - 7 C Case Temperature Tcase - 5 C Input ESD protection HBM ESD prot - 2 V Guaranteed by design and characterization, not % tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS Notes Input High Voltage V IH 3.3 V +/-5% 2 V DD +.3 V Input Low Voltage V IL 3.3 V +/-5% V SS V Input High Current I IH V IN = V DD -5 5 ua Input Low Current V I IN = V; Inputs with no pull-up IL resistors -5 ua V I IN = V; Inputs with pull-up IL2 resistors -2 ua Low Threshold Input- High Voltage V IH_FSL 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input- Low Voltage V IL_FSL 3.3 V +/-5% V SS V Operating Supply Current I DD3.3OP Full Active, C L = Full load; 35 ma Operating Current I DD3.3OP all outputs driven 4 ma Powerdown Current I DD3.3PD all diff pairs driven 7 ma all differential pairs tri-stated 2 ma Input Frequency F i V DD = 3.3 V MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C IN & 2 pins 5 pf From V Clk Stabilization T DD Power-Up or deassertion of PD# to st clock STAB.8 ms Modulation Frequency Triangular Modulation 3 33 khz Tdrive_PD# CPU output enable after PD# de-assertion 3 us Tfall_Pd# PD# fall time of 5 ns Trise_Pd# PD# rise time of 5 ns SMBus Voltage V DD V Low-level Output I PULLUP.4 V Current sinking at =.4 V I PULLUP 4 ma SCLK/SDATA (Max VIL -.5) to T Clock/Data Rise Time RI2C (Min VIH +.5) ns SCLK/SDATA (Min VIH +.5) to T Clock/Data Fall Time FI2C (Max VIL -.5) 3 ns *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 4.388MHz to meet ppm frequency accuracy on PLL outputs /24/4 2

13 ICS9549 Electrical Characteristics - CPUCLKT/C --.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Current Source Output Impedance Zo V O = V x 3 Ω Voltage High VHigh Statistical measurement on mv,3 Voltage Low VLow single ended signal -5 5 mv,3 Max Voltage Vovs Measurement on single ended 5 mv Min Voltage Vuds signal using absolute value. -3 mv Crossing Voltage (abs) Vx(abs) mv Crossing Voltage (var) d-vx Variation of crossing over all edges 4 mv Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 4MHz nominal ns 2 4MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2 Average period Tperiod 2MHz nominal ns 2 2MHz spread ns MHz nominal ns MHz spread ns MHz nominal ns MHz spread ns 2.MHz nominal ns 2.MHz spread ns 2 4MHz nominal/spread ns, MHz nominal/spread 2.94 ns, MHz nominal/spread ns,2 Absolute min period T absmin 2MHz nominal/spread ns, MHz nominal/spread ns, MHz nominal/spread ns,2.mhz nominal/spread ns,2 Rise Time t r =.75V, =.525V 75 7 ps Fall Time t f =.525V =.75V 75 7 ps Rise Time Variation d-t r =.75V, =.525V 25 ps Fall Time Variation d-t f =.525V =.75V 25 ps Measurement from differential Duty Cycle d t3 wavefrom % Skew t sk3 CPU(:), = 5% ps CPU(:) to CPU2_ITP, Skew t sk4 = 5% 5 ps Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom (CPU2_ITP) 25 ps Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom, (CPU(:)) 85 ps *T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 3 I REF = V DD /(3xR R ). For R R = 475Ω (%), I REF = 2.32mA. I OH = 6 x I REF and Z O =5Ω /24/4 3

14 ICS9549 Electrical Characteristics - SRC/SATA/PCIE.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS Notes Current Source Output Impedance Zo V O = V x 3 Ω Voltage High VHigh Statistical measurement on mv,3 Voltage Low VLow single ended signal -5 5 mv,3 Max Voltage Vovs Measurement on single ended 5 mv Min Voltage Vuds signal using absolute value. -3 mv Crossing Voltage (abs) Vx(abs) mv Crossing Voltage (var) d-vx Variation of crossing over all edges 4 mv Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 Average period Tperiod.MHz nominal ns 2.MHz spread ns 2 Absolute min period Tabsmin.MHz nominal/spread ns,2 Rise Time t r =.75V, =.525V 75 7 ps Fall Time t f =.525V =.75V 75 7 ps Rise Time Variation d-t r =.75V, =.525V 25 ps Fall Time Variation d-t f =.525V =.75V 25 ps Measurement from differential Duty Cycle d t3 wavefrom % Skew t sk3 = 5% 25 ps Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 25 ps *T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 3 I REF = V DD /(3xR R ). For R R = 475Ω (%), I REF = 2.32mA. I OH = 6 x I REF and Z O =5Ω. Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.55 V Output High Current Output Low Current I OH I =. V -33 = 3.35 V -33 MIN =.95 V 3 MA =.4 V 38 ma Edge Rate t slewr/f Rising/Falling edge rate 4 V/ns Rise Time t r =.4 V, = 2.4 V.5 2 ns Fall Time t f = 2.4 V, =.4 V.5 2 ns Duty Cycle d t =.5 V % Group Skew t skew =.5 V 5 ps Jitter, Cycle to cycle t jcyc-cyc =.5 V 25 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2 pf with Rs = 7Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production /24/4 4

15 ICS9549 Electrical Characteristics - 48MHz/USB48MHz/24_48MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Long Accuracy ppm see Tperiod min-max values - ppm Clock period T period 48.MHz output nominal ns Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.55 V Output High Current Output Low Current I OH I =. V -33 = 3.35 V -33 MIN =.95 V 3 MA =.4 V 38 ma Edge Rate t slewr/f Rising/Falling edge rate 4 V/ns Edge Rate t slewr/f_usb USB48 Rising/Falling edge rate 2 V/ns Rise Time t r =.4 V, = 2.4 V.5 2 ns Fall Time t f = 2.4 V, =.4 V.5 2 ns Rise Time t r_usb =.4 V, = 2.4 V 2 ns Fall Time t f_usb = 2.4 V, =.4 V 2 ns Duty Cycle d t =.5 V % Jitter, Cycle to cycle t jcyc-cyc =.5 V 5 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2 pf with Rs = 7Ω (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not % tested in production. Electrical Characteristics - DOT_96MHz.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS Notes Current Source Output Impedance Zo V O = V x 3 Ω Voltage High VHigh Statistical measurement on mv,3 Voltage Low VLow single ended signal -5 5 mv,3 Max Voltage Vovs Measurement on single ended 5 mv Min Voltage Vuds signal using absolute value. -3 mv Crossing Voltage (abs) Vx(abs) mv Crossing Voltage (var) d-vcross Variation of crossing over all edges 4 mv Long Accuracy ppm see Tperiod min-max values - ppm,2 Average period Tperiod 96.MHz nominal ns 2 Absolute min period Tabsmin 96.MHz nominal.635 ns,2 Rise Time t r =.75V, =.525V 75 7 ps Fall Time t f =.525V =.75V 75 7 ps Rise Time Variation d-t r =.75V, =.525V 25 ps Fall Time Variation d-t f =.525V =.75V 25 ps Measurement from differential Duty Cycle d t3 wavefrom % Measurement from differential Jitter, Cycle to cycle t jcyc-cyc wavefrom 25 ps *T A = - 7 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 3 I REF = V DD /(3xR R ). For R R = 475Ω (%), I REF = 2.32mA. I OH = 6 x I REF and Z O =5Ω /24/4 5

16 ICS9549 Electrical Characteristics - REF-4.38MHz PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 Clock period T period 4.38MHz output nominal ns 2 Output High Voltage I OH = - ma 2.4 V Output Low Voltage I OL = ma.4 =. V, Output High Current I = 3.35 V =.95 V, Output Low Current I =.4 V ma Edge Rate t slewr/f Rising/Falling edge rate 4 V/ns Rise Time t r =.4 V, = 2.4 V 2 ns Fall Time t f = 2.4 V, =.4 V 2 ns Duty Cycle d t =.5 V % Jitter t jcyc-cyc =.5 V ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2 pf with Rs = 7Ω (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 875 5/24/4 6

17 ICS9549 INDE AREA N 2 D E A E h x 45 c α L 56-Lead, 3 mil Body, 25 mil, SSOP In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS a 8 8 e b A -C- - SEATING PLANE VARIATIONS D mm. D (inch) N MIN MA MIN MA (.4) C Reference Doc.: JEDEC Publication 95, MO-8-34 Ordering Information Example: 875 5/24/4 ICS9549yFLF-T ICS y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 7