1 Transistor Characterization Figure 1.1: ADS Schematic of Transistor Characterization Circuit 1.1 Question 1 The bias voltage, width, and length of a single NMOS transistor (pictured in Figure 1.1) were swept over a range of values independently, and the effects on the transistor s transition frequency, drain current, intrinsic gain, noise figure, and insertion gain were subsequently observed. While one parameter was being swept the other parameters were held at default values: Vgs= 0.8V,L = 0.18µm,W = 50µm *It should be noted that the drain current analyses, intrinsic gain analyses, and transition frequency analyses were all conducted with a short circuited drain and source (in contrast to Figure 1.1). 2
1.1.1 Drain Current vs Parameter Sweeps Figure 1.2: Drain Current vs L Figure 1.3: Drain Current vs W 3
Figure 1.4: Drain Current vs Vgs 4
1.1.2 Intrinsic Gain vs Parameter Sweeps Figure 1.5: Intrinsic Gain vs L Figure 1.6: Intrinsic Gain Current vs W 5
Figure 1.7: Intrinsic Gain vs Vgs 6
1.1.3 Transition Frequency vs Parameter Sweeps Figure 1.8: Transition Frequency vs L 7
Figure 1.9: Transition Frequency Current vs W 8
Figure 1.10: Transition Frequency vs Vgs 9
1.1.4 Insertion Gain vs Parameter Sweeps Figure 1.11: Insertion Gain vs L Figure 1.12: Insertion Gain vs W 10
Figure 1.13: Insertion Gain vs Vgs 11
1.1.5 Noise Figure vs Parameter Sweeps Figure 1.14: Noise Figure vs L Figure 1.15: Noise Figure vs W 12
Figure 1.16: Noise Figure vs Vgs 13
1.2 Question 2 Explain the shapes of the intrinsic gain and transition frequency curves obtained in Question 1. Why do both the DC gain and the unity gain frequency have such a weak dependence on W? The intrinsic gain of an NMOS transistor can be represented in mathematical form (for the drain-source shortcircuit case) by g m = g m r 0 = 2I D (V 0 A )(L) (1.1) g ds v OV I D where the product (V 0 A )(L) is the Early Voltage of the MOSFET decomposed into a process dependent part given by V 0 A, and a channel length dependent part. It should be noted that the channel length dependent part is present due to the effects of channel length on the channel modulation parameter = 1 V A. Upon cancelation of common terms in equation (1.1), the intrinsic gain becomes g m = (V 0 A)(2L) (1.2) g ds v OV Resultantly from equation (1.2), one would expect the intrinsic gain to increase in concert with the channel length as observed in Figure 1.5. The nonlinearity of the the DC Gain vs. Length plot is due to the nonlinear (inverse) relationship between the channel modulation parameter and the channel length. The DC gain from equation (1.2) shows an inverse relationship to v GS = v OV + v threshold. This relationship is exactly depicted in Figure 1.7. This makes sense since g m is proprtional to v OV whereas g ds is proportional to drain current which exhibits a squared relationship to the overdrive voltage. Also, from equation (1.2), it is evident that there is no clear first-order dependency of the intrinsic gain on channel width since both g m and g ds have a proportionality to width that near-perfectly cancel out - thus explaining the weak dependence of DC gain on W as shown in Figure 1.3. As for the transition frequency, taking the same approach in the reasoning as was done with the intrinsic gain - we first provide an expression in mathematical form that rationalizes the observations based on the mathematical expressions, and concurrently explain the physical nature of the mathematical expressions. f T = g m 2º(C gs +C gd ) = k0 W n L v OV (1 + v DS ) 2º 2 3 WLC OX (1.3) * / 1 L *In saturation mode of operation for the enhacement type FET - the primary region of interest - C gs can be approximated as 2 3 WLC OX, and C gd can be approximated as 0. From equation (1.3), we can make some immediate comments with respect to the curves obtained in Question 1. First off, there is a clear inverse relationship between f T and channel length, this is supported by Figure 1.8. Secondly there is also a clear proportionality between f T and v OV, explaining the overall shape of the curve in Figure 1.10. Specifically, we see f T remain 0 until the transistor turns on at v OV > 0.35V, then as the current density in the channel starts to increase (the transistor enters triode mode of operation), f T increase almost linearly with current (which also increase linearly with v GS ), and then f T flattens off as the current saturates and the channel clips. The low-sloped pseudo-linear increase in f T even after current saturation is attributable to channel length modulation. And finally, as can be seen from equation 1.3, the width dependencies in the numerator and denominator cancel out, thereby explaining the weak dependence of f T on transistor width seen in Figure 1.12. 1.3 Question 3 Explain the shape of the curves obtained in question 1, parts (d) and (e). S(2, 1) is the forward-feedthrough voltage gain of the transistor. First with regards to Figure 1.13 - as is expected, the gain remains extremely low, until the transistor turns on, and then starts increasing linearly in the triode region until the current saturates and S(2,1) stabalizes. S(2,1) is going to increase proportionally to the ratio of g m to the 14
gate capacitances. Since g m is inversely proportional to L, and the gate capacitances are proportional to L, we see an inverse relationship between S(2, 1) and the channel length in Figure 1.11. As for width. S(2, 1) increases with width due to the increase in drain current which increases faster than the capacitance, causing the concave rise seen in Figure 1.12. This concave rise continues until the current saturates, and the capacitive effects start to dominate the increase in current; the result is that S(2, 1) decline after a certain threshold in saturation. Said threshold can clearly be extrapolated as the peak of the curve in FIgure 1.12. (depending on the MOSFET model used given the frequency of operation). We expect the noise figure to be minimized when our gain is low, and when we are operating far away from our f T. Since our operating point is fixed at 5.16GHz, operating far from f T corresponds to maximizing f T. Since f T is inversely proportional to channel length, it makes sense that noise figure will exhibit a proportional behaviour to channel length (as seen in Figure 1.14). As for width. The weak relationship between f T and width has already been examined, so the main width dependency in the noise figure is attributable to g m. To minimize g m, the width is minimized, and concequently the noise figure is maximized, hence the inverse relationship between noise figure and width depicted in Figure 1.15. The noise figure s relationship to v GS is very nuanced with many contributing factors. When the transistor is off, the noise figure is of practically 0 since the MOSFET s input-referred noise is negligible. Upon turning on the transistor the noise figure quickly establishes itself as the current-dependent noise contributors being contributing (i.e shot noise, flicker noise). When v GS reaches º 0.4V, f T grows out of 0, and starts sharply rising (Figure 1.10), thereby explaining the sudden rapid decrease in noise figure in FIgure 1.16. This decrease in noise figure continues as f T continues to increase rapidly, and then starts reversing when the increase in v GS begins contributing more constructively to g m than f T (f T begins flattening out long before g m ). The minimum noise figure is proportional to some nonlinear function of p g m f f T 1.4 Question 4 What is the maximum usable frequency of this transistor? What values for VGS, W, and L would you use to obtain this frequency?. The maximum usable frequency of the transistor is º 35GHz, which can be achieved at v GS = 1.5V,L = 0.18µm,W = 200µm 1.5 Question 5 Based on the above plots, what values for VGS, W, and L would you pick to obtain the minimum noise figure at your design center frequency? What would the current consumption be? The minimum noise figure achievable by the transistor is 0.931dB, and can be achieved at The current consumption would be 8.454mA. v GS = 0.6V,L = 0.18µm,W = 200µm 15