Name: EXAM #3 Closed book, closed notes. Calculators may be used for numeric computations only. All work is to be your own - show your work for maximum partial credit. Data: Use the following data in all the problems in the Exam: V DD 1.8V µ n C ox 200 µa/v 2 µ p C ox 100 µa/v 2 V THN 0.4V V THP 0.5V NMOS Equations Cutoff region I D = 0, VGS < VTHN Triode (linear) region 2 W V DS I = µ C ( V V ) V, V L 2 > V, V < V V Saturation region I 1 2 = µ C W ( V V ) ( 1 + λv 2 L ), V > V, V V V Small-signal Parameters D n ox GS THN DS GS THN DS GS THN D n ox GS THN DS GS THN DS GS THN W W 2I D gm = µ ncox ( VGS VTHN ) = 2µ ncox I D = L L VGS V 1 r0 = λi D PMOS Equations Assuming all positive convention, make the substitutions in the above equations: µ n µ p, V GS V SG, V DS V SD, and V THN V THP Inverter Equations 2V TH V N TPHL = Ron C ln 3 4 n L + V V N V TH N DD TH DD 2 V TH V P TPLH = Ron C ln 3 4 p L + VDD V V TH P 1 Ron = n, p W µ n, pcox ( VDD VTH N, P ) L TH P DD THN 1
1. (30 points) Consider the CMOS inverter shown below (Here, V DD =1.8V and C L =100fF). 3.6µ 0.18µ VDD I D V in V out 1.8µ 0.18µ 100fF (a) (5 points) Sketch the voltage transfer curve (VTC) for the inverter and properly label the plot. (b) (5 points) Sketch the current flowing in the inverter as V in is swept from 0 to V DD (also label the plot). 2
(c) (5 points) If the input is stepped down from V DD to 0, calculate the delay (T PLH ). Sketch the input and output waveforms on the same plot. (d) (5 points) If the input jumps from 0 to V DD, calculate the delay (T PHL ). Sketch the input and output waveforms on the same plot. 3
(e) (5 points) If an ideal clock of 100 MHz frequency is applied at the input, estimate the dynamic power dissipated in the inverter. (f) (5 points) Suppose, the supply voltage is raised by 10%. By how much do T PHL and T PLH decrease? 4
2. (10 points) Draw the CMOS implementation of a 3 input NOR gate. ECE 310 Microelectronic Circuits 5
3. (15 points) CMOS Amplifier Design: Assume that the transconductances of all the transistors in this problem is equal to g m and the output resistance is r o. Also, V b1 and V b2 are DC bias voltages. Clearly show your work. (a) (5 points) Find the small-signal gain of the amplifier (in terms of g m and r o ) shown below. (b) (5 points) Assume that M 1 and M 2 are in saturation. Using small-signal analysis, find the output resistance (R o ) in the circuit shown below. R o V b2 M 3 V b1 M 2 6
(c) (5 points) Using the result from part (b), find the small-signal gain of the amplifier shown below. Compare the answer with the result in part (a). 7
4. (15 points) On an IC, current mirrors are used to generate currents and voltages for DC biasing. Consider the current mirror circuits shown below and assume all the transistors are in saturation. Also, ignore channel length modulation (λ n = λ p =0) (a) (5 points) Calculate the DC voltages V biasn and V biasp 8
(b) (10 points) Find the currents I 1, I 2, I 3, I 4 and I 5 in the above circuit. Hint: Take ratios of the current equations. 9
5. (20 points) Design a generated CS amplifier design following the given steps. The amplifier must provide a voltage gain of 4 with a power budget of 2mW while the drop across R s is equal to 200 mv. The overdrive (V ov =V GS -V THN ) of the transistor M 1 should be 300mV and the total power consumed in the biasing resistances (R 1 + R 2 ) should be only 5% of the total power. Assume that C 1 is large. VDD=1.8V R 1 R D C 1 V out M 1 V in R 2 R s (a) (3 points) Given the power budget for the transistor M 1, estimate the value of the bias current (I D ). (b) (3 points) Using part (a), find the value of R s. (c) (3 points) For the current, I D, estimate the W/L ratio of the transistor. 10
(d) (4 points) Estimate the value of R D for the required small-signal gain, A v =4. ECE 310 Microelectronic Circuits (e) (3 points) Find the voltage at the gate of M 1, (V G ) (f) (4 points) Using the 5% power budget constraint, and the gate voltage (V G ) estimate the value of resistors R 1 and R 2. 11
6. (10 points) Consider the Source Follower shown below. Here, V b1 is a DC voltage and assume all transistors are in saturation. Your answers should be in terms of the small-signal parameters (g m1, r o1, r o2 ). (a) (5 points) Find the small-signal voltage gain of the SF. (b) (5 points) Find the output impedance of the circuit. 12