FLT-BSE TYPE INSULTED PCKGE FETURE a) dopting new 5th generation (CSTBT) chip, which performance is improved by µm fine rule process. r example, typical ce(sat)= @Tj=25 b) I adopt the over-temperature conservation by Tj detection of CSTBT chip, and error output is possible from all each conservation upper and lower arm of IPM. c) New small package Reduce the package size by 32%, thickness by 22% from S-DSH series. d) Current rating of brake part increased. 50% for the current rating of inverter part. 3φ 50, 600 Current-sense type inverter 75, 600 Current-sense regenerative brake Monolithic gate drive & protection logic Detection, protection & status indication circuits for, shortcircuit, over-temperature & under-voltage (P- available from upper arm devices) coustic noise-less 5kW/8.5kW class inverter application PPLICTION General purpose inverter, servo drives and other motor controls PCKGE LINES Dimensions in mm 7 06 ±0.25 9.75 3.25 6 3-2 6 3-2 66.5 3-2 6 5.25 6-2 2-φ5.5 MOUNTING HOLES 7 6 3 35 25.75 25 55 9.5 2.5 9.5 22 23 7.75 98.25 23 9-0.5 23 9.5 27.5 4 4 4 4 N P 5 9 3 9 2-φ2.5 B U W 4 4 4 4 4 4 4 4 4-φ2.5 Terminal code. UPC 2. UFO 3. UP 4. UP 5. PC 6. FO 7. P 8. P 9. WPC 0. WFO. WP 2. WP 3. NC 4. N 5. Br 6. UN 7. N 8. WN 9. pr. 04
FLT-BSE TYPE INSULTED PCKGE INTERNL FUNCTIONS BLOCK DIGRM Br NC WN N N UN WP WP WPC WFO P P PC FO UP UP UPC UFO cc cc cc cc cc cc cc Out Out Out Out Out Out Out B N W U P MXIMUM RTINGS (Tj = 25, unless otherwise noted) INERTER PRT Ratings CES ±IC ±ICP PC Tj oltage Collector Current Collector Current (Peak) Collector Dissipation Junction Temperature D = 5, CIN = 5 600 50 300 480 ~ +50 W BRKE PRT Ratings CES IC ICP PC R(DC) Tj oltage Collector Current Collector Current (Peak) Collector Dissipation Rated DC Reverse oltage rward Current Junction Temperature D = 5, CIN = 5 600 75 50 300 600 75 ~ +50 W CONTROL PRT Ratings D Supply oltage pplied between : UP-UPC P-PC, WP-WPC, N-NC CIN put oltage pplied between : UP-UPC, P-PC WP-WPC, UN N WN Br-NC FO O Fault Output Supply oltage Fault Output Current pplied between : UFO-UPC, FO-PC, WFO-WPC FO-NC nk current at UFO, FO, WFO, FO terminals m pr. 04
FLT-BSE TYPE INSULTED PCKGE TL SYSTEM Ratings CC(PR) Supply oltage Protected by D = 3.5 ~ 6.5, verter Part, SC Tj = +25 Start 400 CC(surge) TC Tstg iso Supply oltage (Surge) Module Case Operating Temperature Storage Temperature Isolation oltage pplied between : P-N, Surge value 60Hz, nusoidal, Charged part to Base, C min. 500 ~ +00 40 ~ +25 2500 Tc (base plate) measurement point is below. rms B U W Top view N P THERML RESISTNCES Rth(j-c)Q verter part (per /6) (Note-2) 0.* Rth(j-c)F verter part (per /6) (Note-2) 0.33* Rth(j-c)Q Brake part (Note-2) 0.32* Rth(j-c)F Junction to case Thermal Brake part (Note-2) 0.53* Rth(j-c)Q Resistances verter part (per /6) 0.26 Rth(j-c)F verter part (per /6) 0.43 /W Rth(j-c)Q Brake part 0.42 Rth(j-c)F Brake part 0.69 Rth(c-f) Contact Thermal Resistance Case to fin, (per module) Thermal grease applied 0.038 * If you use this value, Rth(f-a) should be measured just under the chips. (Note-2) Tc (under the chip) measurement point is below. axis X Y arm 28.3 7.7 UP 28.3 65.0 7.7 P WP UN N WN Br 65.0 87.0 7.7 87.0 Tc 39.3 5.7 39.3 4.4 54.0 5.7 54.0 4.4 76.0 5.7 76.0 4.4 8. 0.5 (unit : mm) 8. 4.0 Bottom view ELECTRICL CHRCTERISTICS (Tj = 25, unless otherwise noted) INERTER PRT CE(sat) EC ton trr tc(on) toff tc(off) ICES Saturation oltage rward oltage Switching Time Cutoff Current D = 5, IC = 50 Tj = 25 CIN = 0, Pulsed (Fig. ) Tj = 25 IC = 50, D = 5, CIN = 5 (Fig. 2) D = 5, CIN = 0 5 CC = 300, IC = 50 Tj = 25 ductive Load (Fig. 3,4) CE = CES, CIN = 5 (Fig. 5) Tj = 25 Tj = 25 0.5.6 2.2.0 0.2 0.4.2 0.5 2. 2.0 3.3 0.4.0 2.5.0 0 µs m pr. 04
FLT-BSE TYPE INSULTED PCKGE BRKE PRT CE(sat) FM ICES Saturation oltage rward oltage Cutoff Current D = 5, IC = 75 Tj = 25 CIN = 0, Pulsed (Fig. ) Tj = 25 = 75 CE = CES, CIN = 5 (Fig. 5) (Fig. 2) Tj = 25 Tj = 25.6 2.2 2. 2.0 3.3 0 m CONTROL PRT ID th(on) th(off) SC toff(sc) r U Ur O(H) O(L) tfo Circuit Current put ON Threshold oltage put OFF Threshold oltage Short Circuit Trip Level Short Circuit Current Delay Time Over Temperature Protection Supply Circuit Under-oltage Protection Fault Output Current Minimum Fault Output Pulse Width D = 5, CIN = 5 pplied between : UP-UPC, P-PC, WP-WPC UN N WN Br-NC Tj 25, D = 5 (Fig. 3,6) D = 5 Detect Tj of chip Tj 25 D = 5, FO = 5 D = 5 N-NC XP-XPC verter part Brake part D = 5 (Fig. 3,6) Trip level Reset level Trip level Reset level (Note-3) (Note-3) Min..2.7 300 50 35.0 Typ. 5 2.0 (Note-3) Fault output is given only when the internal SC, & U protections schemes of either upper or lower arm device operate to protect it. 0.2 45 25 2.0 2.5 0.8 Max. 30 0.8 2.3 2.5 0.0 5 m µs m ms MECHNICL RTINGS ND CHRCTERISTICS Mounting torque Weight Mounting part screw : M5 2.5 3.0 340 3.5 N m g RECOMMENDED CONDITIONS FOR USE CC D CIN(ON) CIN(OFF) Supply oltage Control Supply oltage put ON oltage put OFF oltage pplied across P-N terminals pplied between : UP-UPC, P-PC WP-WPC, N-NC pplied between : UP-UPC, P-PC, WP-WPC UN N WN Br-NC (Note-4) Recommended value 400 5 ± 0.8 9.0 fpwm PWM put Frequency Using pplication Circuit of Fig. 8 khz rm Shoot-through Blocking Time r IPM s each input signals (Fig. 7) 2.0 µs (Note-4) With ripple satisfying the following conditions dv/dt swing ±5/µs, ariation 2 peak to peak pr. 04
FLT-BSE TYPE INSULTED PCKGE PRECUTIONS FOR TESTING. Before appling any control supply voltage (D), the input terminals should be pulled up by resistores, etc. to their corresponding supply voltage and each input signal should be kept off state. fter this, the specified ON and OFF level setting for each input signal should be done. 2. When performing SC tests, the turn-off surge voltage spike at the corresponding protection operation should not be allowed to rise above CES rating of the device. (These test should not be done by using a curve tracer or its equivalent.) P, (U,,W,B) P, (U,,W) CIN (0) IN CIN (5) IN U,,W, (N) D (all) Fig. CE(sat) Test U,,W,B, (N) D (all) Fig. 2 EC, (FM) Test a) Lower rm Switching P CIN (5) CIN gnal input (Upper rm) gnal input (Lower rm) U,,W CS cc 90% trr Irr 90% CE b) Upper rm Switching CIN CIN (5) gnal input (Upper rm) gnal input (Lower rm) D (all) D (all) N P U,,W Fig. 3 Switching time and SC test circuit N CS cc 0% 0% 0% 0% tc(on) tc(off) CIN td(on) tr td(off) tf (ton= td(on) + tr) (toff= td(off) + tf) Fig. 4 Switching time test waveform CIN Short Circuit Current P, (U,,W,B) Constant Current CIN (5) IN Pulse CE SC D (all) U,,W, (N) Fig. 5 ICES Test toff(sc) Fig. 6 SC test waveform IPM input signal CIN (Upper rm) 0 2 t IPM input signal CIN (Lower rm) 0 2 2 t : put on threshold voltage th(on) typical value, 2: put off threshold voltage th(off) typical value Fig. 7 Dead time measurement point example pr. 04
FLT-BSE TYPE INSULTED PCKGE P D D kω 0µ UP UP UPC P P PC cc cc U + M D kω 0µ WP WP WPC UN cc cc W N kω 0µ N cc D kω 0µ N WN cc 4.7kΩ NC Br cc B 5 kω : terface which is the same as the U-phase Fig. 8 pplication Example Circuit NES FOR STBLE ND SFE OPERTION ; Design the PCB pattern to minimize wiring length between opto-coupler and IPM s input terminal, and also to minimize the stray capacity between the input and output wirings of opto-coupler. Connect low impedance capacitor between the cc and GND terminal of each fast switching opto-coupler. Fast switching opto-couplers: tplh, tphl 0.8µs, Use High CMR type. Slow switching opto-coupler: CTR > 00% Use 4 isolated control power supplies (D). lso, care should be taken to minimize the instantaneous voltage charge of the power supply. Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N terminal. Use line noise filter capacitor (ex. 4.7nF) between each input C line and ground to reject common-mode noise from C line and improve noise immunity of the system. pr. 04