Contents Preface List of trademarks xi xv Introduction and Overview of the Book WHY ARE CUSTOM CIRCUITS SO MUCH FASTER? WHO SHOULD CARE? DEFINITIONS: ASIC, CUSTOM, ETC. THE 35,000 FOOT VIEW: WHY IS CUSTOM FASTER? MICROARCHITECTURE TIMING OVERHEAD: CLOCK TREE DESIGN AND REGISTERS LOGIC STYLE 8. LOGIC DESIGN 9. CELL DESIGN AND WIRE SIZING 0. LAYOUT: FLOORPLANNING AND PLACEMENT TO MANAGE WIRES PROCESS VARIATION AND IMPROVEMENT SUMMARY AND WHAT S NOT IN THE BOOK ORGANIZATION OF THE REST OF THE BOOK 3 4 9 2 5 7 8 20 22 26 28 28 CONTRIBUTING FACTORS Improving Performance through Microarchitecture EXAMPLES OF MICRO ARCHITECTURAL TECHNIQUES TO INCREASE SPEED MEMORY ACCESS TIME AND THE CLOCK PERIOD SPEEDUP FROM PIPELINING Reducing the Timing Overhead CHARACTERISTICS OF SYNCHRONOUS SEQUENTIAL LOGIC 33 34 44 45 57 58
vi Contents EXAMPLE WHERE LATCHES ARE FASTER OPTIMAL LATCH POSITIONS WITH TWO CLOCK PHASES EXAMPLE WHERE LATCHES ARE SLOWER PIPELINE DELAY WITH LATCHES VS. PIPELINE DELAY WITH FLIP-FLOPS CUSTOM VERSUS ASIC TIMING OVERHEAD 77 8 83 87 90 High-Speed Logic, Circuits, Libraries and Layout Andrew Chang, William J. Dally Stanford University David Chinnery, Kurt Keutzer, Radu Zlatanovici UC Berkeley TECHNOLOGY INDEPENDENT METRICS PERFORMANCE PENALTIES IN ASIC DESIGNS FROM LOGIC STYLE, LOGIC DESIGN, CELL DESIGN, AND LAYOUT COMPARISON OF ASIC AND CUSTOM CELL AREAS ENERGY TRADEOFFS BETWEEN ASIC CELLS AND CUSTOM CELLS FUTURE TRENDS SUMMARY Finding Peak Performance in a Process PROCESS AND OPERATING CONDITIONS CHIP SPEED VARIATION DUE TO STATISTICAL PROCESS VARIATION CONTINUOUS PROCESS IMPROVEMENT SPEED DIFFERENCES DUE TO ALTERNATIVE PROCESS IMPLEMENTATIONS PROCESS TECHNOLOGY FOR ASICS POTENTIAL IMPROVEMENTS FOR ASICS 0 0 02 08 29 34 38 39 45 46 55 57 59 6 64 DESIGN TECHNIQUES Physical Prototyping Plans for High Performance Michel Courtoy, Pinhong Chen, Xiaoping Tang, Chin-Chi Teng, Yuji Kukimoto Silicon Perspective, a Cadence Company FLOORPLANNING PHYSICAL PROTOTYPING 69 69 70 72
TECHNIQUES IN PHYSICAL PROTOTYPING 80 85 vii 8. 9. Automatic Replacement of Flip-Flops by Latches in ASICs Jagesh Sanghavi, Earl Killian, Kaushik Sheth Tensilica THEORY ALGORITHM RESULTS CONCLUSION Useful-Skew Clock Synthesis Boosts ASIC Performance Wayne Dai UC Santa Cruz David Staepelaere Celestry Design Technologies 8. 9. IS CLOCK SKEW REALLY GLOBAL? PERMISSIBLE RANGE SKEW CONSTRAINTS WHY CLOCK SKEW MAY BE USEFUL USEFUL SKEW DESIGN METHODOLOGY USEFUL SKEW CASE STUDY CLOCK AND LOGIC CO-DESIGN SIMULTANEOUS CLOCK SKEW OPTIMIZATION AND GATE SIZING CONCLUSION Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing Michel Côté, Philippe Hurat Cadabra, a Numerical Technologies Company OPTIMIZED CELLS FOR BETTER POWER AND PERFORMANCE PPO FLOW PPO EXAMPLES FLOW CHALLENGES AND ADOPTION 87 87 9 99 203 207 209 209 20 2 23 26 28 220 220 22 225 225 226 228 235 238 239 0. Design Optimization with Automated Flex-Cell Creation Debashis Bhattacharya, Vamsi Boppana Zenasis Technologies FLEX-CELL BASED OPTIMIZATION OVERVIEW MINIMIZING THE NUMBER OF NEW FLEX-CELLS CREATED 24 244 249
viii CELL LAYOUT SYNTHESIS IN FLEX-CELL BASED OPTIMIZATION GREATER PERFORMANCE THROUGH BETTER CHARACTERIZATION PHYSICAL DESIGN AND FLEX-CELL BASED OPTIMIZATION CASE STUDIES WITH RESULTS Contents 254 255 259 26 266 Exploiting Structure and Managing Wires to Increase Density and Performance Andrew Chang, William J. Dally Stanford University INHERENT DESIGN STRUCTURE SUCCESSIVE CUSTOM TECHNIQUES FOR EXPLOITING STRUCTURE FUTURE DIRECTIONS SUMMARY Semi-Custom Methods in a High-Performance Microprocessor Design Gregory A. Northrop IBM CUSTOM PROCESSOR DESIGN SEMI-CUSTOM DEISGN FLOW DESIGN EXAMPLE 24 BIT ADDER OVERALL IMPACT ON CHIP DESIGN Controlling Uncertainty in High Frequency Designs Stephen E. Rich, Matthew J. Parker, Jim Schwartz Intel FREQUENCY TERMINOLOGY UNCERTAINTY DEFINED WHY UNCERTAINTY REDUCES THE MAXIMUM POSSIBLE FREQUENCY PRACTICAL EXAMPLE OF TOOL UNCERTAINTY FOCUSED METHODOLOGY DEVELOPMENT METHODS FOR REMOVING PATHS FROM THE UNCERTAINTY WINDOW 8. THE UNCERTAINTY LIFECYCLE 9. CONCLUSION 269 269 27 285 285 289 289 290 29 297 300 306 309 32 34 35 37 32
ix Increasing Circuit Performance through Statistical Design Techniques Michael Orshansky UC Berkeley PROCESS VARIABILITY AND ITS IMPACT ON TIMING INCREASING PERFORMANCE THROUGH PROBABILISTIC TIMING MODELING INCREASING PERFORMANCE THROUGH DESIGN FOR MANUFACTURABILITY TECHNIQUES ACCOUNTING FOR IMPACT OF GATE LENGTH VARIATION ON CIRCUIT PERFORMANCE: A CASE STUDY CONCLUSION 323 324 329 334 338 342 DESIGN EXAMPLES Achieving 550MHz in a Standard Cell ASIC Methodology David Chinnery, Kurt Keutzer UC Berkeley A DESIGN BRIDGING THE SPEED GAP BETWEEN ASIC AND CUSTOM MICROARCHITECTURE: PIPELINING AND LOGIC DESIGN REGISTER DESIGN CLOCK TREE INSERTION AND CLOCK DISTRIBUTION CUSTOM LOGIC VERSUS SYNTHESIS REDUCING UNCERTAINTY 8. SUMMARY AND The icore 520MHz Synthesizable CPU Core Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni STMicroelectronics OPTIMIZING THE MICROARCHITECTURE OPTIMIZING THE IMPLEMENTATION PHYSICAL DESIGN STRATEGY RESULTS 345 345 346 348 353 356 357 358 358 36 36 363 375 378 379 380